DD289609A5 - METHOD AND CIRCUIT ARRANGEMENT FOR DATA COMPRESSION - Google Patents

Abstract

The invention relates to a method and a circuit arrangement for data compression, which are applicable for checking digital Datenstroeme with required high error detection probability. The object of the invention is an increase in the probability of error detection while preserving the known positive characteristics of data compression methods based on the signature analysis. A method for data compression based on signature analysis using an n-digit signature register is proposed. According to the invention, the data stream to be analyzed is decoupled from the signature register in parallel at m locations, the data stream is then compared in the clock raster with a programmed m-bit-wide mask, and the resulting comparison result is passed to a counter. At the conclusion of the examination, the actual content of the counting device is evaluated. Fig. 1 {complex digital circuit; Self-test; Compact test; Data compression; Signature analysis; Error detection probability; masking; counting operation; Signature register}

Description

For this 1 page drawing

Field of application of the invention

The invention relates to a method and a circuit arrangement for data compression, which are applicable to the testing of digital data streams with required high error detection probability and are preferably used in compact and self-test in the examination of complex digital circuits in different phases of life and different functional environment.

Characteristic of the known state of the art

For testing complex digital circuits, compact and self-test methods are becoming increasingly popular.

The circuit to be tested is stimulated on the input side with certain test sets; The test data sequences appearing as an output-side reaction are now each not directly compared with a desired data sequence corresponding to the error-free circuit, but are compressed by being mapped onto a license plate with a considerably smaller amount of information.

In data compression, two basic techniques are well known.

Syndrome compression, which is realized as enumeration, transition counting, with Walsh spectral coefficients, etc., are non-linear operations in which the division of the test data sequences occurs in unequal sections due to the relatively poor error detection properties and the considerable Hardware overheads remain limited to exceptions to their pure applications.

As a preferred method, the signature analysis ("polynomial division") has prevailed.In contrast to the counting techniques are linear operations.

The method of signature analysis was first described in Frohwerk, R.A .: Signature Analysis: A New Digital Field Service Method. Hewlett-Packard Journal; May 1977; Pp. 2-8.

In the signature analysis, the respective test data sequence is mapped to the state vector of a signature analyzer, the corresponding signature. In this case, the rest of the data stream after division by an irreducible polynomial is understood as the signature.

If one defines a setpoint test data sequence with an associated setpoint signature for an error-free test object, all signatures deviating from it indicate an error in the test object.

The result "test object error-free" or "test object faulty" is formed by comparing the signature obtained with a corresponding reference pattern in a comparison circuit.

The error detection probability of the signature analysis is realtively high and is included

with n ... length of the shift register

t ... bit length of the data stream to be analyzed ·

Single bit errors are detected with 100% probability. For multi-bit errors, the error detection probability is lower, since a following error can change the signature so that the influence of the first (detected) error is compensated and both errors result in a co-operative "error-free" signature Linear feedback shift registers are well known (see, for example, Japanese Patent No. 2538651, U.S. Patent No. 4,320,509, U.S. Patent No. 4,597,080).

In this case, a shift register formed from η memory cells by serial interconnection is coupled out at outputs determined by the selected feedback polynomial. These outputs are linked via a modulo-2-adder (EXOR) and the output of the modulo-2-adder is fed to the input of the first memory cell. In addition, a nonlinear component may be implemented in the linear feedback (see de Visme, G.H .: Binary Sequences, The English Universities Press Ltd, London, 1971).

There is no known algorithm that specifies the construction of a one-to-one mapping register for all conceivable errors in any binary sequence.

In "Simultaneous Signature and Syndrome Compression" (May 1988; Vol. 7; p.584-590), JP Robinson and NR Saxena disclose a data compression method that combines signature analysis and counting (enumeration / transition counting), d, h parallel, used.

Thus, it is noted that a data stream having a signature equal to the target signature does not uniquely have the same number of ones as the valid target data string.

The result is an improvement in the false-detection truthfulness by reducing the error coverage due to the complementary effect of the two compression techniques.

But also in this way it is not possible to increase the error detection probability to one. The decisive disadvantage of the method according to Robinson and Saxena is that the internal logical context of the data sequence to be compressed, d.i. the temporal and local context of the occurrence of certain bit patterns, is ignored. Furthermore, the character of the data sequences to be analyzed can hardly be considered by simple counting operations.

Object of the invention

The object of the invention is to increase the probability of error detection in the compression of data in conjunction with low Hardwareovehead and little additional software effort, without increasing the test time, and ensuring compatibility with classical signature analysis and an excellent self-test suitability.

Explanation of the essence of the invention

The invention has for its object to develop a usable for the self-test and compact test of complex digital circuits method for data compression and in its realization a circuit arrangement in which respects the temporal and local context of the occurrence of certain bit patterns and it becomes possible to the character of to be tested data sequences by process or circuitry configuration to better match.

To achieve the object, a method for data compression based on the signature analysis using an n-digit signature register is proposed. According to the invention, the data stream to be analyzed is decoupled from the signature register in parallel at m locations. The data stream is then compared in the clock grid with a programmed m-bit mask. The obtained comparison result is passed to a counter. At the end of the test, the actual content of the counter is evaluated.

In a preferred embodiment of the invention, the distance between the m elements of the mask is 0 <k £ η - 2.

In a further embodiment variant of the invention, an actual content that can be easily checked is preferably reached from a preset state of the counter by incrementing / decrementing.

In a further embodiment, the actual content of the counter is compared with a desired value at the end of the test.

Alternatively, in another embodiment of the invention, at the end of the examination, the actual content of the counter is inserted into a linear feedback shift register, a final actual signature is formed and then compared with a desired signature.

In this case, the signature register itself or an additional verifiable register is used as the linear feedback shift register.

To solve the problem, a circuit arrangement for data compression is further proposed, which contains a signature register of η register cells, on which at least one input of the circuit is guided.

According to the invention, the outputs of the ith register cells (with 0 <i <n) of the signature register are routed to the m inputs of a combinatorial network serving as a mask. The network has m outputs which are connected to the m inputs of a logic element assigned to them. The output of the logic element is connected to an input of a counter.

An output of this counter represents an output of the circuit arrangement.

From the said register cells, the current content is coupled out in parallel. Each of these bits is fed to a specified input of the combinatorial network. Its outputs are summarized by the logic element.

The combinatorial network and the logic element are constructed and interconnected so that precisely when the content of the combinatorial network representing the mask corresponds to the bits coupled out of the signature register, a given logical value is generated and passed to the counter, the content of which changes becomes.

The elements of the mask are freely positionable and programmable, so that the character of the test sequence can be better met.

The inventive solution realized in the data compression, that the temporal and local context of the occurrence of certain bit patterns is considered.

Compared with the known data compression methods based on the signature analysis, it achieves a significantly higher error detection probability in the analyzed data stream.

By suitable choice of the decoupling points as well as the mask content, the character of the masking can be adapted to the sequence to be analyzed. Thus, the error detection probability can be further increased.

The benefits of signature analysis, such as ease of implementation, low overhead, and good adaptability, remain unchanged. There is no increase in the test time.

The solution according to the invention is clearly compatible with the classical signature analysis, already existing signature analysis arrangements can be easily retrofitted. It is suitable for the self-test.

Execution Abel Game

The invention is explained below with reference to an embodiment and a drawing. It shows

Fig. 1: the circuit arrangement according to the invention.

According to the method according to the invention, which uses an n-digit signature register 1, the test data sequence to be analyzed is decoupled from the signature register 1 in parallel at m locations. The data sequence is then compared in the clock grid with a programmed m-bit-wide mask 5 and passed the resulting comparison result of a counter 10. If the result is positive, the counter 10 is incremented. At the end of the test, the actual content of the counter 10 is compared with a desired value and from this the test result "circuit error-free" or "circuit defective" derived.

In the following, the circuit arrangement according to the invention will be explained with reference to FIG.

As shown, it has a data input IN and a data output OUT. It contains an eight-bit wide signature register 1, which is designed as a linear feedback shift register 2. The shift register 2 consists of eight serially connected register cells 2.1. 2.8. In this case, the data output of a register cell 2.i (with i = 1... 7) is routed to the data input of the subsequent register cell 2.i + 1. The outputs of the selected from the selected feedback polynomial register cells 2.1; 2.8 are placed on the inputs of an EXOR gate 3. Another input of the EXOR gate 3 is connected to the data input IN of the circuit arrangement. EXOR gate 3: aalizes the modulo 2 link of the values at its input. The output of the EXOR gate i is connected to the data input of the first register cell 2.1, d. H.

the input of the shift register 2, guided.

Furthermore, the outputs of the register cells are 2.2; 2.4; 2.6; 2.8 placed on the inputs 4.1 ... 4.4 serving as a mask combinatorial network 5. The network 5 carries the outputs 6.1 ... 6.4.

Within the network 5, its input 4.1 is connected directly to the output 6.1 and the input 4.3 to the input 6.3. The input 4.2 is routed via an inverter 5.1 to the output 6.2 and the input 4.4 via the inverter 5.2 to the output 6.4 of the network 5.

The outputs 6.1 ... 6.4 of the network 5 are each applied to the inputs 7.1 ... 7.4 of a logic element 8. This is designed as an AND gate 8 and has an output. 9

The output 9 of the AND gate 8 is connected to the input (10) of an incrementing counter 11 whose output represents the output OUT of the circuit arrangement.

The test data are from the mentioned register cells 2.2; 2.4; 2.6; 2.8 coupled in parallel and to the inputs 4.1; 4.2; 4.3; 4.4 of the network 5 laid. Within the network 5, the logical values from the register cells 2.4 and 2.8 unchanged to the associated outputs 6.2; 6.4 transfer. The values from the register cells 2.2; 2.6 are each inverted over their respective negator 5.1 or 5.2 to the associated outputs 6.1; 6.3 led. The output values of the network 5 are combined via the AND gate 8.

If the data sequence [X0X1X0X1J (arbitrary with X ... any) is present in the signature register 1, the logical values "1" appear at the outputs 6.1 ... 6.4 AND-linked in the AND gate 8, the value "1" appears at the output 9 of the AND gate 8 and is located at the input 10 of the payer 11. The counter 11 increments, d. H. its actual content increases by "1".

At the conclusion of the test, the actual content of the counter 11 is compared with a setpoint value formed in advance for a fault-free test object. All deviations of the actual content from the setpoint indicate an error in the test object.

Claims (8)

1. A method for data compression on the basis of the signature analysis using an n-digit signature register, characterized in that a data stream to be analyzed is decoupled from the signature register (1) in parallel at m locations, that this then spread in the clock grid with a programmed m bits Mask (5) is compared, that the obtained comparison result of a counter (11) handed over and that the actual content of the counter (11) is evaluated at the conclusion of the test. 2. The method according to claim 1, characterized in that the distance between the m elements of the mask (5) 0 <k <η - 2. 3. The method according to claim 1 or 2, characterized in that from a preset state of the counter (11) by incrementing / decrementing an easy-to-check actual content is achieved. 4. The method according to any one of claims 1 to 3, characterized in that at the conclusion of the test, the actual content of the counter (11) is compared with a desired value. 5. The method according to any one of claims 1 to 3, characterized in that at the conclusion of the examination of the actual contents of the counter (11) inserted into a linear feedback shift register we 1, that a final actual signature formed and that this with a target signature is compared. 6. The method according to claim 5, characterized in that at the end of the examination of the actual content of the counter (11) is inserted into the signature register (1). 7. The method according to claim 5, characterized in that at the end of the examination of the actual content of the counter (11) is inserted into an additional verifiable register. 8. Circuit arrangement for data compression comprising a signature register of η register cells, to which at least one input of the circuit arrangement is guided, characterized in that the outputs of the ith register cells (2.1 ... 2.n, withO <i <n) of the signature register (1) on the m inputs (4.1 ... 4.m) of a combinatorial network (5) serving as a mask, that the m outputs (6.1 ... 6.m) of the combinatorial network (5) to the m Inputs (7.1 ... 7.m) of a logic element (8) are placed such that the output (9) of the logic element (8) is connected to an input (10) of a counter (11) and an output of the counter (11) represents an output (OUT) of the circuit arrangement.