DD289149A5 - METHOD AND CIRCUIT FOR QUICK STORAGE AND EVALUATION OF NON-SYNCHRONOUS SIGNALS IN A MULTI-COMPUTER SYSTEM - Google Patents

Abstract

The invention relates to a method and circuit arrangement for fast storage and evaluation of non-synchronous signals in a multi-computer system, wherein these are detected by a direct memory access. The features of the invention are that the signals acquired from the direct memory access are compared with data from masked data, the read-in cycle of the signal to be stored being determined by a variable clock cycle and an event-related trigger pulse, respectively Additional data storage and retrieval is divided into two and done separately. By the mask signal formed on the one hand, the control of the addressing and thus the mutual setting of the additional storage and on the other hand, the signal activation enabled to Prozeszrechner, whereby an immediate reading and evaluating the data content of the additional storage can be made. With the reading of Prozeszrechner a free message of the additional storage is signaled and thus a non-synchronous clock cycle realized by the write-in signal. In terms of circuit technology, the additional memory blocks each have two switchable address busses, which allow the memory blocks to be set in the sequence with the data or to query the data via the processor bus. FIG {Speicherbloecke; selectable address reports; Adreszlogik; mask-controlled signals}

Description

Field of application of the invention

The invention relates to a method and a circuit arrangement for fast storage and evaluation of non-synchronous signals in a multi-computer system taking into account a direct memory access. The solution according to the invention can be used for detecting process data which can only be detected by the direct memory access through its rapidity of the sequence or whose registration cycle is controlled by non-synchronous event-dependent trigger pulses, but the data content must be detected immediately by the process computer for controlling the process. By using the solution according to the invention, a problem-free immediate data evaluation is possible, since this can be done in parallel to the data registration, but the data acquisition is not affected even in the direct memory access.

Characteristic of the known state of the art

In the process control, the multi-computer coupling occupies an excellent place. There are many suggestions for synchronizing computer systems. For example, in DE-OS 3431169 the signals are detected and replaced by synchronization of a computer system with another. The disadvantage of this solution is that the overall data acquisition system consisting of both computers becomes slower than the slowest imaginable system. An undisturbed direct memory access for the non-synchronous data acquisition can not be realized by means of this solution. In DE-OS 3716506 a method is described which allows the access of two computers to a common memory. Also in this method, the control of the read-write cycle is realized in the waiting process. The mutual subordination of the computers also does not allow an undisturbed dire (direct memory access.) A direct write-in can not be realized in the DMA procedure for the second computer either time-critical process data are not detected in these methods, or the evaluation of the data can only after a large time shift

Object of the invention

The solution according to the invention is intended to enable the immediate storage and evaluation of non-synchronous process data acquired by direct access. The evaluation should be done by a process computer, which is not synchronized with the process of data acquisition. Furthermore, the process computer should be able to statistically monitor the process by time-synchronous querying of data blocks. In addition, the additional call-up of the measuring positions required for the necessary individual detection should be omitted. The thus saved computing time can be used to specialize the process control or to take over control of other processes.

Explanation of the essence of the invention

The invention has for its object to provide a method and a circuit arrangement for fast storage and evaluation of non-synchronous signals in a multi-computer system in which a fast non-synchronous process data acquisition can take place and the process data can be fed to the process computer for controlling the process according to certain selection criteria. At the same time, the statistical data should be compressed and the possibility created to provide this data to the computer time-synchronized in larger amounts of data available. According to the invention, this object is achieved in that the data acquired by the direct memory access are compared with masked data. If the values match, there is a two-part additional storage of data. The two-part additional storage can receive alternately influenced by the process computer write and read commands. By addressing it is ensured that the additional stored data after reading into the process computer include the entire record, so that no data loss caused by synchronization errors and the process computer is thus able to read in the data acquisition phase in the direct memory access data and already Issue commands that affect the process at this time. The evaluation of the comparison with the masked data causes inequality no call to the process computer, so that the process computer, the data collected in the main memory data can be read non-time critical.

The circuit arrangement for carrying out the method according to the invention consists in the fact that the measured value is connected via a erstan control bus with an address logic, the address logic is connected via a third and fourth address bus to the main memory blocks and that the measured value detection via a second data bus connected to a comparator unit which simultaneously has a second control bus in connection with the address logic. To the main memory blocks two additional memory blocks are arranged so that a parallel reading of data is possible and that for mutual writing and reading this switching is provided, via one of the additional memory blocks su the address logic out address bus a set or read signal is switched and in that two groups of bus selection circuits are connected to the address logic via a third control bus for the purpose of their activation or blocking. Another data bus is connected on the one hand to the output of the comparator unit and on the other hand to the other input of the first group of bus selection circuits whose outputs are connected via further data buses to the inputs of the second group of bus selection circuits. This second group of bus selection circuits is connected via its output via a further data bus to the process computer, wherein the fourth or fifth data bus is simultaneously with the first and second auxiliary memory block and the sixth or seventh data bus with the respective main memory block in combination. When the address logic is activated via a further control bus, a read request is output to the process computer, whereby at the same time the corresponding bus selection circuit (fifth to eighth) can be connected via the third control bus, so that data can be fed to the process computer via a corresponding data bus.

embodiment

The inventive method will be described in more detail with reference to a circuit arrangement. The circuit arrangement shows that DB 1 is written into the measured value acquisition 1 via the data bus. The measured value acquisition is connected to the address logic 2 via a control bus SB 1. This provides the addresses for the continuous data acquisition in the main memory blocks M 3 and M 4. The main memory blocks M 3 and M 4 are connected to the address logic 2 via the address bus AB 3 and AB 4. The data from the measured value acquisition are routed via the data bus DB 2 to the comparator unit 3. In this, the comparison is made with the values typical for the process, which are stored in the form of masks in the comparator unit 3. If equality is detected between the mask values and the input data, the comparator unit 3 sends a control command to the address logic 2 via the control bus SB 3. From this, when these states are reached, the additional memory blocks M 1 or M 2 are routed via the address bus AB 1 and AB 2 Sit-or. Read signal given. The enable or disable signal for the bus selection circuits BA 1 to BA 8 (with the data bus inputs DB 3 to DB 7) is synchronized with the address switching. The bus select circuits are activated or disabled via the control bus SB 2. If the address logic 2 is activated by control signals from the comparator unit 3, a read request is sent to the process computer 4 via the control bus SB 4. With the read request, one of the bus selection circuits BA 5 to BA 8 is simultaneously enabled by the address logic 2 via the control bus SB 3. so that the process computer 4 via the data bus DB 8 can receive the corresponding data without the write command is disturbed in the direct memory access. The arrangement of the main memory blocks M 3 and M 4 with possible mutual read and write controls is done according to the known prior art and serves to limit the memory size of these main memory blocks M 3 and M 4.

Claims (4)

1. A method for fast storage and evaluation of non-synchronous signals in a multi-computer system, which are detected by a direct memory access and are fed to the process computer for controlling processes according to certain selection criteria, characterized in that the detected by the direct memory access signals of data with Masked data are compared, wherein the read-in cycle of the signal to be stored by a variable clock cycle or by an event trigger pulse is determined and that when a match of the data additional data storage is parallel to the main storage, the additional data storage is divided into two parts and that the writing in alternation happens and after each write cycle, a change can take place within the additional storage and that by switching to describing the first additional storage, the second additional storage is described and that the first additional storage is released for immediate reading and that after reading this an immediate re-description can be done and the second additional storage is read and that not only the control of the addressing and thus the mutual setting of the respective additional storage is initiated by a mask signal, but that a Signal activation to the process computer can be done and thus the immediate reading and evaluating the data content of the additional storage happens that by reading from the process computer fro a free message of additional storage is signaled to realize a non-synchronous clock cycle by the write-in, and that the additional storage via switchable addresses which make it possible to make the additional storage in the sequence with the data settable or query corresponding data. 2. Circuit arrangement for fast storage and evaluation of non-synchronous signals in a multi-computer system, which are detected by a direct memory access, with main memory blocks and corresponding mutually-operating write and read drives, in which the buses of the individual computer units via interface and control circuit with a bus selector are connected, characterized in that the measured value acquisition (1) via a control bus (SB 1) with an address logic (2) is connected, wherein the address logic (2) via address buses (AB 3, AB 4) is in communication with the main memory blocks (M 3, M 4) and that the measured value acquisition (1) via a data bus (DB 2) is connected to a comparator unit (3), which simultaneously via a control bus (SB 2) in connection with the address logic (2) and that the main memory blocks (M 3, M 4) additional memory blocks (M 1, M 2) are assigned so that a parallel reading of data is possible and that for the mutual writing and reading of the additional memory blocks (M 1 and M 2) a switching is provided, wherein one of the additional memory blocks ( M 1 bzw.M 2) to the address logic (2) guided address bus (AB 1 or, AB 2) is a set or read signal is switched and that bus selection circuits (BA 1 to BA 8) via a control bus (SB 3) for the purpose their activation or blocking in conjunction with the address logic (2) and that a data bus (DB 3) on the one hand to the output of the comparator unit (3) and on the other hand to the other input of the bus selection circuits (BA 1 to BA 4) in conjunction and the outputs of which are connected via further data buses (DB 4 to DB 7) to the inputs of the bus selection circuits (BA 5 to BA 8) and the connection between the outputs of the bus selection circuits (BA 5 to BA 8) and the process computer (4) by ei NEN data bus (DB 8) is formed, wherein the data bus (DB 4 or DB 5) simultaneously with the additional memory blocks (M 1 or M 2) and the data bus (DB 8 or DB 7) with the main memory blocks (M 3 or M 4) and that upon activation of the address logic (2) via a further control bus (SB 4) a read request to the Prozeßrecher (4) is passed. For this 1 page drawing