DD282089A5 - MORE COMPUTER ARRANGEMENT - Google Patents

Abstract

The invention relates to a multi-computer arrangement according to the master-slave principle for universal use in decentralized drive systems of Mesz- and Feingeraetetechnik, such. B. Mesz- and Kreuztische, feed units, plotters, robot controls u. ae. According to FIG. 1, a main controller, and an operational memory having a plurality of module computers and a dual-port RAM for each module computer, are coupled via a common system bus. Furthermore, the Zweitorespeicher are connected via a local auxiliary bus with the dazugehoerenden module computers. Each two-port memory is composed of two memory areas. On the one hand, from a memory area which, from the point of view of the main controller, occupies a different section in the overall address space for each module computer and a second memory area which has the same memory addresses for all module computers from the point of view of the main controller. This allows the main controller to communicate either with each module computer individually or with all module computers at the same time, as needed, without an additional I / O address generation. In addition, there is the possibility of direct communication of all module computers with each other. Fig. 1 {multi-computer arrangement; Master-slave principle; Engines; Mesz and Feingeraetetechnik; Mesz- and Kreuztische; Plotter; Robot controls; Two goals memory; dual-port RAM; Main controller; Module computer}

Description

is. U.S. Patent No. 3,551,694 teaches a system in which each processor has its own serial data bus to connect to each device to which data is transferred. Both systems reduce the bus utilization issues because each processor has its own output bus connected to each data destination. The physical connections between the processors are, however, relatively complicated by the large number of data buses. In addition, this system is not particularly well suited to adding more processors, since the data bus must be connected to each pre-sighting device with which it is to communicate. Another way to improve data transfer between multiple processors is shown in US Pat. Nos. 414-9242. It consists of optimizing jodon Prozossor with oinom gomoi.isamen (or two-way) memory, which routes all data transfers to other processors within the system. The advantage of such an architecture is that, after the processing of the portion of the contiguous data by the processor, these data may be stored in the common memory for transfer to another i.t. The source processor can then perform other tasks and there is no delay in that Lr must wait on the bus until it is available to transfer data. Each module has a separate data bus that connects to and communicates with each processor module. In order to avoid the complexity of modem data buses for pre-processor connection, the common memories of the processor modules may be interconnected by an ozone-less system bus. Data transfers between such memories can be made with an additional computer or a central data transfer unit coupled to the system bus. In US-PS 4181936 as -v.> M essay with the title "Dual-port RAM likes throughput in input / output controller board" in the magazine Electronics on 17 August 1978 described configuration, each processor has an input / output section Jodor gemoinsamo memory is associated with a portion of the address space of the system defined by all the memory locations addressable by the add-on, master, or onoron zontralon communication device over the system bus. Since each processor module appears to the system merely as a spoofing block, additional modules may have been added, minimizing the burden on the system's systombus and programming.Each shared (two-way) memory occupies a particular portion of the address space of the system, that is the number dor dom system bus adding boron modulo by don Gosamtadreßraum the additional central processing unit or the master is limited. However, this disadvantage plays almost no role in motor drive systems with central units in 16-bit technology, since the addressable by oinon 16-bit computer storage space is very large in relation to the size of the share of the common Speichor the einzolnen Rechnerermodulo. Furthermore, since each common (two-way) memory has a uniform address block, the additional central unit or the master can only be connected to one memory at a time. For many applications, however, it is desirable to be able to transmit data to mohroro processors at the same time. For this purpose, a multi-computer configuration is proposed in PS DE 3247083.

An advantage of this arrangement is that each common (two-way) memory on the system bus for the main controller or the master has the same addresses. There; means that each memory is assigned to the same section of the address space of the main control line on the system bus. Thus, the shared memories occupy the same amount of address space regardless of the number of memories in the system. Another advantage is that this arrangement provides the ability to simultaneously write information into multiple shared memories.

A major disadvantage of the <n PS 3247083 arrangement shown is that in addition to the Speicheroradreßgenierung generation of at least one selection signal or dio generation at least one additional address for the respective module or modules is required that hoißt in the program need to additional commands been processed. As a result, this type of selection of the modules is unfavorable for real-time critical programs. Furthermore, extensive additional hardware is needed to control this module disruption. A woicherer disadvantage is that a direct Kummunikation between two modules without the main control or the master banuuen is not possible. Often, however, direct communication between module computers is required, e.g. in the case of positioning systems which are intended to realize trajectories realistically, without the circumference via the main control or the master.

Object of the invention

The aim of the invention is to reduce the Systombusbolegungszoit each other in a multi-computer arrangement by improving the Datonaustauschbedingungen and minimizing doj effort for don't data provision between the master and the slaves or don slaves and thus to increase the performance of dioecomputer systems for special control tasks with high real-time requirements.

Explanation of the essence of the invention

The task dor invention is to provide an improved multi-computer configuration that can work with a large number of processors and the simultaneous writing of data in common (two-port) memory allows without having to generate an additional selection signal for dio modules. Furthermore, there should be the possibility that a module computer (slave) can transmit data to other module computers (slaves) without having to use the main controller (master) and their operational memory for buffering.

The distribution of tasks ι. As a positioning on several processors on the one hand oino ensures high performance of the overall system and on the other hand, so that the transparency of implomonton software and the reliability is increased by the creation of redundant redundant functions. According to the invention, the object is achieved by the configuration shown in FIG. A common system bus is used to couple a main controller or a master and an opsiive memory module and a plurality of modulo computers or slaves. Furthermore, there is a two-port memory at the system bridge for each module computer. This two-port memory is with dom Systombus and over a local Nebenbus mi. connected to the associated module computer (slave). Of particular importance st the configuration of the two-port memory and access to it by the main controller and the module computer. To the

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Zwoitorespeicher oinos each Prozossormoduls either the processor of the respective module over its local Nobenbus or the main control (Mastor) over the Systombue access. The shared memory has a logic for granting the access rights necessary to access the two-port memory simultaneously in an attempt of the main controller and the module computers, whereby priorities in attempting concurrent access can be set. Each two-port memory consists of two memory areas, a memory area occupying a different section in the total address space from the main controller's point of view for each module computer and a second memory area consisting of one or more registers from the master bus or system bus point of view for all module computers the same or the same memory addresses bositzon. This has the advantage that an additional I / O Adroßgonoriorung as in dor PS DE 3247083 deleted and with a single Spoichoradroßgenorieru ng directly to the respective memory cell can be accessed, which is particularly important in real-critical programs From the point of view of the module computer is the area the Zwoitorespeicher fostlegbar within dos adressierbaron Gosamtspeicherraumos the respective module computer. Wio already stated, each two-port memory comprises one or more registers within its memory address space, which are made up of de; View of the system bus or the main control unit have the same address. It follows that when addressing this Registoradrosson a simultaneous communication between the main controller and all module computers is possible. Likewise, there is the possibility in this way to perform a direct communication between all the module computers via the system bus, without an additional I / O address generation. A module computer assumes the function of the source computer and all other module computers are receivers. Although this or these registers have all the same memory addresses from the perspective of the main control, they can be freely defined in the overall pouch space. From the point of view of module computers, these registers can be freely set in the memory space of each module. The module computers are also able to use the operating memory located on the system bus via the system bus connection. This type of multicomputer coupling is particularly suitable for real-time systems, such. B. Positioning group.

Ausführungsbelsplel

In the drawings, Figure 1 shows a multi-computer arrangement according to the master-slave principle with a coupling of the master with the slaves via two-port memory and Figure 2 as Ausführungsbeispiol a Positioniorbauciruppe to the described multi-computer arrangement. On a common system bus 1 are an assembly computer 7 (Mastor), a 3 Operativspeicher, ano Intorfacebaugruppe 8, three Achsrechner 9 (slaves) and each Achsrechner 9 each connected to it via a lokalon sub-bus 6 Zweitorespeicher 5. Each Zweitorespeicher 5 is also connected to the system bus 1. Dor Operativspeicher 3 is used only by the module calculator 7. Dio communication between the master 7 and don slaves 9 takes place exclusively via the secondary memory 5. Dio axis computers 9 (slaves) are used for positioning in the X direction, in the Y direction and in direction. Dor module calculator / and all three Achsrechner 9 are constructed identically in terms of hardware, which creates the possibility that each Achsrechner 9 can take over if necessary dio function of Mes'.ors 7. Each axis calculator 9 consists of a central processing unit, oinpm program and data memory and a special input / output module, which forms an interface to the measuring element 10. As measuring elements 10 have been used incrementally Gebor.

Each two-port memory 5 is divided into two memory groups. An urston storage group 5A, consisting of Ί kWorte RAM, occupies from the point of view of the master 7 for each axis calculator 9 another section in the Gesamtadössraum of the memory and a Spoichergruppe 5 B, consisting of 4 bytes, organized into two words, from the point of view of the master 7 for each axis 9 have the same address.

Furthermore, each Zweitorespeicher 5 eino special access logic 5C, which ortst in a possible simultaneous access attempt by Master 7 and Slavo 9 on the common Zwoitorespeicher 5 access rights. Di i module has the task of optimally positioning an object according to a given travel curve. For this purpose, the module computer 7 transmits, via the memory group 5A, the axis computer 9 the orfordorlichen bases for determining their specific driving curves. The axis calculator 9 can then take these from the Zwoitorospeichern 5 after parameter and initial word calculations. After the axle calculator has calculated the travel curves, the module computer 7 describes the registers of the memory group 5B in all the second memories 5 simultaneously with specific word combinations. These serve z. B. the realization of a hochgonauon Fahrkurvo. Dio word register of the memory group 5B t -onnen also for fast transmission of status information by the master 7 or a Slavo 9 to all other laves 9, ζ. B. grazing situations, used grazing. The interface module 8 is used to implement a serial interface 11 to a parent host computer.

Claims (3)

1. Multi-computer arrangement according to the master-slave principle with oin.er main controller and with several connected via a system bus modulators each of which is coupled via a local bus with a ebenfal's connected via the system bus to the master two-store, which is used for communication between the main controller and the module computers or the module computer with each other, characterized in that each Zweitorespeicher (5) has a two-part memory, wherein the first, the individual communication with the main controller (2) or with another module computer (4) serving, memory area (5A) for each second-processor memory (5) another section in the memory address space of Hauptstouerung (2) be'egt and the second, the simultaneous communication of the main controller (2) with all rviodulrechnern (4) and all module computers (4) under einender serving, memory area (5B ) for each two-port memory (5) with respect to the main controller (2) on the system bus (1) a common address block; having. 2. Multi-computer arrangement according to claim 1, characterized in that module computer (4) and main controller (2) are constructed identically. 3. Multi-computer arrangement according to claim 1, characterized in that in each Zweitor9speicher (5) of the zwoite memory area (5 B) is located with its addresses in the input / output address range. For this ? Pages drawings Field of application of the invention The invention relates to a multi-computer arrangement for universal use in decentralized drive systems of the measuring and fine gate technology, such. Measuring and cross tables, feed units, plotters, etc. By virtue of the multicomputer arrangement presented in the invention, a high performance of the recomputation ensures the overall system, which enables the implementation of efficient storage control algorithms with which a precise and highly dynamic positioning of the inserted drives is realized. Dos is also the multi-computer arrangement in all hierarchically organized decentralized control devices, where the task is to process many real-time processes in parallel, at the same time as low as possible load on the system bus, can be used. Characteristic of the known state of the art Drive systems with a single processor, which is often referred to as a central unit, are limited by the size and operating speed of the central unit itself. This is especially true in such drive systems where a central unit must control multiple motors. In order to increase the performance of such Antrifibssysteme various Mohrrechnerkonfigurationen are proposed. Multicomputer configurations are multi-processor systems. A variant consists in that one central unit assumes the function of a master and the other central units represent slaves. From this definition, there are various possibilities for designing the architecture of such an assembly. So one can couple each additional processor (slave) with the system bus, which connects the master with memories and input and output devices. The disadvantage of this arrangement is that each central unit must be competitive with the other central units in accessing the system bus for data exchange with system memory or an input or output device. Another disadvantage is that this principle generally increases the complexity of the programs. Both disadvantages can reduce the operating speed of each central unit. They have particularly severe effects in certain real-time applications such as highly accurate and highly dynamic positioning systems, where often larger amounts of data must be exchanged and processed and greater delays in the real-time processing of critical program sections of the slaves are not allowed by the system bus. Another possibility is to form a single module with each additional central unit. Each module may include direct memory access logic and memory. Thereby ka. ~ R. d ^; e bus occupancy partially reduced. But even here there are still quite considerable delays in the high bus occupancy, which are unacceptable for certain real-time requirements. In order to minimize the Busbelcgung have been proposed various connection principles for processors. For example, US Pat. No. 3,815,095 describes a system in which each processor includes a multiplexer that selectively receives data from multiple data buses, each data bus connected to the output of a processor