DD268306A1 - METHOD AND CIRCUIT ARRANGEMENT FOR CHECKING THE CONNECTING LINES OF MULTICHIP MODULES ARRANGED ON MULTILAYER GUIDE PLATES - Google Patents

Abstract

The invention relates to a method for testing the connecting lines of multichip modules arranged on multilayer printed circuit boards with fitted gate-array circuits and a circuit arrangement for carrying out the method. The invention is characterized in that the multichip modules are electronically separated and subjected to test vectors by means of the test device, wherein the interface drivers of a multichip module carry low signal and the interface drivers of all other multichip modules are controlled with high resistance, and that before each switching to the next Multichip module detection, storage and evaluation of the state information is made. The circuit arrangement is characterized by a control module, which acts on the control lines according to the method. Fig. 1

Description

For this 2 pages drawings

Field of application of the invention

The invention relates to a method for testing the connection lines of multichip modules arranged on multilayer printed circuit boards with equipped gate-array circuits and a circuit arrangement for carrying out the method.

Characteristic of the known state of the art

By using multi-chip modules on printed circuit boards, the packing density has reached a degree which requires the use of more and more complex test methods. In addition to the switching speeds, in the integrated circuits, the number and density of the contact surfaces increase between connecting lines between the gate-array circuits and the multilayer printed circuit board. A multirip module in a flat construction can have on all four sides a multiplicity of connection strips which have to be connected to connection strips of other multichip modules or to the circuit planes of the circuit board, hereafter referred to as MTL. Was it possible with a smaller number of pads to use adapters and probes, a fixation of the probes with a very large number of connecting cords, if at all, can only be realized with an unreasonable economic outlay. From DE-OS 2360762 an elementary circuit arrangement for switching operations for performing data processing operations is known, oei the logical functioning of circuit tiles is checked on a populated circuit board. Each circuit tile can be controlled independently of the others in the operating mode or test mode. However, the inputs and outputs of the circuit board to be tested must be supplied to the tester.

That is, all logic networks of the assembled circuit board must be guided on the connector, or it is resorted to a needle bed adapter. In the latter case, the method corresponds to the in-circuit test. The circuits of DE-OS 2360762 as well as those mentioned in the article by Smith, K .: Scan-path logic integrated on chip test gate array-Electronics 55 (1983), July 28, p. 85 and 86, have testable hardware structures:

!,) All Funktionspflipflops have in addition to the work master and slave work a diagnostic slave and S'nd combined to form a shifter chain. By means of a control voltage, the shifter chain is activated, so that all Fl'pflops can be set by a serial vector. In the same way, the flip-flop states can be output after a successful function clock as a serial result vector.

b) All interface driver stages of the gate arroy circuits, which make the connection between the internal logic and the Scha'txreisrand, by zwoi external control voltages in the states "test high", "test low", "test Tristate" and "work mode" are controlled.

The test data flow takes place from the input terminals and the set flip-flops of the test object (sources) to the output terminals and result flip-flops of the test object (sinks).

The existing between sources and sinks logic can be very complex, so that long test sets are required, which require a high generation cost (computing time) and lead to long test times.

Object of the invention

The aim of the invention is the reduction of the effort for test set generation and the shortening of the test times of gate array assemblies.

Explanation of the essence of the invention

The invention has for its object to perform the MTL test by utilizing an advantageous MCM control in which the individual multichip modules either act as a low source, as a high source or as a receiver and boi are formed by varying these states sensitive paths , which ensure a statement about the functional reliability of the MTL pre-wiring without level conflicts.

According to the invention, the object is achieved by the features specified in the characterizing part of the patent claims. The essence of the invention is that all MCM input / output stages via two interface controllers in the states "working mode" (A = f [E], "test high" (A = "High"), "test low" ( A = "low") and "test Tristade" (A = high impedance) are controllable. The control vector for the inputs of the interface control lines is part of the initialization sequence of the shifter of the gate arrays. The specified circuit arrangement for carrying out the test method allows a simple Schaltungsaufbnu.

embodiment

The invention will be explained in more detail sn an exemplary embodiment. In the drawing show:

1 shows a block diagram of interconnected multichip modules on a multilayer printed circuit board, FIG. 2 shows a circuit arrangement according to the invention for controlling the gate array circuits.

The block diagram in FIG. 1 shows multichip modules MCM1 to MCM 20, which are arranged on a multilayer printed circuit board 1 including their wiring. Each multichip module MCM1 to MCM 20 is connected to data inputs Q1, data outputs Q0, signal lines 2, clock lines CA, CB, mode control lines MT, and interface control lines S, T. The data inputs Ol are coupled to the data outputs QO of the upstream multichip modules MCM1 to MCM20. The beginning of the chain is connected to the terminal SKE and the end of the chain to the terminal SKA. Each multichip module MCM1 to MCM 20 includes β gate array circuits GA1 to GA6, which are also provided with data inputs Ql, data QO, signal lines 2, clock lines CA, CB, mode control lines MT, and interface controllers S, T. In principle, the shutter is identical to that shown in FIG. 1; here too, for example, the data outputs Q0 are coupled to the data inputs Q1 of the following gate-array circuits GA2 to GA6. Minor differences are irrelevant to the invention. By virtue of said wiring, such a diagnostic shifter chain comprises all the circuits of the MTL 1. All the flip-flops of the test object can be made via the terminal SKE and monitored via the terminal SKA. The functional clock of the flip-flops is made available via the clock lines CA, CB. In diagnostic mode (shift) the clock line CA is connected to the clocking of the shifterkotte. Via the mode control lines MT all circuits of the MTL 1 in the function and test mode can be controlled.

2 shows the control module 3 according to the invention, which could be arranged in place of any circuit in the Mu / tichipmodulen MCM1 to MCM 2, but in the example as the last gate array circuit GA6 of the signal chain is used. The Steuorbaugruppe 3 consists of a serial-parallel converter 4 in the form of 40D-Flipflopz 'whose ^E: ngänge D1 connected to D40 to ground potential, the inputs of which are D1 to D40 Blindfolded to ground potential, so that in functional operation of the test object, the interface control vector 000 ... 0 is set automatically and thus interface drive stages assume the working state. The outputs F1 to F40 each lead to an AND gate, the second input of which is in each case connected to the negated .signal from the mode control line MT. The Aubjang of the first AND gate is connected to the interface control lines T of the multi-chip module MCM1. The output of the third JND gate is connected to dr.n interface control lines S of the multichip module MCM 2 and the output of the fourth AND gate is connected to the interface control lines T of the multi-chip module MCM 2. This shading continues up to the multichip module MCM19 in the same way. An exception is the last two outputs. Here, the interface control S, T at the input of the sixth gate array circuit GA6, which is identical to the control module 3, already connected to Massf potential. For this reason, the outputs of the last two AND gates are connected only to the interface lines S, T of the first to fifth gate array circuits GA1... GA5 of the multichip module MCM20.

From Fig. 2 it is ersb'.itlich that the control vector is stored for the interface driver of the gate-array circuits in the D flip-flops. The interconnection of the disturbance vector to the interface control lines S, T of the individual multichip modules MCM1 ... MCM20 takes place with the switchover of the test object from the test mode to the working mode. To test the MTL, an automatic test device is connected to the test object via the information and supply lines. The flip-flops of the test object are combined in ascending order to a shifter chain. By loading with a data vector of length η, all the flip-flops are set to a defined state, with the last ones

40Bit the control vector for the interface state of the multi-chip modules MCM1 ... MCM20. The check now starts, for example, by loading a first vector:

- ^ - ------

, 000 ... 0101111111111111111111111111111111111.

Position vector Master vector for interface drivers; for functio- 40 bit

nice flip flops; n-40 bit

This vector is provided by the testing machine and applied to the diagnostic data input terminal SKE of the test object. In synchronism with the elements of the interface control vector, the tester provides clock pulses which are conducted via the clock line CA of the test object. The mode control MT of the test object is supplied with a low signal. After completion of the charging process, the switching of the mode control line (MT = High), wherein the control vector at the inputs of the interface control lines S, T of the multichip modules MCM1 ... MCM20 is so effective that the interface of all other Muiiichipmodule MCM2 ... MCM20 honhohmigen Take state. At the same time the functional Flirflops have been set to the initial state "Low".

The input terminals u'er MTL signal lines 2 are acted upon by the testing machine, for example, the logic level. Low.

The levels at the output terminals of the MTL interface can now be detected and evaluated by the testing machine. By applying the functional clock pulses (clock lines CB, CA), depending on the effectiveness of this first test assignment, a number of the functional flip-flops dos Prüfobjektes influenced. After switching the mode control to the test mode (MT = High), the resulting result vector can be serially output via the diagnostic output (connector SKA) of the test object and evaluated by the tester. At the same time, the second test vector can be loaded.

This is for example:

_v lll. , . ^ lllOlllllllllllllllllllllllllllllllll ^ Actuator control vector for interface driver

for functional flip-flops

This vector sets all functional flip-flops in the initial state »high * and affects the interface control lines S, T of the multichip modules MCM1 ... MCM 20 such that the interface drivers of the multichip module MCM2 switch to low, while the interface drivers of all other multichip modules assume the high-resistance state. In this test step, the input terminals m of the MTL logic interface can be acted upon, for example, by the automatic tester with the logic level "High." The vector is loaded, the input assignment and the functional clock pulses are loaded, and the test object reaction is evaluated analogously to the first test step.

In this way, further test steps are carried out. As a basic configuration, it makes sense that in each case one multichip module with low or high level drives, while the others receive. The assignment of the input terminals of the MTL logic interface and the initial state of the functional flip-flops are each varied. This results in η 8 test steps, which are generated according to a fixed algorithm. It is also possible that several multichip modules drive simultaneously, possibly also with different levels. By applying a simulation calculation, the admissibility of the individual combination with regard to conflict-free driving levels must be checked.

Claims (4)

1. A method for testing the interconnections of multi-layer printed circuit boards arranged on multi-chip modules with populated gate array circuits, characterized in that the multichip modules (MCM 1 to MCM 20) are electronically separated and supplied with test vectors serially, wherein the interface driver of a multichip module (MCM to MCM 20) to the low signal and the interface drivers of the other multichip modules (MCM 1 to MCM 20) are controlled to high impedance and that prior to each switching to the next multichip module (MCM 1 to MCM 20) a detection, storage and evaluation of the state information is made , 2. Test method according to claim 1, characterized in that successively each a multi-chip module (MCM 1 to MCM 20) drives with a level of the same potential, while the other multichip modules (MCM 1 to MCM 20) are connected as a receiver. 3. Circuit arrangement for testing the connection lines of multichip modules arranged on multilayer printed circuit boards, characterized in that a multichip module (MCM 1 to MCM 20) maintains a control module (3) comprising a serial-to-parallel converter (4) for processing the control vector for the interface drivers whose outputs are connected to the output of an input into the mode control line (MT) negator, and that the data inputs (D 1 to D40) and the two inputs of the interface control lines (S, T) of the control module (3) to ground potential and the outputs the control module (3) are connected to the interface control lines (S, T) of the multichip modules (MCM 1 to MCM19) and the gate array circuits (GA 1 to GA5) of the multichip module (MCM 20). 4. Circuit arrangement according to claim 3, characterized in that the serial-parallel ^ Action mitteis D flip-flops takes place and to link their outputs (F 1 to F40) with the negated mode control signal (/ MT) AND-gates are provided.