DD254077A1 - MICRORECHNER ARRANGEMENT FOR USE IN MULTIMIKRORECHNERSYSTEMEN - Google Patents

Abstract

The invention relates to multi-microcomputer systems for complex control tasks, eg. B. for operating and service processors for computer equipment. The object of the invention is the avoidance of waiting cycles, which arise in the case of internal accesses to storage means, if these are also accessible via the system bus. The solution consists in switching means that preventively trigger requests from the CPU, the triggering then starting when the CPU provides a new address. If there are no higher priority requests, the waiting loop flops are reset immediately before the CPU queries their status. Previously, the position of the waiting flip-flops is evaluated and a valid flip-flop is activated for the duration of the cycle. In the preventive cycles, the control lines of the storage means are more likely to be energized, and the cycle is sooner terminated. Fig. 5

Description

Field of application of the invention

The invention relates to a microcomputer assembly for use in multi-microcomputer systems, which is preferably equipped with dynamic RAMs. Such arrangements are interconnected with each other and with other devices in multi-core computer systems via a common time-division multiplex bus, wherein the memory means, which are preferably equipped with dynamic RAMs, can be accessed both internally by the CPU of the microcomputer array and externally via the time division multiplex bus.

Arrangements of this kind can be used to build relatively complex information processing equipment ^ e.g. peripheral devices for computer equipment, such as operator and service processors, machine controls, etc.

Characteristic of the known technical solutions

Microcomputer arrangements for use in multi-microcomputer systems when connected via a common time-division multiplex bus (system bus) have been known for a long time. It is characteristic that at least certain parts of the memory means of such microcomputer arrangements are accessible both from the own CPU and via the time-multiplexed bus. In the case of the latter accesses, the microcomputer arrangement is addressed as a slave. Furthermore, it is possible that accesses to other devices are actively requested. Then the bus is assigned as master. Suitable bus systems with "multi-master capability" (several devices can alternatively occupy the bus as masters) are described, for example, in the review article "Buses form the backbone of computer systems" (in: Electronic Design 30 [1982] Vol 117-132).

The microcomputers themselves must be equipped with switching and flow control devices to realize the multiple access modes. This is described in detail, for example, in WP 159916 "Microcomputer arrangement, preferably for use in multi-microcomputer systems." Internal accesses to the execution of commands by the CPU are essential for the operating speed of such a microcomputer arrangement Therefore, this will immediately trigger a WAIT signal for the CPU, which will increase the duration of the access for the duration of the excitation, WAIT will not become inactive until Although system access is comparatively rare, WAIT must always be energized to ensure safe operation, and a certain amount of time is needed to decide whether to perform the access or defer in favor of other requests masters The microprocessor CPUs now expect such a decision by querying the WAIT input already shortly after the beginning of the respective access cycle, that is, WAIT must always first be prophylactically energized in order to give the switching circuits time for the decision-making process. This requires at least one clock cycle more per access than would be the case without switching (slowing by about 20-30%). Thus, the potential speed of modern fast microprocessor CPUs (16 or 32 bit processing width) in such microcomputer arrangements is not exploitable. This is critically referred to in the article by JC Mathon, "2nd Generation Bit Microprocessor" (in: Electronics, 29.11.85, pp. 71-81), and a new type of microprocessor is presented in which the corresponding query (instead of WAIT with READY) is shifted in time, so that for the switch a considerable time interval remains, whereby a wait can be avoided in the rule, but now it is hardly possible, especially with the constant Modernisieruang and advancement of complex multi-microcomputer systems, the type Rather, account must be taken of existing (often very extensive) software complexes, so that a specific type of CPU must be maintained in principle.

Object of the invention

The object of the invention is to avoid in microcomputer arrangements, which are intended for use in multi-microcomputer systems, the time losses which occur during internal accesses to storage means, even if these are accessible externally (via the system bus).

Essence of the invention

The object of the invention is a microcomputer arrangement for use in multi-core computer systems in such a way that even when using CPU types that do not have special precautions, waiting cycles are avoided when internal access to memory means, which is also for external access on the part of the System bus are accessible. The disadvantages of known microcomputer arrangements are either that such time losses occur or that specific types of CPU circuits must be used so that existing software is no longer executable. According to the invention the object is achieved by the circuit arrangements specified in the claims. This makes it possible to initiate preventive requirements on the part of the internal CPU for the storage medium in question. The triggering starts at the earliest possible time exactly when the CPU provides a new address. If a corresponding access is mediated (there are no higher-priority requests), the wait-flip-flops, which are excited in a known manner, are immediately reset for internal accesses, even before the CPU queries their status. Previously, the position of these Warteflipflops is evaluated: a set Warteflipflop indicates that the access in question should actually be led to the said storage means. This activates the valid flip-flop for the duration of the cycle. Otherwise, the validity flip-flop remains inactive, so that the executed cycle has no effects. The arrangement of the selection circuits for the memory addresses ensures that preventive for this

the shortest running times are guaranteed (the upstream disjunctive link does not act in the sense of switching until other than the said cycles have been carried out). About the the shift register of the flow control downstream selection circuit is changed in adaptation to the actual time required, the duration of the cycles. In the preventive cycles, the control lines of the storage means are more likely to be energized, and the cycle is also terminated sooner. *

embodiment

In the following embodiment show:

1 shows the block diagram of a microcomputer arrangement designed according to the invention, FIG. 2 shows different register assignments,

3 shows the interpretation of the CPU address,

Fig.4-9: Details of control circuits,

10 shows the sequence of a LOOKAHEAD CYCLE,

11 shows the sequence of another cycle,

Fig.12,13: Details of the addressing,

14: details of the RAM,

Fig. 15: Details of the control circuits.

Reference is made to the following sources from the literature:

/ 1 / -: Busesform the backbone of computer systems. Electronic Design 30 (1982) Vol. 23, p. 117-132. Ill Mathon, JC: 32-bit 2nd Generation Microprocessor. Electronics, 29.11.85, S.71-81.

/ 3 / Hedtke, R .: Microprecessor Systems. Reliability, Testing, Fault Tolerance, Springer-Verlag, Berlin-Heidelberg-New York-Tokyo 1984.

IAI Matthes, W .: Multimikrorechnersysteme. radio television efektronik Issue 4/1984 - Issue 12/1985 (Contribution episode). / 5 / WP 154244 Memory arrangement with error detection and diagnostic features, preferably for microcomputers. / 6 / WP 156743 Bus system for connecting logical function modules.

Ill WP 159916 Microcomputer arrangement, preferably for use in multi-core computer systems.

/ 8 / WP 233435 Memory arrangement with input / output connection, preferably for use in multi-microcomputer systems. / 9 / WP-Anmeldung GOGF / 288147.3 Memory arrangement with error correction, preferably for microcomputer. 1 shows the block diagram of a microcomputer arrangement designed according to the invention. It is in fact a modernized version of the microcomputer, which is described in detail in 111 and / 4 / respectively. The arrangement is suitable for connection to a system bus. / 6 / or / 4 / designed; In principle, however, other bus systems (vgl./i/) can be provided.

The CPU 1 is directly connected to a ROM 2 and I / O circuits 3. This is already shown in detail in / 4 /, 111 ; Furthermore, such elementary microcomputer arrangements are explained in detail in the many relevant company documents or textbooks.

Both switching means, which are accessible both from the CPU 1 and from the system bus, are a RAM 4, read registers 5 and write register 6.

The RAM 4 is constructed with dynamic RAM circuits which require feeding the address in two consecutive sections. The address inputs are arranged downstream of a first selection circuit 7, which is connected on the one hand to the low-order address lines of the CPU 1 and on the other hand to a second selection circuit 8. This in turn is connected on the one hand with higher-value common address lines (COMMON ADRS) and on the other hand with a third selection circuit 9, are connected to the nied'erwert common address lines and a refresh address counter 10. All common address lines (COMMON ADRS) are connected via CPU and bus-side coupling stages 11,12 the address lines of the CPU 1 and the system bus. Furthermore, common data lines (COMMON DATA) are provided, which are connected via further CPU or bus-side coupling stages 13, 14 to the corresponding data lines. The common data lines, the data inputs of the RAM 4 and the write register 6 are connected directly downstream. In addition, a terminal for an external diagnostic adapter is provided, as already shown in FIG . 111 .

The data outputs of the RAM 4 are connected to a read select circuit 15, which is further connected to all the read registers 5 via common read lines (COMMON READ). The read select circuit 15 are a bus read register 16 and a CPU read register 17 downstream, the bus read register 16 are directly connected to the data lines of the system bus and the CPU read register 17 directly to the data lines of the CPU 1. Finally, control circuits 18 are provided.

All data paths in the array are 8 bits wide. The CPU 1 supplies 16-bit addresses, the system bus has 20 address lines (/ 6 /); of these, the four most significant ones are used to select the slave device.

The RAM 4 has a capacity of 64k bytes and is equipped with an error correcting device. For this purpose, aside from 8 data bits, 4 correction bits are stored per byte, which are formed in accordance with an error correction code (ECC, compare / 31) so that 1-bit errors can be corrected during reading.

As an alternative to error correction, a comparison stop mode acc. / 5 / adjustable. The read registers 5 include:

- A BACKUP register

A register for reading the ECC bits of the RAM 4 as well as status bits

A register for reading the assignment of the diagnostic adapter connection (for this purpose, connected to the COMMON DATA on the input side according to FIG.

The write registers 6 include:

- a CONTROL register

- a DIAG MODE register

- a BUSADRS register

- a register on the connectable diagnostic adapter.

The assignment of essential registers is shown in FIG. 2. The registers CONTROL, DIAG MODE and BUS ADRS generally correspond to the description in IAI, / 7 /. BUS ADRS is completely identical to these descriptions, the assignment of CONTROL and DIAG MODE is revealed by comparison with the descriptions given above. Key features include:

The CONTROL register specifies the specification of a segment address in order to be able to access all 64 kbytes of RAM 4. For normal access, the lower 32kBytes are achievable in 8 segments of 4kBytes. Alternatively, the CPU 1 may directly address the entire RAM 4 when UNSEG MODE is activated. Then neither ROM nor bus accesses (as master) are possible. The write registers 6 themselves are alternatively accessible via I / O accesses.

If ECC BIT ACCESS is active, the ECC bit positions of RAM 4 can be accessed directly from the system bus. Corresponding accesses by the CPU 1 are possible if the bits 7,6,5 of the CONTROL register are all set. The entire address space is divided into 16 segments of 4 kbytes. When reading, some general status information appears in the higher nibble of the data bytes (Figure 2 below).

DISABLE REFRESH allows for the resetting address counter 10 to be disabled for diagnostic purposes.

- ENABLE LOOKAHEAD is used to turn on the actual operation of the invention.

- The BACKUP register records the higher-order positions of the RAM address. It is described in the context of essential aspects of error correction below.

Fig. 3 gives an overview of the interpretation of the CPU address

The assignments a), b), d), e) fully correspond to those already described in IAI, ΠΙ .

Assignment c) is used to access a 4 kbyte segment in RAM 4, the segment itself being selected via the CONTROL register. For normal access there are 8, for access to the ECC bits 16 segments.

In the case of register accesses (b) to the write registers, a copy is automatically stored in the RAM 4 when writing; when reading only this copy is read (see ΠI). In this case, each corresponding address of the form 2xxrH is converted into one of the form 8xxrH, so that the exact register addresses can be distributed arbitrarily, ie, for example, according to / 4/ or gem./7/. • Alternatively, the write registers 5 can be loaded via I / O output accesses.

The parts of the control circuits 18 which are essential for the embodiment according to the invention are shown in FIGS. 4 to 9. Otherwise, the control circuits 18 in principle do not differ from the circuit solutions described in more detail in / 4 / - / 8 / in various contexts. 4 illustrates the decoding of the accesses by the CPU 1. For this purpose, higher-order CPU address lines as well as outputs of the CONTROL register are connected to a ROM, which is used for each address and register assignment according to FIG. Fig. 2, 3 each excited one of three access control lines:

ROM ACCESS identifies accesses to ROM 2; executed at an address assignment acc. Fig. 3a)

- MASTER ACCESS identifies accesses via the system bus (as master); executed at an address assignment acc. 3 d)

- LOCAL ACCESS identifies accesses to the RAM 4 or to the registers 5, 6; executed at address assignments acc. 3b), c), e).

Furthermore, LOCAL ACCESS becomes effective for all address assignments when UNSEG MODE is active in the CONTROL register and no internal access is made to the ECC bits.

With this description, it is easy to set up the Boolean equations for occupying the ROM.

Fig. 5 shows a section of the wait signal circuit, whose other parts correspond to the respective switching means described in IAI, 111 .

For the CPU accesses that require switching, waiting flip-flops 19-21 are provided, namely

Flip-flop 19 for I / O accesses to registers 6; In this case, REGISTER I / O is an access line driven via a decoder, not shown, for I / O addresses of the CPU 1, IORQ being the corresponding request line of the CPU 1

- Flip-flop 20 for local accesses

- Flip-flop 21 for master accesses.

MREQ is the corresponding request line of the CPU 1.

The outputs of the Warteflipflops 19, 20 for internal accesses are connected in disjunctive connection a validity flip-flop 22, the output of which is in turn returned to the reset inputs of the said Wartflipflops 19, 20 in disjunctive link with the per se provided reset lines. The valid flip-flop 22 is further connected to a clock line synchronized with the clock input of the CPU 1 and a cycle control line.

Fig. 6 illustrates the excitation of the request lines for accesses by the CPU 1. The master and local access lines (MASTER REQUEST, LOCAL REQUEST) are energized by switching means as already described in IAI, 111 . To. In addition, a further request line (LOOKAHEAD REQUEST) of a conjunctive link 37 of a permit line is connected downstream with a NOR link 33 of all request lines of the CPU 1. The permission line is connected to programmable switching means, in this case to the DIAG MODE register.

In general, the permit line is provided primarily for diagnostic reasons and can therefore be omitted. Then the said request line is directly followed by the NOR operation.

The NAND link 38, which is also connected conjunctively in FIG. 6, has only technical reasons (suppressing internal accesses if the system bus signals "selective resetting", cf., for example, IAI) and is therefore not considered further.

FIG. 7 shows from FIG. 4 /, / 7 /, / 8 / an already known arrangement of a request register 23 and a cycle register 25 arranged downstream via a priority network 24.

Both registers 23, 25 are each extended by one position for the further request line shown in FIG. 6; the priority network 24 is designed such that the request in question has the lowest priority.

It is essential that the request register 23 is beschältet with a clock line which is energized synchronously with the clock input of the CPU 1.

The sequence control is also carried out in a known manner (/4/.../9/) acc. 8 by a shift register 26 with downstream Endeflipflop 27. The shift register 26 outputs time-offset control pulses (P 1 ... P8), if one cycle was mediated until the end flip-flop 27 is activated. Notwithstanding the already known solutions for excitation of the end flip-flop 27 and the control lines of the RAM 4 (RAS, CAS, SWITCH ADRS) gem. 9, a selection circuit 28 is provided, which is connected to different outputs of the shift register 26. Their selection input is preceded by a flip-flop 29 whose clock input is connected to the end flip-flop 27 and whose reset input is connected to said additional position of the cycle register 25. The control lines of the RAM 4 are connected downstream of the selection circuit 28 in conjunctive link 34 with access permission lines, which in turn are associated with the said additional position of the cycle register 25 disjunctive (35).

In the embodiment according to the invention is therefore to avoid unnecessary waiting cycles of the CPU 1. This is achieved by providing access to RAM 4 to a certain extent and by making accesses.

Such accesses are referred to below as LOOKAHEAD accesses. For virtually all types of CPU circuits, the address is first provided and then the request line (here: MREQ) is energized.

Dynamic RAMs require a time-division supply of the address (lower part with RAS, higher part with CAS).

The microcomputer arrangement according to the invention now makes it possible to preemptively make a request when the CPU has provided an address. This is the case when none of their request lines is energized (see NOR link 33 in Figure 6) and a particular edge of the CPU clock becomes active (here, rising edge).

If there are no higher-priority requests, a corresponding cycle (LOOKAHEAD CYCLE in the cycle register 25) is thus prompted by the request register 23 immediately during the provision of an address by the CPU 1.

This immediately flip-flop 29 is reset, so that via the selection circuit 28 early excited outputs of the shift register 26 for the control of the RAM 4 are effective and END is formed according to timely (P6).

Regardless of the specific CPU address, the control signals for the RAM 4 are enabled by LOOKAHEAD CYCLE

Since the first selection circuit 7 is connected in front of the address inputs of the RAM 4 directly to the lower part of the CPU address, there is a minimum runtime, so that the early delivery of control pulses is technically feasible. Thus, such a cycle can always be completed within the time frame specified by the CPU 1.

Waiting cycles are not necessary. While the cycle is already running, the addresses are gem. Fig. 4 decoded. The CPU activates 1 MREQ (or lORQ) on the next falling clock edge. There are now two possible cases:

1. It is actually a local access to the RAM 4 or to the registers 5,6.

2. It is a different access.

Only in the first case, one of the Warteflipflops 19, 20 is energized for internal accesses.

This leads to switching on the validity flip-flop 22, whereby the Warteflipflops 19,20 reset immediately before the CPU 1 evaluates their position.

In the second case, the valid flip-flop 22 is not energized; The cycle therefore runs, as it were, next to the actual access (eg to ROM 2 or as master via the system bus). It is important to avoid falsification of the contents of the RAM 4 or the write register 5 and to prevent the unauthorized intrusion of read information. This can be achieved directly by corresponding conjunctive junctions 39 of the respective control lines with a disjunctive link 36 of the validity flip-flop 22 and the inverted additional position of the cycle register 25, so that the control effects only occur outside of LOOKAHEAD cycles or in "valid" LOOKAHEAD cycles. With the switching off of the end flip-flop 27, flip-flop 29 becomes active again.

Thus, in all cycles that are not LOOKAHEAD cycles, the control signals for the RAM 4 are delivered later in time (via the selection circuit 28), taking into account the extended address transit times (via the selection circuits 7-9) as well as other reversal times.

The procedures described are illustrated in Fig. 10 (LOOKAHEAD cycle) and Fig. 11 (other cycle). Fig. 10 illustrates the timing of time-critical CPU access (instruction read). Such accesses require the fastest possible provision of the read information for the CPU 1. This is ensured in accordance with the invention (FIG. 1) by guaranteeing the shortest run times for the read information from the RAM 4 via the read select circuit 15 and the CPU read register 17 be, in particular by direct connection of the read register 17 to the data lines of the CPU 1 (bypassing all coupling stages). The read registers 16, 17 themselves are activated as already described in / 8 /.

The crucial address paths are illustrated in more detail in FIGS. 12, 13.

According to FIG. 12, the coupling stages 11 for connecting the CPU address to the common address lines are connected to the cycle control line for slave accesses (SLAVE CYCLE) in such a way that they enable the common address lines only in the case of such accesses. Otherwise, the coupling stages 11 are constantly activated, so that no switching times take effect with consecutive LOOKAHEAD cycles. ·

The selection circuit upstream of the coupling stages 11 serves to feed the segment address from the bus address register (see Fig. 2) into the most significant positions in the case of master accesses (with addresses according to Fig. 3d). In Fig. 13, the address selecting circuits 7-9 are shown in more detail.

Selection circuit 7 is controlled so that the lower part of the CPU address is always controlled by, unless specific conditions occur.

For this purpose, the selection input is connected in disjunctive link 40 with the address switching line of the RAM 4 (SWITCH ADRS) and all remaining output lines of the cycle register 25 except LOOKAHEAD CYCLE. The reversal thus becomes effective only if the higher-order part of the RAM address is to be supplied or if cycles other than LOOKAHEAD cycles are to be executed

 Selection circuit 8 controls the higher-order part of the address when the SWITCH ADRS is active, otherwise the

which is formed via selection circuit 9 during refresh cycles by the content of refresh address counter 10 and otherwise by the low-order part of the common address lines.

The higher part of the address at the input of the selection circuit 8 consists on the one hand directly from parts of the common address lines and on the other hand from lines (HI ADRS 15-12), which are connected to control means not described in detail.

The selection circuit 8 is further followed by the BACKUP register (Figure 2), which in turn is connected to common read lines before the read select circuit 15.

In Fig. 14, details of the RAM 4 are shown together with the said read selection circuit 15.

The actual RAM receives 64k words in 12 bits (8 data and 4 ECC bits) to allow the correction of 1-bit errors. To form the ECC bits, a converter implemented as a ROM 30 is connected upstream, which is additionally connected to a changeover line (ECC DATA ACCESS), which is ultimately arranged downstream of the CONTROL register (FIG. 2) via unconfigured further assigners. In said ROM 30, both the formation of the error correction code and the direct transfer of the low-order four data bits are provided (with active ECC DATA ACCESS these are entered directly in the corresponding positions of the RAM).

The actual RAM is followed by a correction network 31 and connected directly to the read selection circuit 15.

This implements the following functions:

- Detection of 1-bit errors in the 12-bit words; doing so the ECC EFFECTIVE error line is energized.

- Correction of those 1-bit errors that affect the 8 data bits. The formation and evaluation of error correction codes is extensively described in the literature (eg, / 3 /), so that the presentation of details can be omitted.

It is essential that data bits are corrected immediately during reading, since with the LOOKAHEAD cycles there is no longer any possibility of stopping, modifying or the like in the event of a fault. Error correction principles that assume that the cycle is extended in the event of a fault (for example, after / 9 /) are therefore not applicable here.

In the arrangement according to the invention, instead, it is provided that an interrupt in the CPU 1 is triggered by means of switching means which are not shown, but which can easily be implemented in the event of a fault (ECC EFFECTIVE = 1). A corresponding ROM-resident software routine then inspects the RAM 4 and corrects the RAM content by program writing.

So that not all the RAM must be screened, the BACKUP register is provided. This is loaded in each cycle with the higher order part of the address. Loading is prevented if a RAM read error has been detected.

(This way of operating BACKUP registers is described in / 6 /.) This makes the higher part of the address of the erroneous word available to the software.

Furthermore, it is essential that the path through the correction network 31 during reading is traversed very quickly. Therefore, the direct connection to the read select circuit 15 is provided. The remaining sources of read information are connected to the second inputs of the read select circuit 15 via common read lines (COMMON READ). In Fig.

this is illustrated by the coupling stage for reading the ECC bit positions and additional status bits (Fig. 2). The selection is made by the selection line SPECIAL READ, which is arranged downstream of address decoders, not shown.

Fig. 15 shows essential details of the general control circuits. All access control lines are connected downstream of a register 32, which is preceded by a relatively complex decoding circuit (this can be stated without problems from the description of the different access possibilities in accordance with ΠΙ, 181 , eg in the form of Boolean equations covering the allocation of ROM or Determine PLA circuits).

Write and load pulses for memory or register are derived in principle by conjunctive connections of outputs of the register 32 with pulses, which are formed via the shift register 26 in conjunction with the Endeflipflop 27. In FIG. 15 this is illustrated by means of such a pulse line (PULSE), which in addition is connected conjunctv (39) with a disjunctive link 36 of the validity flip-flop 22 with the inverted additional position of the cycle register 25 (LOOKAHEAD CYCLE). This achieves the effect already described above:

Pulses are delivered only outside LOOKAHEAD cycles, or only when the preventively initiated cycle actually addresses the storage means concerned.

For this purpose, the fact is further exploited that when energized the control line P3 (loading of the register 32), the address of the CPU 1 is guaranteed valid (with appropriate lead for passing through the decoding), so that at this time the type of access is clearly established (see Fig. 10). The advantage of the invention is that microcomputers, which are used in multi-microcomputer arrangements and are predominantly equipped with dynamic RAMs for internal and external accesses (dual port access), enable operation while largely avoiding wait states, even if the CPU does not is specially designed.

Claims (4)

A microcomputer arrangement for use in a multi-core computer system, wherein the memory means, preferably equipped with dynamic RAMs, are accessible both from the internal CPU and from a shared time-multiplexed bus (system bus) and the control circuits thereof are provided with switching and flow control devices, characterized in that the address inputs the relevant storage means (4) are arranged directly downstream of a first selection circuit (7), on the one hand, directly connected to low-order address lines of the CPU (1) and, on the other hand, to a second selection circuit (8) which, in turn, is connected to all of them for addressing the storage means (4) required address lines is connected, that the intrinsic control circuits (18) are formed so that the existing itself request and cycle registers (23,25) with intervening priority network (24) by one position extended si nd, wherein the priority network (24) is formed so that this postition has the lowest priority that the said additional position of the request register (23) is preceded by a NOR operation (33) of all request lines of the CPU (1) that a valid flip-flop (22) is provided, preceded by the outputs of the inherent waiting flip-flops (19, 20) for internal access in disjunctive link, that this validity flip-flop (22) in turn in disjunctive connection with the per se provided reset lines to the reset inputs of said Warteflipflops (19, 20), the valid flip-flop (22) is synchronized with the cycle control line (LOOKAHEAD CYCLE) connected to said additional position of the cycle register (22) and synchronously with the request register (23) with a clock input to the CPU (1) Clock line (CPU CLOCK) is wired, that in the connections to sic h provided access permission lines with per se provided conjunctive links (34) to which the control lines (RAS, CAS) of the respective storage means (4) are connected, disjunctive links (35) are inserted with said additional position of the cycle register (25) and that the write, load pulse and enable enable lines in conjunctive connections to a disjunctive link (36) of the valid flip-flop (22) are connected to the inverted said additional position of the cycle register (25). 2. Arrangement according to claim 1, characterized in that the sequence control in the context of the control circuits (18) is designed so that a per se provided shift register (26) a selection circuit (28) is arranged downstream, .the one with earlier in time and on the other hand with connected laterally energized outputs of the shift register (26) that this selection circuit (28), the control lines (RAS, CAS, SWITCH ADRS) of the memory means (4) and the self-existing Endeflipflop (27) are connected downstream and that the selection input of the selection circuit (28) is followed by a flip-flop (29) which is connected on the one hand to the output of the additional position (LOOKAHEAD CYCLE) of the cycle register (25) and on the other hand to the Endeflipflop (27).  3. Arrangement according to claim 1, characterized in that in the connection between the NOR operation (33) of all request lines of the CPU (1) and the additional position of the request register (23) is inserted a conjunctive link (37) with a permission line, which is connected to programmable adjustable switching means of the microcomputer arrangement. 4. Arrangement according to claim 1, characterized in that the selection input of the first selection circuit (7) before the address inputs of the memory means (4) a disjunctive link (40) of all positions of the cycle register (25) with the exception of the additionally introduced and the address switching line (SWITCH ADRS) of the storage means (4) is connected upstream. For this 15 pages drawings