DD252484A1 - CIRCUIT ARRANGEMENT FOR MONITORING AN OPERATING VOLTAGE - Google Patents

Abstract

Circuitry for monitoring an operating voltage, in particular of CMOS memory devices, it is provided that a threshold value when falling below a minimum value of the operating voltage forms a signal with which a first transistor switch realized a separation of the connection between the operating voltage source and the power supply terminal of the memory modules and a second Transistor switch which acts as a lockable negator prevents the formation of a signal to activate the memory modules. Fig. 1

Description

For this 1 page drawings

Field of application of the invention

Computer systems with memories, in particular with memory modules in CMOS technology, require a so-called buffer voltage source to maintain the data in the memory. If the operating voltage source is switched off or falls below a minimum value in the computer system, the buffer voltage source, which is preferably realized by a rechargeable battery or a battery, takes over the power supply of the memory modules. In this case, in order to prevent discharge of the buffer voltage source via the operating voltage source, the connection operating voltage source - power supply terminal of the memory modules must be separated without feedback.

So that only defined data can be written to the memory modules, the memory modules should, for example, fall below a minimum value of the operating voltage. B. be locked via their chip ENABLE input. For this purpose, a circuit arrangement for monitoring an operating voltage is used, which disconnects the operating voltage source from the power supply terminal of the memory modules without reaction when switching off the operating voltage source or falls below its voltage below a minimum value and prevents the formation of a signal to activate the memory modules.

Characteristic of the known technical solutions

For this application, DE-PS 3311258 and DD-PS 216546 circuit arrangements have become known to which a high circuit complexity attached, which is due to the use of separate threshold switches for the realization of the following functions:

-Trennen the connection operating voltage source - power supply terminal of the memory modules; Preventing the formation of a signal for activating the memory modules.

Furthermore, in these circuit arrangements for maintaining a low tolerance of the switching thresholds and the switching sequence, a single adjustment or a single programming of the threshold value is required.

Object of the invention

Essoll reduced the circuit complexity and the mentioned disadvantages are eliminated, thereby making circuit arrangements of this kind more economical. .

Explanation of the essence of the invention

The object of the invention is to provide a circuit arrangement for monitoring an operating voltage, in particular for memory modules in CMOS technology, which manages compared to known technical solutions with a small number of electronic components and a lower adjustment effort, and the switched off operating voltage source, the buffer voltage source only with a very low power consumption. According to the invention the object is achieved in that a threshold value when falling below a minimum value of the operating voltage forms a signal with which a first transistor switch realizes a separation of the connection between the operating voltage source and power supply terminal of the memory devices and a second transistor switch prevents the formation of a signal to activate the memory modules, whereby the type of coupling of the two transistor switches to the threshold value switch ensures that the second transistor switch reliably prevents the formation of the signal for activating the memory components before the first transistor switch disconnects the connection between the operating voltage source and the power supply terminal of the memory components.

embodiment

With reference to an embodiment of the invention will be explained in more detail.

The accompanying drawings show:

1 shows a circuit diagram of the circuit arrangement according to the invention,

2 shows the time dependence of the voltage at the power supply connection of the memory components and the signal for activating the memory components from the operating voltage.

If the operating voltage U _B falls below a value which is less than the sum of the Z voltage of V ₁ and the base-emitter voltage of V ₂ , then V _{2 is} de-energized. Since flow through the collector-emitter of stretch of V ₂ in its energized state, the base current of V ₃ and the Ermitterstrom of V _4, and V ₃ and V ₄ de-energized in the currentless state of V ₂ that a separation of the connection Ub- Us and the rise of the level of the signal CS to the value of the voltage Us, regardless of the level of the signal CS causes.

During the transition from the conducting to the currentless state of V _2, the collector-emitter of voltage of V ₂ increases, which is a reduction in the oversteer factor of V ₃ and with further increase of the collector-emitter of voltage of V ₂ to the blocking of the transistor V ₃ leads.

In contrast, the rise of the collector-emitter voltage of V ₂ by the series connection of the collector-emitter paths of V ₂ and V ₄ directly affects the level of the signal CS, which is to safely block the formation of the signal CS from the signal CS, even before the separation of the compound Ug-Us by V ₃ leads.

The resistors R ₁ ; R ₃ and R ₆ are the base current limit of the transistors V ₂ ; V ₃ and V ₄ and the resistors R ₂ ; R ₅ the safe locking of the transistors V ₂ and V ₄ . By means of R ₄ is formed in connection with the transistor V ₄ in the current-carrying state of V ₂ by negation of the signal CS, the signal CS. With the resistor R ₄ further, when directly connecting the signal CS to the CS input of a CMOS RAM circuit, the conditions of some manufacturers of CMOS RAM circuits are met, according to which U _cs ^ U _C c and in the sleep state of the CMOS RAM circuit Ue _s = U _{cc is} to ensure.

Since falling below a minimum value of the operating voltage U _B all transistors V ₂ ; V ₃ ; V ₄ get into the de-energized state in the described manner, the current decrease of the circuit arrangement according to the invention and thus the load of the buffer voltage source U _P is in this case only very low (only leakage current of the locked transistors).

Claims (4)

1. Circuit arrangement for monitoring an operating voltage, in particular of CMOS memory modules, characterized in that a threshold value switch (Ri; R ₂ ; V ₁ ; V ₂ ) when falling below a minimum value of the operating voltage (U _B ) forms a signal with which a first Transistor switch (R ₃ ; V ₃ ) realized a separation of the connection between the operating voltage source (U _B ) and power supply terminal of the memory devices (Us) and a second transistor switch (R ₄ ; R ₅ ; R ₆ ; V ₄ ) which acts as a lockable Negator, the Forming a signal to activate the memory blocks (CS) from the signal (CS) prevented. 2. Circuit arrangement according to claim 1, characterized in that the threshold value switch (R ₁ ; R ₂ ; V ₁ ; V ₂ ) has a transistor (V ₂ ) whose threshold voltage is adjustable by a Zener diode (V ₁ ). 3. Circuit arrangement according to claims 1 and 2, characterized in that the first transistor switch (R ₃ ; V ₃ ) has a transistor (V ₃ ) which is controlled by the threshold value switch (R ₁ ; R ₂ ; V ₁ ; V ₂ ) in that its base is connected to the collector of the transistor (V ₂ ) belonging to the threshold value switch via the resistor (R ₃ ) which fulfills a current limiting function. 4. Circuit arrangement according to claims 1, 2 and 3, characterized in that the second transistor switch (R ₄ ; R ₅ ; R ₆ ; V ₄ ) has a transistor (V ₄ ) which is connected to the threshold value switch (R ₁ ; R ₂ ; V ₁ V ₂ ) in which its emitter is connected to the collector of the transistor (V ₂ ) belonging to the threshold value switch, and whose collector is connected via a resistor (R ₄ ) to the collector of the first transistor switch (R ₃ ; V ₃ ) belonging transistor (V ₃ ) is connected, so that one of the base of the transistor (V ₄ ) supplied signal (CS) only in the current-carrying state of (V ₂ ) negated at the collector of the transistor (V ₄ ) as a signal for activating the memory modules (CS) is provided.