DD247543A1 - METHOD FOR PRODUCING SEMICONDUCTOR COMPONENTS - Google Patents

Abstract

The invention finds application in the production of semiconductor devices with planar epitaxy technique. The aim of the invention is a method for increasing the yield and increasing the packing density of semiconductor devices, wherein regions below and above the epitaxial layer are assigned exactly, independently of the occurring epitaxial offset. According to the invention, this object is achieved in that, following the epitaxial process, the epitaxial layer is treated at selected locations until the center of the resulting relief coincides with the center of the actual position of the buried region as it is projected perpendicularly onto the relief.

Description

Field of application of the invention

The invention relates to a method for the production of semiconductor devices with planar epitaxial technology.

Characteristic of the known technical solutions

Substrate materials with defined crystal orientation are used to fabricate integrated solid-state circuits and semiconductor devices in planar epitaxial technology. The growth of the monocrystalline epitaxial layer is known to be such that by preferentially maintaining the crystal orientation of the substrate material during the growth process, lateral displacement of structural edges present in the substrate prior to the epitaxial growth process may occur, particularly when using <111> material. In bipolar technology, it is z. B. required to realize areas that are "buried" by the epitaxy whose relief edges according to the crystal orientation of the substrate material used, usually <111> Si at a defined angle, usually Φ 90 ° grow with the substrate surface A lateral offset arises between the position of the structural edges of the buried (eg, n ⁺ ) region transmitted as a result of the epitaxy process and the original structural edges projected perpendicular to the substrate surface.

This lateral epitaxial displacement is to avoid yield losses already in the layout constructively taken into account by correspondingly large safety distances or overlaps of the electrically relevant circuit elements, such. B. a sufficiently large distance between the n ⁺ -begrabentfn area and the insulating frame or a sufficient overlap of the n ⁺ -benched area through the shaft area as a low-resistance contact to this, their Eindiffusion projecting symmetrical to the substrate surface at least greater than the thickness of the epitaxial layer in they have to be inside. As a particular problem has a negative effect that the lateral epitaxial displacement particularly depends on a number of technological parameters and its reproducibility must either be considered difficult to control or so far can only be determined by non-destructive analysis methods, eg. B. by introducing appropriate cuts.

In order to realize a high integration density or minimum area requirement for the corresponding function of the circuit or the component, this epitaxial displacement must be "compensated" by a sufficient lateral displacement of arrangements under the epitaxy Compensate, this essentially two methods are known.

First, a fixed epitaxial skew is taken into account in the design of the circuit or device by shifting assignment structures or alignment marks with respect to the structures of the circuit or device by the epitaxial displacement. This requires a well-known stable epitaxial displacement over all discs, which experience has shown that it is difficult to control. The current state of the epitaxial offset can be compensated for changes in the same by a similar design change, which appears economically questionable.

Secondly, a suitable measuring arrangement is used to set a shift from one slice to another in a photolithographically defined manner (WP 229537). However, this presupposes that the epitaxial displacement is previously analyzed and digitized, and is sufficiently constant on each slice.

Since previously known analysis methods are not destructive and relatively expensive, not every substrate to be processed can be analyzed and the distance between 2 analyzes is relatively large. Short-term fluctuations between 2 analyzes can thus not be detected. It is also organizationally difficult, u. a. under production conditions with large variety of types, to react to an unstable epitaxial displacement.

Object of the invention

The aim of the invention is to specify a method for increasing the yield and for increasing the packing density of semiconductor components in planar epitaxial technology, in which regions under and over the epitaxial layer are assigned exactly, independently of the occurring epitaxial displacement.

Explanation of the essence of the invention

The invention has for its object to provide a method with which areas below and above the epitaxial layer can be assigned exactly regardless of epitaxial displacement.

According to the invention the object is achieved in that following the epitaxial process, the epitaxial layer is treated at selected locations until the center of the resulting relief coincides with the center of the actual position of the buried territory in its vertical projection on the relief. Thus, a sufficiently accurate lateral assignment of sequence structures to the actual location of the buried territory is possible.

This sufficiently accurate assignment avoids negative electrical effects of the epitaxial skew on the crop yield in all areas of each slice.

Consequently, the safety margins that preclude an increase in the degree of integration and the packing density can be minimized without the analysis and compensation of the epitaxial displacement that was previously required.

embodiment

The invention will be explained below with reference to an embodiment.

Figure 1 shows a slice after epitaxy with a mask over the buried area.

In Figure 2, the disc is shown after making an opening in the silicon.

FIG. 3 shows the processing state after the production of a lacquer mask assigned to the buried area according to the invention.

In the production of integrated circuits, an η-type epitaxial layer 2 is deposited on a p-type Si substrate 1, whereby the regions 3, 3 'previously generated by suitable masking and doping are buried. Reliefs 4,4 'are formed on the surface of the epitaxial layer. The center of these reliefs is laterally shifted by the epitaxial displacement 5 with respect to the vertical projection of the center of the buried area on the surface.

To secure an epitaxial displacement-independent assignment of the following planes to the buried area, an opening 7 in the epitaxial silicon is to be produced over a selected buried area 3 and the associated surface relief 4. For this purpose, a mask 6 is applied and the silicon located under this mask 6 in a mixture

60-95 mol% HNO ₃

4-40Mol-% HF

0.1-35 mol% CH ₃ COOH

0.01-1 mol% H ₂ [SiF ₆ ]

10-35 mol% H ₂ O dissolved,

wherein the temperature is preferably kept smaller than 293 ⁰ K constant. The result is a relief 8, whose center coincides with the center of the now dissolved buried territory 3.

After production of an SiO ₂ layer 9 on the wafer surface, the assignment according to the invention of the openings 10 in the lacquer mask for the successive plane to the buried region 3 'takes place by assigning this mask 6 to the relief 8 in the opening 7 in the silicon.

Claims (8)

Invention claim: 1. A process for the production of semiconductor devices with planar epitaxial technology for accurate assignment of areas under and over the epitaxial layer, regardless of the occurring epitaxial displacement, characterized in that this assignment by means of reliefs (4,4 ', 8 ), which are made visible at selected locations only by suitable treatment, preferably by ablation, of the epitaxial layer (2). 2. The method according to item 1, characterized in that the treatment is carried out by sole or combined processes based on chemical, physical or physico-chemical principles of action. 3. The method according to item 2, characterized in that the treatment is carried out using masking layers (6) on S1O2 and / or Si ₃ N ₄ or other metal layers or compounds on which preferably a paint mask is. 4. The method according to item 1, characterized in that the selected locations are preferably in the scribe grid, in blank or test fields or on the back of the disc. 5. The method according to item 3, characterized in that the treatment with a mixture of 60-95 mol% HNO ₃ 4-40 mole% HF
0.1-35 mol% CH ₃ COOH
0.01-1 mol% H ₂ [SiF ₆ ]
10-35 mole% H ₂ O
is carried out. 6. The method according to item 5, characterized in that the treatment at constant temperature, preferably less than 293 ° K, takes place. 7. The method according to item 5, characterized in that a relative movement between the mixture and the discs is generated, preferably with a flow rate of greater than 10cm / s. 8. The method according to item 2, characterized in that the treatment takes place as a removal to below the expitaxial layer. For this 1 page drawings