DD239482A5 - REAL-TIME SPECTRAL ANALYSIS OF ELECTRICAL SIGNALS AND PICTURE TRANSFORMATION TECHNIQUES AND DEVICE FOR REAL-TIME SIGNAL PROCESSING AFTER A HIERARCHIC PYRAMID - Google Patents

Abstract

With the aim of real-time realization of the Burt pyramid algorithm, it is the object of the invention to provide a real-time spectral analysis of electrical signals and image transformation techniques as well as a real-time signal processing device according to a hierarchical pyramid. A pipelined structure (Figure 3) is used for either or both of the following: (a) Delayed real-time analysis of the frequency spectrum of an information component (having one or more dimensions) of a given temporal signal (G0) whose highest one of interest Frequency is not greater than f0 and (b) for the delayed real-time synthesizing of such a temporal signal (G0) from its frequency analysis spectrum (L0 ... GV). Such a pipeline structure is particularly suitable for the image processing of the two-dimensional spatial frequencies of television images, which are defined by a temporal video signal. Fig. 3

Description

For this 9 pages drawings

Field of application of the invention

The invention relates to a signal processing device for signal analysis and / or synthesis. Specifically, the signal processing device of the present invention uses a pipelined structure to analyze, in delayed real time, the frequency spectrum of an information component (having one or more dimensions) of a given temporal signal whose highest frequency of interest is not greater than f ₀ and / or delayed Real time to synthesize such a temporal signal from its analyzed frequency spectrum. The invention is particularly, but not limited to, real-time delayed image processing of the two-dimensional spatial frequencies of television images defined by a temporal video signal.

Characteristic of the known technical solutions

Much work has gone into developing a model for human vision. It has been found that the human visual perception system performs a primitive decomposition of luminous images in spatial frequencies by dividing the spatial frequency information into a number of continuous, overlapping spatial frequency bands. Each band is roughly one octave wide, and the center frequency of each band differs from that of the neighboring band by a factor of about two. Research suggests that there are about seven bands or channels ranging from 0.5 to 60 periods / Cover the spatial frequency of the human visual system. The significance of this finding is that a spatial frequency information that is more than a factor of 2 away from the other spatial frequency information is processed independently of the human optical system of perception.

It has also been shown that the spatial frequency processing carried out in the human optical perception system is spatially localized. The signals within each spatial frequency channel are therefore processed over small subregions of the image. These subareas overlap one another and are broadly two periods - at a particular frequency - wide.

Using a sinusoidal grid as the test pattern shows that the threshold contrast / sensitivity function for the sine grid pattern drops rapidly as the spatial frequency of the sine grid image is increased. This means that at high spatial frequencies one must see a high contrast (= 20% at 30 cycles / degree), but that at low spatial frequencies only a relatively low contrast has to be seen ("0.2% at 3 cycles / degree).

It has been found that the ability of the human visual perception system to perceive a change in contrast of a sine grid image that is above the threshold is better even at lower spatial frequencies than at higher spatial frequencies. In order to correctly differentiate a contrast change in 75% of all cases, a normal human needs a contrast change of 12% for a sine grating of 3 periods / degree, but a contrast change of 30% for a grating of 30 periods / degree.

Dr. Peter J. Burt, who knows the above-mentioned characteristics of the human visual perception system, has developed an algorithm (hereinafter referred to as "Burt pyramid") which he has realized with the aid of a computer, without real time, around the two-dimensional spatial frequencies in an image Each spatial frequency band, except the lowest, is preferably one octave wide, so if the highest spatial frequency of interest of the image is not greater than fo, then the highest frequency band covers the octave from f _o / 2 to f ₀ (with a center frequency of 3f _o / 4), the next higher frequency band covers the octave from f _o / 4 to f _o / 2 (with a center frequency of 3 f _o / 8), etc.

It should be pointed out at this point to some essays, the author or co-author. Burt is and in which various aspects of the Burt pyramid are described in detail:

"Segmentation and Estimation of Image Region Properties Through Cooperative Hierarchical Computation", by Peter J.Burt et al., IEEE Transactions on Systems, Man, and Cybernetics, Volume SMC-11, No. 12,802-809, December 1981. "The Laplacian Pyramid as a Compact Image Code "by Peter J. Burt et al. a., IEEE Transactions on Communications, Vol. COM-31, No.4,532-540, April 1983.

"Fast Algorithms for Estimating Local Image Properties," by Peter J. Burt, Computer Vision, Graphics, and image Processing 21, 368-382 (1983).

"Tree and Pyramid Structures for Coding Hexagonally Sampled Binary Images" by Peter J. Burt, Computer Graphics and Image Processing 14, 271-280 (1980).

"Pyramid-based Extraction of Local Image Features with Applications to Motion and Texture Analysis" by Peter J. Burt, SPIE, vol. 360,114-124.

"Fast Filter Transforms for Image Processing" by Peter J.Burt, Computer Graphics and Image Processing 16: 20-51 (1981). "A Multiresolution Spline with Applications to Image Mosaics" by Peter J. Burt et al. a., Image Processing Laboratory, Electrical, Computer, and Systems Engineering Department, Rensselaer Polytechnic Institute, June 1983.

"The Pyramid as a Structure for Efficient Computation" by Peter J. Burt, Image Processing Laboratory, Electrical and Systems Engineering Department, Rensselaer Polytechnic Institute, June 1982.

The Burt pyramid algorithm uses special sampling techniques to analyze a relatively high resolution original image into a hierarchy of N (where N is an integer> 1 = plural integer) separate component images (each of which is a Laplacean image that is another octave the spatial frequencies of the original image) plus a residual Gaussian image (which consists of all spatial frequencies of the original image below the Laplacian component image of the lowest octave). As used herein, the term "pyramid" refers to the successive reduction of the spatial frequency bandwidth and sampling density of each of the component image hierarchies as they progress from the component image of the highest octave to that of the lowest octave A first advantage of the Burt pyramid algorithm is the ability to A second advantage of the Burt pyramid algorithm is that the spatial frequency bandwidth of one octave of each of the hierarchy of component images is related to the characteristics of the human As a result, it becomes possible to selectively process or change the spatial frequencies of individual ones of the hierarchy of the component images in various independent ways (ie without the signal processing i of a component image would significantly affect any other component image) to highlight or create any other desired effect in the synthesized image formed from the processed component images. An example of such a desired effect is the multi-resolution dithering technique described in detail in the above article "A Multiresolution Spline with Applications to Image Mosaics." Heretofore, the Burt pyramid algorithm has been implemented by means of a general-purpose digital computer The size of each pixel sample of an original image is represented by a multiple bit number (e.g., 8 bits) stored at an individual address location of a computer memory For example, a relatively high resolution two-dimensional original image will require from 2 ⁹ (512) pixel samples in each In both of its two dimensions, there is a large memory of 2 ¹⁸ (262144) address locations for storing each of the multiple bit numbers representing the levels of the respective pixel samples that make up the original image Computers are processed according to the Burt pyramid algorithm. Multiple steps are performed such as convoluting pixel samples having a predetermined kernel or trunk weight function, sample decimation, sample expansion by interpolation, and sample subtraction. The size of the kernel function (in each or several directions) is relatively small (expressed in terms of the number of pixels) as compared to the size in each dimension of the entire image. The subarea or window of the picture elements (which are equal in size to the kernel function and in turn symmetrical about each picture element) is multiplied by the kernel weight function and summed in a convolution calculation operation.

The kernel weight function is chosen to act as a low pass filter for the multidimensional spatial frequencies of the convolved image. The nominal cut-off frequency (also referred to in the filter technique as the cut-off frequency) of the low-pass filter characteristic, which results from the kernel function in each dimension, is chosen at practically half of the highest frequency of interest in this dimension of the folded signal. However, this low-pass filter characteristic does not need to have a steep drop at a given excitation frequency, but the decay may be relatively gradual, in which case the nominal cut-off frequency is defined as the frequency at which a predetermined attenuation (for example 3 dB) occurs. Filters with a less steep drop can be used because the Burt pyramid inherently compensates for the occurrence of spurious frequencies due to aliasing effects that occur with a gradually decreasing low-pass filter characteristic. The convolution image is decimated by effectively suppressing every other convolved image element in each of the sequentially viewed dimensions of the image, reducing the number of pixels in the convolved image by half in each of its dimensions. Since an image is usually two-dimensional, the folded decimated image consists of only a quarter of the number of pixels that the image contains prior to such decimation. The reduced number of pixel samples of this folded decimated image (referred to as Gaussian image) is stored in a second memory.

Starting with the stored pixel samples of the original image, the mentioned convolution decimation process is iteratively performed N times (where N is an integer> 1) to obtain (N + 1) images consisting of the high-resolution original image and a hierarchical pyramid of N additional Gaussian images with reduced resolution, where the number of pixel samples (sample density) in each dimension of each additional image is only half the number of pixels in each dimension of the immediately preceding image. If the high-resolution stored original image is referred to as Go, then the hierarchy of N stored additional images can be denoted Gi to Gn, with the increasingly reduced number of pixel samples of each of these N additional images being stored in a separate one of N stores. When counting the stored original image, one thus comes to a total of N + 1 storage.

According to a non-real-time implementation of the Burt pyramid algorithm, the next computation procedure is to generate additional interpolation samples between each pair of stored pixels Gi in each dimension of the image so that the reduced sample density of the stored image G is again stored to the sample density of the original Image G _{0 is} expanded. The digital value of each of the pixel samples of the expanded image Gi is then subtracted from the stored digital value of the corresponding pixel sample of the original image Go to a difference image (referred to as a Laplace image). This Laplacian image (L ₀ ), which has the same sample density as the original image G ₀ , consists of those spatial frequencies that are in the original image within the octave f _o / 2 to f ₀ plus often a small lower spatial frequency error compensation component, which is a loss of information which is due to the decimation step made in the derivative of the reduced sampling density image G ₁ , and the introduction of the interpolation samples which again occur when the sample density is expanded to that of the original image G ₀ . This Laplace image L ₀ then replaces the original image Go in memory in the first of the N + 1 pyramid memories.

By iterating this method, a hierarchy is again derived in the same way, consisting of N-1 additional Laplace images L ₁ to L _n ., And written into a corresponding additional N-1 memory in which the Gaussian images G ₁ to G _N -i are stored (in which memory the Gaussian images G ₁ to G _N _i are replaced). The Gaussian image G _n (with the most reduced sample density) is not replaced in its corresponding memory by a Laplace image, but remains stored therein as the Gaussian remainder consisting of the lowest spatial frequencies of the original image (ie those below the octave L) _n .-,).

The Burt pyramid algorithm allows storage of the original image without aliasing effects by an iterative calculation method of several steps of the expansion of the stored residual image Gn to the sample density of the image L _n .! and then adding this image to the stored Laplace image L _N _i for deriving a summation image. This sum picture is similarly expanded and added to the Laplace picture Ln_ ₂ and so forth until the original high-resolution picture is synthesized by summing all the Laplace pictures and the residual picture. After analyzing one or more original images in N Laplace images and a Gaussian remainder, one may perform any particular desired image processing or modification step (such as image gearing) before synthesizing a complete high resolution image therefrom.

Object of the invention

The non-real-time realization of the Burt pyramid algorithm by computer processing is effective in processing fixed image information. However, it is not applicable for the analysis of consecutive images that are constantly changing over time (ie consecutive video images when watching TV). To analyze successive, time-varying images requires a real-time realization of the Burt pyramid algorithm, as given by the invention.

Explanation of the essence of the invention

In particular, the invention is directed to a signal processing device having a pipeline structure which, in delayed real time, analyzes the frequency spectrum of an information component of a given temporal signal in which the highest frequency of interest of this frequency spectrum is not greater than fo. Furthermore, this information component of the given temporal signal corresponds to information having a given number of dimensions. The apparatus includes a set of N sequentially arranged sampled signal transmitters (where N is an integer> 1). Each of the transmission devices has first and second input terminals, and first and second output terminals. The first input terminal of the first transmission means of the set is supplied with a given input temporal signal. The first input terminal of each of the second to Nth transmission means of the set is coupled to the first output terminal of the immediately preceding transmission means of that set so that each of the second to Nth transmission means forwards a signal to the immediately following transmission means of the set. The second input terminal of each of the transmission means of the set is supplied with a separate sampling clock signal. With this arrangement, each of the transmit means of the set at its first and second output ports provides signals at a rate equal to the sampling frequency of the applied clock signal.

Furthermore, each of the transmission means of the set has a low-pass transfer function between its first input terminal and its first output terminal for the information component of the signal supplied to its first input terminal. The low-pass transfer function of each transmission means of the set has a nominal cut-off frequency which is a direct function of the sampling frequency of the clock signal applied at the second input of that set's transmission means. The clock signal applied to the second input terminal of the first transmission means of the set further has a sampling frequency which is (a) twice as large as fo and (b) for this information component gives a nominal cutoff frequency of that low pass transmission function of the first transmission means of the set which is less than fo , Finally, the clock supplied to the second input terminal of each of the second through Nth transmitters of the set has a sampling frequency which is (a) less than the clock frequency applied to the second input terminal of the immediately preceding transmitter of the set, (b) at least twice the maximum frequency and (c) gives a nominal cut-off frequency for its low-pass transfer function less than that of the immediately preceding transfer means of the set.

The signal provided at the second output terminal of each of the transmission means of the set corresponds to the difference between the information component supplied at its first input terminal and a direct function of the information component supplied at its first output terminal.

The information component of the given temporal signal, which is processed by the signal processing device according to the invention, can be, for example, but not limited to, the 7 \ A / piHimAnAnimAn Ranimfriant ien7Vnmnnnontiin ioHoe Listening »i η α nH rf η In eanHon \ / nl I hi I Her oinoc telecontrol radio frequency

In general, the invention is useful in analyzing the frequency spectrum of a signal derived from a source of spatial or non-spatial frequencies in one or more dimensions / independent of the particular nature of that source. For example, the invention is useful for analyzing one-, two-, three- or more-dimensional complex signals derived from sound sources, radar sources, seismographic sources, robotic sources, etc., other than the two-dimensional visual image sources such as television images. Furthermore, the invention relates to a signal processing device which uses a pipeline structure and synthesizes such a complex signal from a set of analyzed signals in delayed real time.

embodiments

In the accompanying drawings show:

Fig. 1 is a functional block diagram for illustrating the invention in its most general form;

FIG. 1a: a digital embodiment of a first type of any one of the set of transmission devices for the

sampled signal according to Fig. 1; Fig. 1b: a digital embodiment of a second type of any one of the set of signal transmitting means for the sampled signal of Fig. 1;

Fig. 1c shows an alternative digital embodiment of the last signal transmission means of the set of transmission means for the sampled signal of either the first or the second kind;

Fig. 2 is an illustrative example of a kernel weight function useful for practicing the invention; Fig. 3 is a block diagram of a one-dimensional system of the spectrum analyzer, the spectrum varying circuit and the signal synthesizer according to aspects of the invention, wherein a legend designates certain of the illustrated blocks;

Fig. 4 is a block diagram of one of the analyzing stages used in the iterative calculations of the spectral analysis of Fig. 3 implementing an aspect of the invention; 5 is a block diagram of a modification which may be seen in a subsequent pair of the analyzing stages according to FIG. 4

in another embodiment of the invention; FIG. 6 is a block diagram of one of the synthesizing stages used in the iterative method of signal analysis according to FIG

the spectral components is used; Figs. 7, 8, 9 and 10 are block diagrams of representative spectrum conversion circuits of Fig. 3 for use in the invention;

Fig. 11 is a block diagram of a modification of the system illustrated in Fig. 3, which is used when timing the spectrum samples for processing, according to one aspect of the invention; 12 is a block diagram of a two-dimensional spatial frequency spectrum analyzer using a pipeline

13 shows a block diagram of a circuit for synthesizing signals describing the sample half-tone image; FIG

from the spectrum analyzer of Fig. 12, from its output spectra. As shown in Fig. 1, each signal transmission circuit has a set of N series-arranged transmission devices 100-1 to 100-N including two input terminals for sampled signals and two output terminals (N is an integer> 1). A first of two input terminals of the first transmission device 100-1 of the set is supplied as an input signal with a given time signal G ₀ , which defines information. The temporal signal Go may be a continuous analog signal (such as a sound signal or a video signal), or alternatively, the temporal signal Go may be a sampled analog signal; Furthermore, in the latter case, each sample may be represented directly by an amplitude level or indirectly by a digital number (for example, by passing each sample amplitude level through an analog-to-digital converter, not shown in Fig. 1, before the timing signal G ₀ the first input terminal of the transmission device 100-1 is supplied). The frequency spectrum of G ₀ is in a range between 0 (ie DC) and frequency f ₀ (ie a range containing all frequencies of interest corresponding to information with a given number of dimensions). Specifically, G ₀ may be a prefiltered signal that does not contain frequencies greater than fo. In this case, the clock frequency 2f _{0 of} the transmission device 100-1 fulfills the Nyquist criterion for all frequency components of f ₀ . However, in the alternative, Go may contain some frequency components that are higher than fo and are not of interest. In this latter case, the Nyquist criterion is not met and aliasing effects occur. From a practical point of view, such aliasing effects (if not too large) can often be tolerated, although they are undesirable. Referring to Figure 1, the first input port of each of the other transmission devices 100-1 ... 100-N of the set is coupled to the first of two output ports of the immediately preceding transmission device of the set. Specifically, the first output terminal of the signal transmission device 100-1 is coupled to the first input terminal of the transmission device 100-2; the first output terminal of the transmission device 100-2 is coupled to the first input terminal of the transmission device 100-3 (which is not shown) ... and the first output terminal of the transmission device 100- (N-1), which is also not shown, is with coupled to the first input terminal of the transmission device 100-N. In this way, the signal processing circuit illustrated in Figure 1 uses a pipelined structure in coupling each of the individual transmitters of the set to another.

The second of the two input terminals of each of the set of transmission facilities 100-1 ... 100-N is supplied with a separate sampling frequency clock. Specifically, the transmission device 100-1 is supplied with a sampling frequency clock CL ₁ at a second input, the transmission device 100-2 is supplied with a sampling frequency clock CL2 at a second input ... and the transmission device 100-N is supplied with a sampling frequency clock CL _n at its second input , The relative values of the clocks CLi ... CLn with respect to each other are limited in the manner indicated in FIG. The importance of these limitations will be explained in detail later.

Further, the transmitter 100-1 provides a second output signal L ₀ at its second output port. Similarly, the other transmitters 100-2 ... 100-N of the set provide corresponding second output signals L ₁ ... L _n at their respective second output ports _ · ,.

Each one of the transmission devices 100-1. ..100-N of the set, regardless of its particular internal structure, may be considered as a black box having a low-pass transfer function between its first input terminal and its first output terminal for the frequency spectrum of the information component of the input signal applied to its first input terminal. This low-pass transfer function of each transmission 100-1,100-2 ... 100-N of the set further has a nominal cut-off frequency drop, which is a direct function of the sampling frequency of the clock applied to the second input port. As noted earlier, in the case of the Burt pyramid, the drop may be gradual rather than steep.

In detail, the already mentioned input signal Go is supplied to the first input of the transmission device 100-1. The highest frequency of interest in the frequency spectrum of Go is not greater than f ₀ . Further, the sampling frequency clock CL applied to the second input terminal of the transmitter 100-1 is equal to 2f ₀ (thus having a frequency which satisfies the Nyquist criterion for all frequencies of interest within the frequency spectrum of Go). In this case, the low-pass transfer function between the first input terminal and the first output terminal of the transmitter 100-1 is such that only those frequencies within the frequency spectrum of G ₀ that are not greater than fi (where fi is less than f ₀ ) to the first output terminal the transmission device 100-1. In this way, at the first output terminal of the transmission device 100-1, there is provided an output signal G ₁ whose frequency spectrum (which is determined by the specific characteristics of the low-pass transmission function) consists mainly of the lower part of the frequency spectrum of G ₀ . This signal G ₁ is then supplied as an input signal to the first input terminal of the transmission device 100-2.

As shown in Fig. 1, the sampling frequency clock CL ₂ (which is applied to the second input terminal of the transmitter 100-2) is lower than 2fo (the sampling frequency of the clock CL ₁ ) but at least equal to 2fi (twice the maximum frequency f i in the frequency spectrum of G) _1). it is therefore the sampling frequency of the clock CL _{2 is} still sufficiently high to satisfy the Nyquist criterion for the frequency spectrum of G _1, which is supplied to the first input terminal of the transmission device 100-2, however, it is not high enough the Satisfies the Nyquist criterion for the highest possible frequency f _{0 of} interest in the frequency spectrum of Go supplied to the first input port of the immediately preceding transmission device 100 - 1. This type of relationship (in which the sampling frequency of the second input port of the transmission means of the set Bar gets lower when the order position of this practice the rate of charge of the sentence is higher) applies in general. Specifically, the clock supplied to the second input terminal of each of the transmission means 100-2 ... 100-N of the set has a sampling frequency which is (a) lower than the clock supplied to the second input terminal of the immediately preceding transmission means of the set, (b) at least equal is the double maximum frequency of the information component of the signal applied to its first input port, and (c) downshifts the nominal cutoff frequency for the low pass filter function to a value lower than that of its immediately preceding transmission device of the set. Thus, the maximum frequency f _{2 of} the signal G ₁ appearing at the second output terminal of the transmitter 100-2 is less than fi ... and finally the maximum frequency fu in the frequency spectrum of the signal Gn (the one at the first output terminal of the transmitter 100-N occurring) lower than the frequency fN-i of the frequency spectrum of the signal Gn -i (occurring at the first output terminal of the unillustrated transmitter of the set immediately preceding the transmitter 100-N and applied to the first input terminal of the transmitter 100-N) , Looking again at each of the transmission devices 100-1 ... 100-N as a black box, then each of the individual output signals L ₀ ... L _n - _1r corresponds to each of the second output terminal of each of the transmission devices 100-1 to 100 -N of the set, the difference between the information component of the signal supplied to the first input terminal of this transmission device and a direct function of the information component of the signal supplied at the first output terminal of this transmission device. Thus, L _{0 is} equal to or at least equal to the difference G ₀ ^ (G ₁ ), as indicated in Fig. 1, where glG ^ is either G ₁ itself or a direct function of Gi specified in a particular way. Likewise, L _{1 is} equal to (or equal to at least) G _r g (G ₂ ); .... L _n -! is equal to (or equal to at least) G _n - rg (G _N ).

The signal processing circuit shown in Fig. 1 analyzes the original signal Go into a plurality of parallel output signals composed of the Laplace outputs L ₀ , L ₁ ... L _n - 1 (respectively at the second output terminal of each of the respective pipeline structure transmission facilities 100-1 ... 100-N of the set) plus a residual Gaussian output G _n (originating at the first output terminal of the last transmission device 100-N of the set).

In general, the only restrictions on the relative values of the respective sampling clock frequencies f _o ... FN_i are those indicated in FIG. However, it is usually preferable to specify values of the sampling clock frequencies supplied to the second input terminal of each of the respective transmission devices 100-1 ... 100-N so that the respective ratios CL ₂ ZCL ₁ , CL ₃ / CL ₂ ... .CL _N / CL _N _τ are equal to 1/2 (or they may also be an integer power of 1/2 corresponding to the number of dimensions of the information component of the signal to be analyzed). This results in a division of the analyzed output of the frequency spectrum of the original signal G ₀ into separate parallel frequency bands of the Laplace component signals L ₀ ... L _n -1 (ignoring any sampling errors due to losses of the signal information by reducing the sampling density or due to the addition transient aliasing frequency components) each have a bandwidth of one octave for each dimension of the computer interest component and contain only those frequencies which are in the frequency spectrum of the original signal G ₀ and fall into that particular octave. These frequencies of the frequency spectrum of the original signal G ₀ which fall below the Laplace component signal L _n - 1 of the lowest octave are then included in the residual Gaussian signal Gn of the analyzed output.

Generally, N is an integer of any given value of 2 or more. However, there are types of information in which a relatively small given value of N may be sufficient to analyze all frequencies of interest in each dimension of the frequency spectrum of the original signal G ₀ with sufficiently high resolution. For example, is often found in the case of visible images a value of 7 for N sufficient so that in this case, the frequencies in each dimension of the residual signal Gn is smaller than 1 / 128th (1/2 ⁷⁾ of the highest interest frequency f _o of the frequency spectrum Go of the original signal are

 Fig. 1a shows in general form a digital version of a first type of transmission devices 100-1 ... 100-N of

In Fig. 1a, this first embodiment of each of the transmission means is 100-1 ... 100 (N-1) of the 10Oa-K set and the first embodiment of the immediately following transmission means of the theorem 10Oa- (K-1).

The transmission device 10Oa-K consists of a digital convolution filter 102 with m-taps (where m is an integer> 3, preferably odd), further a decimator 104, an expander 106, a digital interpolation filter 108 with n-Abgriff (where η is an integer> 3, preferably odd) is a delay circuit 109 and a Subtrahierschaitung 110. the Abtastfrequenztakt CL _K (of FIG. 1, each transfer means of the set 10Oa-K is supplied to the second input terminal) is each of the elements 102,104,106,108,109 and 11OaIs control signal fed.

The signal G _K -1 supplied to the first input terminal of the transmission device 10Oa-K is supplied to the convolution filter 102 and via a delay circuit 109 to an input of the subtraction circuit 110. The sample densities shown in Fig. 1a are those per dimension of the information signal. Specifically, the signal G _K -1 has a sample density in each dimension of the information signal plotted in the time plane as the sampling rate of the clock CL _{K of} the transmitter 10Oa-K. In this way, each of the samples formed by G _K -1 is processed by the filter 102. The purpose of the convolution filter 102 is to reduce the maximum frequency of its output signal Gk with respect to the maximum frequency of its input signal Gk-1 (as already explained above in connection with FIG. 1). However, the sample density at the output of the filter 102 is still the sampling rate CL _K , as indicated in FIG. The output signal of the filter 102 is supplied to the decimating circuit 104 as an input signal. The decimator circuit allows only certain (not all) of the successive samples in each dimension supplied to its input from filter 102 to reach its output. In this way, the sample density in each dimension at the output of the decimator 104 is reduced in sample dimension density in that dimension at the input to the decimator circuit 104. Like FTg. 1 a, the sampling density CL _K +1 in each dimension at the output of the decimator 104 is such that it can be plotted in the time plane at a reduced rate determined by the reduced sampling frequency clock CL _{K +} 1 which at the second input terminal immediately following transmission device 10Oa- (K + 1) has been supplied. Furthermore, the samples of reduced sample density in each dimension of the signal G _{K appear} at the output of the decimator circuit 104 when applied in the time plane in phase with the occurrence of the sampling frequency clock CLk +1 which is applied to the second input terminal of the immediately following transmission equipment 10Oa- (K + 1). is supplied. In Fig. 1a, the output signal Gk from the decimator 104 (that is, the signal at the first output terminal of the transmitter 10Oa-K) is supplied to the first input terminal of the immediately following transmitter 10Oa- (K + 1). Thus, the isochronous relationship between the reduced sample density samples of Gk at the first input terminal and the CLK ₊ 1 reduced sampling frequency clock at the second input terminal of the transmitter 10Oa- (K + 1) is similar to the isochronous relationship between the higher sample density of the samples of G _K -1 at the second input terminal of the transmission device 10Oa-K at the first input terminal and the higher Abtastfrequenztakt CL _K (as explained above). A preferred embodiment of the decimator circuit 104 is, but is not limited to, one that reduces the sample density at its input in that dimension by half in each dimension of the signal information. In this case, the decimator 104 in each dimension passes every other sample at its input to its output. The Abtastwertdichte CLk therefore is equal to +1 (1/2) ¹ or half as large as the Abtastwertdichte CL _K for a one-dimensional signal information. For a two-dimensional signal information the Abtastwertdichte CL _K +1 in each of the two dimensions is a semi-, so that a two-dimensional Abtastwertdichte of (1/2) ² or 1/4 is obtained.

Although the baseband frequency spectrum of G _{K is} the same at the input of decimator 104 and at its output, the reduced sample density signal Gk at the output of decimator 104 results in a loss of some amount of phase information present in the higher sample density signal G _{K associated with} the signal Input of the decimator 104 is supplied, is present.

The output signal from the decimator circuit 104 is also supplied to the first input terminal of the immediately following transmission device also to an input of the expansion circuit 106. This sets as additional sample a zero (a digital number representing the level 0) to each sampling position of the clock CL _K , where a sample from the output of the decimator 104 is missing. In this way, the sampling density at the output of the expansion circuit 106 is brought back to the sampling density at the input to the decimator circuit 104. In the preferred case in which the sampling density has been reduced by 1/2 in each dimension, the expansion circuit 106 in each dimension adds a 0 between each pair of adjacent samples in that dimension at the output of the decimator 104.

As the expansion circuit 106 increases the sampling density at its output opposite its input, it does not in any way change the information of the signal Gk at its output with respect to its input. However, the insertion of zeroes has the effect of adding images, or repeats the information of the baseband signal Gk which occurs as harmonics of the sideband frequency spectra CL.

The signal G _K at the output of the expansion circuit 106 then passes through the interpolation filter which is a low-pass filter and passes the baseband signal G _K , but suppresses the harmonics of the sideband frequency spectra CL. Therefore, the filter 108 replaces each of the zero-valued zero samples with interpolation value samples, each of which has a value determined by the respective values of the information-containing samples surrounding it. The effect of these interpolation value samples is to define the envelope of the higher resolution information-containing samples. In this way, the high-frequency components of the signal G _K at the output of the expansion circuit 106, which are above the baseband, are substantially removed by the interpolation filter 108. However, the interpolation filter 108 does not add any information to the interpolated signal G _K at its output that would not already be present in the reduced sample density signal Gk at the output of the decimator 104, and may not. In other words, the expanding circuit 106 serves to expand the reduced sampling density in each dimension of the signal G _K again to the sampling density in each dimension of the signal G _K at the output of the convolution filter 102.

The subtracter 110 subtracts the signal G _K appearing at the output of the interpolation filter 108 from the signal G _K -i, which has been supplied to the first input terminal of the transmission device 10Oa-K and has been supplied as an input to the convolution filter 102 and the delay circuit 109 of the subtractor 110 , The

Delay circuit 109 provides a delay equal to the total delay caused by convolution filter 102, decimator 104, expander 106, and interpolation filter 108. Thus, since both subtracting circuits 110 have the same sampling density CLk in each of their dimensions and are equally delayed, the subtracting circuit 110 subtracts the level represented by the digital number of each sample of the input signal Gk supplied thereto from the level represented by the digital number Therefore, the output signal of the subtractor 110 represents the Laplace signal L _K _i which is derived at the second output terminal of the transmitter 10Oa-K.

Only those signal components of Gk -i which are not present also in the subtractor 110 supplied signal Gk are included in the output of the subtractor 110 in the Laplace signal Lk -i. A first such component consists of the high-frequency part of the frequency spectrum of the signal G _K -1, which lies above the passband of the convolution filter 102. For example, if the transmitting device 10Oa-K of the transmission device 100-1 of FIG. 1 corresponds, then the first component of L _K _ ι (L _0), the frequencies of the frequency spectrum of G _K -1 (G ₀₎ within of the passband of f | lie to f ₀ . In addition to this component, the Laplace output L _K -1 from the subtracter 110 also includes a second error compensation component of frequencies within the passband of the convolution filter 102 substantially corresponding to the phase information included in the higher sample density signal Gk at the output of the convolution filter 102 had been lost to the decimation process (discussed above). Thus, the lost phase information in the (decimated) reduced sampling density (decimated) signal, which is passed to the first input terminal of the immediately following transmitter 10Oa- (K + 1), was substantially retained in the Laplacian signal Lk -1 which is present at the second output terminal of the transmitter 10Oa -K arises.

Each of the transmission devices 100-1... 100-N may have the structure of the transmission device 10Oa-K according to FIG. 1a. In this case, the residual signal G _n at the analyzer output provided at the first output terminal of the last transmission device 100-N of the set has a sampling density in each of its dimensions less (preferably half) than the sampling density in each dimension of the signal G _N is -i which is fed to its first input. However, since by definition no transmission means of the set of transmission equipment 100-N follows, it is unimportant for most applications (but except for applications in compressed data transmission) that the sampling density of the residual signal Gn is less than the sampling density of the signal Gn-i, which is supplied to the first input terminal of the transmission device 100-N. Therefore, in this case, the last transmission means 100-N of the set may be alternatively constructed as shown in Fig. 1c instead of the whole structure of the transmission means 10Oa-K (although each of the other transmission means (100-1 ... 100 (N-1) of FIG In the first embodiment, the output signal Gn of the convolution filter 102 (which has the same sampling density in each of its dimensions as the signal Gn-i supplied to the input of the convolution filter 102) is shown in FIG ) is not passed through a decimator circuit, but is directly passed on as the residual output signal G _n from the last transmission device 10Oa-N of the set of the first kind, since in this case no decimation has taken place no expansion and interpolation is required the signal Gn at the output of the convolution filter 102 is supplied directly as an input signal G _{n of} the subtracting circuit 110. In other words, the structure of the transmission device 10Oa-N of Fig. 1 c differs from that of the transmission device 10Oa-K of Fig. A by omitting the decimator 104, the expansion circuit 106 and the interpolation filter 108. In this case, the delay circuit 109 provides a delay which is only equal to that due to the convolution filter 102. The first type shown in Figure 1a (or alternatively that of Figures 1a and 1c) represents a real time implementation of the Burt pyramid algorithm. In its most useful form, of course, each of the Laplacian components at the analyzer output signal has derived from the Burt pyramid algorithm, a one octave bandwidth in each of its directions. This useful form of the Burt Pyramid Algorithm is achieved in real-time implementation according to Fig. 1 a that one half as large as the Abtastfrequenztakt CLk makes the Abtastfrequenztakt CL _K +1 in each dimension in this dimension.

Now describe another type of hierarchy pyramid that is an alternative to the Burt pyramid. This alternative pyramid is called a Filter Subtraction Decimation Pyramid (FSD Pyramid). Although this FSD pyramid does not possess certain desired properties of the Burt pyramid, it does have certain other desirable properties that the Burt pyramid itself does not have. For example, a desirable property of the Burt pyramid (which does not have the FSD pyramid) is its inherent compensation for random aliasing frequencies in the synthesis of the reconstructed original signal occurring in each of the respective Laplace components and residual components in the analyzed output signals. In certain applications, however, the FSD pyramid requires less equipment and can therefore be cheaper than the Burt pyramid realize.

The pipelined signal transmission device according to the invention is also useful for the real-time realization of the FSD pyramid. The FSD pyramid comprises a second type or species of structural design for the individual sample signal transmitters 100-a ... 100-N of the set shown in FIG. 1 using transmission means or stages such as stages 100 bK according to FIG. 1 b (instead of the transmission devices 10Oa-K used in the Burt pyramid described above).

The transmission device 110b-KFig.1b shows a digital version of the above-mentioned second type, in which each individual transmission device 100-1 ... 100 (N-1) of the set of FIG. 1, the transmission device shown in FIG 10Ob-K and 10Ob- (K + 1) are used. Furthermore, the transmission device 10Ob- (K + 1) according to FIG. 1 b represents that of the transmission devices 100-1... 100-N of the set, which immediately follows the transmission device 100 bK. As shown in FIG. 1 b, the transmission device 10Ob-K has a one-tap digital convolution filter 102, a decimator 104, a delay circuit 109, and a subtractor 110. The structural configuration of the second type transmission device 100 bK of FIG. 1 is similar to that of the first type transmission device 10Oa-K (FIG. 1 a) except that the signal G _K -1 (with a sampling density CL _K ) is applied to the filter 102 is supplied as an input signal via the delay circuit 109 and the subtractor 110 as an input signal and that the output signal G _K (also with the sampling density CL _K ) is sent through the decimator circuit 104 to each dimension of the sampling density of

Reduce signal Gk to CLk +1 before the reduced sampling density signal Gk is supplied to the first input terminal of the immediately following transmission device 10Ob- (K + 1).

The transmission device 10Ob-K of the second type differs from the transmission device 10Oa-K of the first type in that the G _K input of the subtractor 110, the signal Gk the sampling density CL _L (in each dimension), which from the output of the filter 102 on the input of the decimating circuit 104 is supplied immediately. More specifically, this is different from the transmitting device 10Oa-K of the first kind, which the signal Gk reduced sampling density CL _K + ι used (in each dimension) at the output of the decimation circuit 104th The first type thus requires the expansion circuit 106 and the interpolation filter 108 to restore the signal Gk to its sampling density CLk (in each dimension) before being supplied to the pK input of the subtracting circuit 110. Since the input signal Gk of the subtracting circuit 110 of the second type transmitting device 100bK is not derived from a decimated sampling density source, no expanding circuit 106 and no interpolation filter 108 are needed in the transmitting device 10Ob-K. Thus, referring to Figure 10, the delay circuit 10 provides a delay which is equal to the delay caused by the convolution filter 102. Furthermore, the output signal L _K -1 of the subtractor 110 consists of only those relatively high-frequency components of the frequency spectrum of the signal G _K -i, which are not present in the signal G _K at the output of the convolution filter 102.

According to the second type, the last transmission device 100-N of the set may also have the structural design of the transmission device 10Ob-K or alternatively the structural configuration according to FIG. 1 c.

The respective embodiments of the first and second types according to Figures 1 a and 1 b are digital versions. In such digital embodiments, an analog-to-digital converter is initially used to convert an analog signal to digital level samples, with the level of each sample normally represented by a multi-bit binary number. However, it is not essential that the first or second type or species of the inventive arrangement be realized in digital form. Sample coupled charge coupled devices (CCDs) are well known in the art. For example, CCD transversal filters, such as split-gate filters, can be designed as convolution filters or interpolation filters. CCD signals consist of a series of discrete samples, but each sample has an analog amplitude level. Thus, the invention can be carried out either in digital or in analog form. The filter characteristics of a tapped filter depend on factors such as the number of taps, the effective time delay between the taps and the specified amplitude levels, and the polarity of the respective weighting factors associated with the individual taps. For purposes of illustration, it is assumed that the convolution filter 102 is a one-tailed five tap filter. Fig. 2 shows an example of the specified magnitude levels of the weighting factors, all of which have the same polarity (positive in Fig. 2) and associated with the five individual taps, respectively. It also shows the deficient time delay between each pair of adjacent taps. More specifically, as shown in FIG. 2 indicates, the effective time delay between each pair of adjacent taps 1 / _K CL, so the sampling period, which is defined by the AbtastfrequenztaktCL _K, which addition convolution filter 102jedereinzelnenderÜbertragungseinrichtungen 100-1 ... 100-N of the first or second Species (as shown in Figs. 1 a, 1 b and 1 c shown) is supplied individually. Thus, the absolute value of the time delay CL _{K of} the convolution filter 102 of each transmission device 100-1 ... 100-N is greater than that of the immediately preceding transmission device of the set.

Referring to Fig. 2, the weighting factors associated with the five taps all have positive polarity and specified size levels (special values) symmetrically distributed around the third tap. More specifically, the weighting factors associated with the third tap in the embodiment of Fig. 2 have specified values of 6, the respective weighting factors of the second and fourth tapes having the same specified lower value 4, and the weighting factors respectively at the first and fifth tapes have the same even lower specified ones Value 1. The weight factor 200 envelope 202 defines the kernel or hull function (and hence the shape of the frequency-domain filter characteristic) of the convolution filter 102 of each of the transmitters 100-1 ... 100-N of the set. Firstly, because all of the samples 200 are of the same polarity (positive in Figure 2), second symmetrically about the center tap (third tap) and thirdly the smaller the sample the farther away from the center sample, the convolution filter 102 has a low pass filter characteristic in each one the respective transmission devices 100-1 ... 100-N of the sentence. While in Fig. 2 all weighting factors have the same (positive) polarity, this need not be so with a low-pass filter. Some of the weighting factors may have the opposite (negative) polarity as long as the algebraic sum of the weighting factors is different from zero. The kernel function form (e.g., envelope 202 of FIG. 2) may be the same for all convolution filters 102 of the respective transmitters of the set, so that the relative low pass frequency characteristics (the shape of the frequency-domain filter curves) will be the same for all filters 102 (though is not necessary). However, the absolute value of the nominal lowpass cutoff frequency of the filter has a rating for each one of the transmitters, which depends on the sampling frequency period 1 / CLk for that filter. By appropriate choice of the levels or magnitudes of the weighting factors 200 (which do not have the special values 1,4 and 6 of Fig. 2), one can achieve a nominal low pass cutoff frequency for the signal Gk at the output of the convolution filter 102 (which has a sampling density CLk in each dimension ), which is substantially half of the maximum frequency (or, in the case of Ga, the highest possible frequency of interest f ₀ ) of the input signal G _K -1 for the convolution filter. In this case, the decimator 104 in each dimension reduces the one-dimensional sample density of the signal Gk to CLk / 2 by suppressing every other sample in that dimension. However, the signal G _K (determined by sampling envelope 202) at the output of decimator circuit 104 remains substantially the same as at its input (although some loss of phase information due to the lower sampling density occurs at the output of decimator circuit 104).

There will now be described certain preferred embodiments of the real-time realization of the Burt pyramid, which form the first species (Figure 1 a) of the type according to Figure 1.

Reference is made to Fig. 3, which shows a system block diagram of a spectrum analyzer, a spectrum changing circuit and a signal synthesizing circuit which process an electrical signal representing one-dimensional information (such as any signal type containing time-varying information).

According to FIG. 3, the original electrical signal whose spectrum is to be analyzed is supplied in analogue form to an A / D converter 305 for digitization. The digital output of the

A / D converter 305 is denoted by G ₀ . The higher frequency output due to G ₀ , a high pass spectrum L ₀ , is extracted in a zero order analyzer stage 310, leaving G ₁ , a low pass filtered output due to VOnG ₀ . The higher frequency portion of G ₁ , a bandpass spectrum L ₁ , is extracted in a first order analyzer stage 315 so that G ₂ remains, a low pass filtered output due to G ₁ . The higher frequency portion of G ₂ , a bandpass spectrum L ₂ below the bandpass spectrum Li, is extracted in a second order analyzer stage 320, leaving G ₃ , a low pass filtered output signal due to G ₂ . The higher frequency component of G ₃ , a bandpass spectrum L ₃ below the bandpass spectra L ₁ and L ₂ , is extracted in a third order analyzer stage 325, leaving G ₄ , a low pass filtered output signal due to G ₃ . The higher frequency portion of G ₄ , a bandpass spectrum L ₄ below the bandpass spectrum L ₃ , is extracted in a fourth order analyzer stage 330, leaving G ₅ , a low pass filtered output signal due to G ₄ . The higher frequency portion of G5, a bandpass spectrum below the other bandpass spectra, is extracted in a fifth order analyzer stage 335, leaving G ₄ , a low pass filtered residual output due to G ₅ . The output signal G ₆ is practically a six times low-pass filtered output signal due to the original signal G ₀ .

Analyzer stages 310, 315, 320, 225, 330 and 335 include input low pass filter stages 311, 316, 312, 326, 331 and 336, respectively, with increasingly narrower passband widths. The low pass filtered outputs of these filters 311 through 336 are sufficiently narrower than their input signals so that they can be resampled at a reduced rate before being passed to the next analyzer stage. The reduction of the samples is made by selection on a regular basis (such as by decimation) in decimation circuits 312, 317, 322, 327, 323, 337 which follow the filters 311, 316, 313, 323, 331 and 336, respectively. In octave-wise spectral analysis, which is particularly convenient, every second sample is suppressed by the decimation process.

The higher-frequency components of the input signal supplied to each analyzer stage are extracted by removing the low-frequency components from the input signal. The decimated low frequency portion of the input signal leads to the problems of being undesirably present in a lower resolution sampling matrix than the input signal and being undesirably delayed from the input signal. The first of these problems is solved in expansion circuits 313, 318, 323, 328, 333, 338 by applying zeros to the missing sample points in the sample matrix of the low pass filter output signal and then eliminating the simultaneously introduced random harmonic spectra by low pass filtering. The second problem is solved by delaying the input signals of the analyzer stages before subtracting from them the expanded low pass filter output signals provided by the expansion circuits 313, 318, 333, 333, 338.

The delay and subtraction operation is performed in circuits 314, 319, 324, 329, 334, 339 included in the analyzer stages 310, 315, 320, 325, 330, 335, respectively. (In certain cases, components may advantageously be shared by the input lowpass filters and the delay and subtractor circuitry of each analyzer stage, as will be described.)

The spectral analysis just described has a pipeline nature, and there is an increasingly longer time shift of the samples L ₁ , L ₂ , L ₃ , L ₄ and L ₅ compared to the samples L ₀ . The term "time shift" as used herein refers to differential time delays of predetermined known amounts occurring between the respective samples of the information-related parallel signals, such as between corresponding samples of the analyzed output signals L ₀ , L ₁ , L ₂ , L ₃ , L ₄ , L ₅ and G ₆ of the spectrum analyzer shown in Figure 3. the still to be described signal synthesis from the spectrum method requires an opposite time shift corresponding sets of samples. This can be by means of delay lines 340,341,342,343 and 344 (typically in the form of shift registers or other types of memory which perform the equivalent function, ie a memory to be written in series and read out) for the samples L ₀ , L ₁ , L ₂ , L ₃ and L ₄ before they are changed in the circuits 345, 346, 347, 348 and 349 respectively, as shown in FIG. 3 shows, alternatively k can the spectra changed and associated with the modified spectrum sample are increasingly delayed. Whether the delay can be split in various ways and before and after the change, for example, to perform spectrum changes in parallel time. Understandably, within the varying circuits 345, 346, 347, 348, and 349, even different delays may be used as part of the overall different delay requirements in some examples.

The spectra L ₅ and G 6 are changed in changing circuits 350 and 351. In some signal processing applications, the modifiers 345 to 351 may not be needed and replaced by direct connections, respectively. The spectral analysis methods described so far can be extended by using additional analyzer stages or truncated using fewer analyzer stages. In such cases the remaining low-pass spectrum G _n at the end of the spectral analysis is not G ₆ .

In the signal synthesis by recombination of the spectral analysis components, possibly in an altered form, the decimation of the sample matrix from analyzer stage to analyzer stage must be undone so that the spectral samples can be summed by adders 353, 355, 555, 595, 633, 633. This is in addition to the correction of the time shift in the delay circuits 340 to 344. The decimation is canceled by means of expansion circuits 352, 354, 356, 358, 360 and 362 which are substantially equal to the expansion circuits 338, 333, 328, 333, 318 and 313, respectively. By multiplexing, a single circuit can perform a dual task. The remaining low-pass spectrum Gn is advanced in time relative to the adjacent band-pass spectrum L ^ ₁ , so that its expansion aligns its sample with that of the signal L ^ ₁ . G n is G ₆ in FIG. 3 which is changed in the expansion circuit 52 (new G ₆ ') and expanded, and then added in the adder 353 to the changed signal L _{1 (} L 5 in FIG. 3), so that a synthesized new one Signal Ga-i (L ₅ in Figure 3) is added, so that a synthesized new signal G _n ^ (new G ₅ ') is formed. The output of the adder 353 is expanded into the expansion circuit 354 and added in the adder 355 to the delayed and changed signal L ₄ , so that the new signal G ₄ , is synthesized. The output of the adder 355 is expanded in the expansion circuit 354 and added to the delayed changed signal L ₃ in the adder 357 so that the new signal G _{3 is} synthesized. The output of the adding circuit 357 is expanded in the expansion circuit 358 and added in the adding circuit 359 to the delayed and changed signal L ₂ to the synthesized new signal G ₂ . The output of the adder 359 becomes in the expansion circuit 60

expanded and added in the addition circuit 361 to the delayed and changed signal L ₂ to the synthesized new signal G ₁ ,. Finally, the output of the adder 361 in the expansion circuit 362 is expanded and added in the adder 363 to the synthesized new signal G ₀ '. The new signals G ₀ ', G ₁ ', G ₂ ', G ₃ ', G ₄ ', G ₅ ' and G ₆ 'are indicated by dashes in the signal synthesizing circuit according to FIG. The new signal G ₀ , if desired, can be converted into analog form by means of a digital / analog converter (not shown).

The expansions in circuits 352, 354, 356, 358, 360, 362 provide suppression above the band at each step of the synthesis process. If the bandpass spectra are not wider than one octave, then this results in suppression of any harmonics generated by the modifiers 345 to 351 which would otherwise affect the signal synthesis by introducing random alias frequencies Figure 9 shows in more detail the construction of the spectral analyzer stage for one-dimensional information, such as the steps 310, 315, 320, 25, 330, 303 or 335 used for the octave spectral analysis The stage is the Kth order spectral analyzer, where KNuII or a positive integer Clock rate for this stage, a rate R for the sampling of the original input signal G ₀ , whose spectrum is to be analyzed.If K is a positive integer, then the clock frequency decreases by 2 _K.

The input signal G _K is applied to the spectrum analyzer stage of Fig. 4 as input to a M-stage shift register 470 which is clocked at a clock frequency of R ^ K. The (M + 1) samples with increasing latencies present at the input and outputs of shift register 470 form each of its output functions as a multi-tap delay line of a low-pass delay line filter. The samples are weighted and summed in circuit 471 to become samples of a linear-phase low-pass filter output G (K + n), except for the input stage which decimates the halved clock rate (as compared to the clock rate) at all analyzer stages where K is greater than zero the preceding stages) used in the initial shift register 70 and the adders of the weighting and summing circuit 471, the signal G _(K + υ versus the signal G _K - The output signal G _(K + d is supplied as an input signal to a multiplexer 472 which alternately selects its input signal G _K +1 and a zero signal with a switching rate of R / 2 _K and generates a signal G _(K + d *).

The signal G "+ d * has a baseband frequency spectrum which is twice the spectrum of G ( _K + υ and is mixed with a suppressed carrier harmonic double sideband spectrum with a peak amplitude G (K + d) The signal G (K + u * is fed as input signal to another shift register 473 having a plurality of stages (the number of stages may be the same or different.) The signal G (K + u *) is supplied as an input signal to a timed signal Gjk + d * instead of the signal G (K + υ of M) clocked at a rate of R / 2k. The (M + 1) samples formed by the input signal and the output signals from each stage of shift register 473 are applied to another weighting and summing circuit 474, which is similar to circuit 471 The circuit 474 suppresses a first harmonic spectrum of G _(K + d *) and provides the signal G _(K + 1> in expanded form as the abbreviation astmatrix with as many samples as the sample matrix of Gk

In an adder 475, this expanded form of Gk +1 is subtracted from Gk after Gk in the shift register 470 and a delay circuit 476 has been delayed. The delay of signal Gk by M cycles in shift register 470 compensates for the M / 2 cycle delay of the average sample for weighting and summing circuit 471 with respect to input signal Gk for the spectral analyzer stage of FIG. 4 and for the same M / 2 period delay between Gs (K ₊ d * and the middle sample for weighting and summing circuit 474. Delay circuit 476 provides a delay to compensate for delays that occur in the addition in weighting and summing circuits 471 and 474, and delay circuit 476 may simply pass through The output Lk from adder 475 is one of the wanted spectral analysis components whose lower frequency limit is determined by the low-pass filtering in the K-th spectral analyzer stage of Figure 4 and whose upper frequency gr is determined by the low pass filtering in the preceding spectral analyzer stage, if any. In Fig. 5, a possibility for reducing the number of shift register stages used in the spectrum analyzer according to the invention is shown. The samples for defining G <k + d *, which are weighted and summed to effect the low pass filtering associated with the interpolation of G _(K + d), are derived from the tapped delay line arrangement used to support the initial Low pass filtering of G (K + d in the following spectral analyzer stage is used, not by using the shift register 473.

FIG. 5 shows by way of example how it is performed between, for example, the zero-order analyzer stage used to generate L ₀ and the subsequent analyzer stage. Elements 570-0,571-0,575-0 and 576-0 are those elements in the zeroth order spectral analyzer stage which correspond to elements 470,471,475 and 476 of the K-order spectral analyzer stage of FIG. Elements 570-1 and 571-1 of the first order spectral analysis stage are analogous to elements 570-0 and 571-0 of the zero order spectral analysis stage, except that they are clocked at half the rate. The four samples taken from the input and the first three outputs of the shift register 570-1 are supplied in parallel at a clock rate R / 2. Between them zeroes are turned on and the results are weighted in two phase relationships by a seven filter weight pattern ABGDCBA to produce a few consecutive samples which are subtracted from the delayed signal Go in the subtraction circuit 575-0 at the clock rate R.

The earlier sample of each pair of consecutive samples to be subtracted from delayed signal G ₀ is obtained by multiplying the input of shift register 570-1 and its first three output signals by filter weights A, C, C and A in weight circuits 580,581,582 and 583 and then summing the weighted samples in the summing circuit 587. The intervening zeros would fall to the positions to be weighted with B, D, B in this positioning of G ₁ versus the filter weight pattern. The later sample of each pair of consecutive samples to be subtracted from delayed signal Go is obtained by multiplying the input of shift register 570-1 and its first two inputs by filter weights B, D and B in weight circuits 584, 585 and 586 and then summing the weighted samples in summing circuit 588. The intervening zeros would fall at locations to be weighted by A, C, C, A for this positioning of G versus the filter weight pattern. A multiplexer operating at clock rate R alternately selects between samples at the outputs of summing circuits 587 and 588 and provides one

Fig. 6 shows in further detail a stage of the signal synthesizing circuit according to Fig. 3. The samples of G _K * (or delayed and changed Gn) are interleaved with zeros in multiplexer 692, and the resulting expanded signal is input to a shift register 693 of M (or other number> 1) stages and clocked at the expanded sample rate , The input to the shift register 693 and the outputs from its stages are applied to a weighting and summing circuit 694. The spectrum G _K , (or G _n ), which is resampled at twice the rate and then has a harmonic structure, then passes from a weighting and summation circuit 694 to an adder circuit 695 where it matches the altered signal L _(K - _K ). d is combined and delayed in time to align with the resampled and filtered samples G _K - (or G _n ) with which it is added The multiplexer 692, the shift register 693, and the weighting and summing circuit 694 may be located in the Multiplexing operate to serve as elements 472,473 and 474 in the spectral analysis process.

At this juncture, it is convenient to consider the characteristics of low pass filtering used in low pass filtering of the spectral analysis method and in the expansion of spectral analysis and signal synthesis. The low-pass filtering is phase-linear, and thus the pattern of the filter weights is symmetrical about the middle sample (s). The filter weights add up to 1 in order to largely suppress low frequencies in the high-pass spectrum L ₀ and in the band-pass spectrums L ₁ , L ₂ , L ₃ . If the spectral analysis is octave-wise and the decimation in the recoding of the sub-band removed by the low-pass filtering in each spectral analyzer stage by a factor of 2, then it is desirable to remove frequencies below two-thirds of the octave center frequency in the low-pass filtering. A stepped frequency characteristic of the filter (ie a steep drop in the filter characteristic) leads to overshoots in the filtered signals, whereby the dynamic range of both the function G _{(K +} d extracted by the spectrum analyzer stage _and that subtracted by the expanded signal G _(K + d of G _K generated function L _(K + u is increased. This is an example of the Gibbs phenomenon, which can be moderated by using a less abrupt discontinuance of the Fourier series. a number of demolition windows (windows truncation) are known which For example, Bartlett, Hanning, Hamming, Blackmann and Kaiser refer to Chapter 5.5 of the book "DIGITAL SIGNAL PROCESSING" by AV Oppenheim and RW Schäfer, published by Prentice-Hall Inc. , Englewood Cliffs, NJ, 1975: the headline of this chapter is "Design of FIR Filters Using Windows" and s See pages 239 to 251.

In practice, the number of samples in low-pass filtering is usually limited to a few. In filtering using an odd number of samples, the filter output signal comprises a direct component and a series of cosine harmonics, and in an even-numbered filter, the filter output signal comprises a direct component and a series of sine harmonics. The desired characteristic curve is approximated to the best match, with the help of a computer selecting the weighting factors according to a trial and error procedure.

It is also possible according to the invention to produce spectra with the same Q and widths other than octaves, but this appears less expedient. The decimation of the low pass filter output to select every third sample and filtering away frequencies below half the center frequency of the bandpass spectrum to produce a lowpass response results in a set of bandpass spectra whose bandwidth is increasingly narrowed by one-third, for example, by half.

The sample change circuits 345 to 351 of Fig. 3 may take various forms, and some of them may be replaced by direct connections. For example, to remove low-level background noise in the various spectrums, each of the altering circuits 345 to 351 may include a baseline limiting circuit 700 shown in FIG. Such a limiting circuit 700 can be easily realized by dropping the last-digit bits of the signal.

Fig. 8 shows a circuit which can be used for each of the spectrum equalizer modifiers 345 to 351. A rotary switch 897 is wired to give each of several shaft positions a binary code. This code is supplied via a latch 898 to a 2-quadrant multiplier to multiply the input spectrum samples to produce output spectrum samples which can be synthesized to produce Go. The latch 898 receives the code input to the multiplier 889 while changing the setting of the rotary switch 897. Any octave spectrum can be subdivided using digital filters using the same sampling rate as the octave spectrum derivative or halved sampling rate, and then adjusting the gains of the spectral divisions one at a time. The subdivision of the octaves into twelfths produces individual tone or halftone settings of, for example, encoded music signals.

The change circuits may be ROM memories for storing non-linear transfer functions. For example, in each of the sample varying circuits 345 to 351 of a transmitter, a ROM 990 storing a logarithmic form of the input signal may be used (Fig. 9), and in each of the corresponding sample varying circuits of a receiving device, a ROM 1091 may be used which stores an exponential form of the input signal (Fig. 10) so as to obtain a pre-emphasis of the signal before transmission and a de-emphasis after reception. Other complementary preemphasis and deemphasis characteristics may also be stored in the ROM modification circuits of the transmitter and receiver spectral analysis signal synthesis circuits.

Fig. 11 shows a modification of the spectrum analyzer and signal synthesis system of Fig. 3 with the delays between analysis and synthesis being divided so as to provide spectral samples without time delay for processing. Such alignment is desirable, for example, in a computational system where spectral analysis is used to separate signals into spectra prior to the expansion so that the companded spectra can be filtered to suppress distortions generated during rapid signal compression or expansion. The amplitude of the original signal applied to analog-to-digital converter 305 in FIG. 3 may be determined to generate in circuit 1130 a compensation control signal CC corresponding to each of compander 1110, 1111, 1112, 1111, 11, 11, 1115, 1116 in order to compander their companded signals with fast rise and slow decay (fast-attack, slow-decay compansion). The companders 1111 to 1116 may consist essentially of digital 2-quadrant multipliers, in which the control signal CC is derived from an analog-to-digital converter, which is connected downstream of the usual analog circuits to detect the signal to be companded and then an analogue

ComnansinnRstfmersinnal 711 or7f »iinp> n

The companders 1110, 1111, 1112, 1111, 11, 11, 11, 11 and 1116 operate on the spectra L ₀ , L ₁ , L ₂ , L ₃ , L ₄ , L ₅ and G ₆ , after using the delay circuits 1110, 1101, 1102, 1103, 1104 and 1106 have been differentially delayed to align the timing of their respective samples. The delay circuits 1120,1121,1122,1123,1124 and 1125 then shift the companded signals L ₀ ', L ₁ ', L ₂ ', L ₃ ', L ₄ ', L ₅ ' and G ₆ 'in an appropriate manner for the Signal synthesis using the elements 352 to 363 of FIG. 3.

The delays in the delay circuits 1106 and 1125 are substantially M / 2 cycles of the R / 2 ^K clock rate, where there are five or 16 M cycles of the base clock rate R, and this delay occurs in the compilation of samples for the weighting cycle. and summation circuit 474 of the last spectral analyzer stage 335. This delay of 16 M cycles is extended by the delay time D _{1 to} compensate for the addition times in the expansion circuits 338 and 352, and is further extended by a delay time D ₂ to increase the additional times in FIG of the delay and subtracter 334 and in the adder 353. It is assumed that all addition operations are performed with the base clock rate R and D ₁ and D ₂ can be expressed by numbers of these clock cycles. The delay in the delay circuit 1104 is longer than 16 M + D ₁ + D ₂ cycles of the clock rate R by the difference between the time required to develop L ₅ from G ₃ and the time required for the delay Development of L ₄ from G _{5 is} needed. The time required to develop L ₅ from G ₅ is M cycles of R / 2 ⁵ clock rates to collect two samples for weighting and summation, or 32 M cycles of the base clock rate plus 2D ₁ for two sets of sample summations plus D ₂ for the Abtubtubtraktion. The time required to develop L ₄ from G ₅ M / 2 cycles of R / 2 ⁴ clock rates to collect samples for weighting and summation or 8M cycles of the base clock rate plus D ₁ for sample sum plus D ₂ for sample subtraction. It takes 24 M + D ₁ cycles of the base clock rate additional delay to align the samples L ₄ with the samples L _{5 in time} . Thus, the delay circuit 104 has an overall delay of 40M + 2D ₁ + D ₂ cycles of the base clock rate R. Similar calculations indicate that the cycles of the base clock rate R by which the samples in the delay circuits 103, 102, 101 and 100 are delayed are 52M + 3D ₁ + D ₂ , 58M + 4D ₁ + D ₂ , 61 M + SD ₁ + D ₂ and (62 1/2) M + 6D ₁ + D _2, respectively.

The delay required by the sampling circuit 1124 in addition to the delay through the delay circuit 1125 is the time needed for the expansion in the circuit 354 and the delay D ₂ needed for the addition in the adding circuit 55. The former delay is M / 2 cycles of clock rate R / 2 ⁴ to collect samples for weighting and summation, 8M cycles of base clock rate R plus delay D ₁ required for summation in the weighting and summing process. The total delay in the delay circuit 1124 is then 24M + D ₁ + D ₂ . By similar calculations, the total delays in the delay circuits 1123, 112, 112, and 1120 in cycles of base clock rate R are expressed as 28 M + 3D ₁ + 3D ₂ , 3OM + 4D ₁ + 4D ₂ , 31 M + 5D ₁ + 5D _2, respectively (31 1/2) M + 6D ₁ + 6D ₂ .

Similar calculations may be used to determine the total delays in the delay circuits 340 through 344 of FIG. 3, assuming that the change circuits 345 through 351 all have the same delays. The delay circuits 340, 344, 316, 433, 344 and 345 each have delays expressed in cycles of the base clock rate R of 77 M + 12D ₁ + 7D ₂ , 76M + 10D ₁ + 6D ₂ , 72M + 8D ₁ + 5D ₂ , 64M + 6D ₁ + 4D _{2 and} 48M + 4D ₁ + 3D ₂ . The digital filtering used in the spectrum analyzer is a type or species of hierarchical filtering of general interest by performing low-pass or band-pass filtering that extends over many many samples with a relatively small number of samples weighted and summed at any one time.

Although the invention is also useful for the use of the one-dimensional signal information spectrum, the Burt pyramid has been developed to analyze primarily the spatial frequencies of two-dimensional image information. The invention allows a real-time spectral analysis of the spatial frequencies of changing image information as occurs in consecutive video images in a television display.

As is known in the television art, successive video frames (in NTSC format) sequentially occur at a frame rate of 30 frames per second. Each frame consists of a grid of 525 interlaced horizontal deflection lines. The successive odd-numbered horizontal deflection lines of a frame are transmitted consecutively during a first field period. The successive even-numbered deflection lines of one frame are successively transmitted during a second field period following the first field period. This is followed by the first field period of the next frame. The duration of each field period is 1 / 60th of a second. However, one must provide storage for at least the number of picture elements in a field time in order to be able to define the full spatial frequency spectrum of the picture in delayed real time.

A technique known as progressive scan is known in the television art to derive frames from the NTSC video signal with the entire 525 consecutive lines at a rate of 60 frames per second. In this technique, each successive NTSC field is delayed for a field period of 1 / 60th of a second. In this way, the successive deflection lines of a concurrent odd-numbered field are interleaved with the successive deflection lines of an immediately preceding even field which has been delayed by one field period so as to obtain a whole frame of picture elements during the concurrent odd-numbered field of each successive frame , Similarly, the successive even-numbered field deflection lines are interleaved with the successive odd numbered field deflection lines which have been delayed by one field period to yield a full frame of picture elements during this concurrent even field period of each of the successive frames ,

The above-described progressive scanning technique is particularly useful for the production of high-definition picture displays known as High Definition Television (HDTV), which is currently being developed in television technology. The invention is also suitable for HDTV to provide better image reproduction.

Fig. 12 shows a spectrum analyzer according to the invention for processing signals representing two-dimensional information, such as the spatial frequency image information contained in successive, progressively scanned television frames. Alternatively, such two-dimensional information can also be obtained from a non-interlaced television camera or from an interlaced camera with downstream memory.

Referring to Fig. 12, for simplicity of description, the monochrome processing of the luminance signals will be explained, however, the technique to be described may be applied individually to the primary colors of color television signals or to the signals derived therefrom by algebraic matrixing. An original video signal is fed in raster-scan format to an analog-to-digital converter 1205 for sampling (if unsampled) or resampling (if already scanned) and for final digitization. The digitized video samples are referred to as G ₀ signals and contain the full two-dimensional spatial frequency spectrum of the original signal and its harmonic spectra associated with the samples. These harmonic spectra are symmetrical about the sampling frequency and its harmonics. The harmonic spectra are treated specifically in the manner explained below. The general fact of their existence is mentioned because the harmonic spectra must be considered in the design of the two-dimensional low-pass spatial frequency filters used by the spectrum analyzer of FIG. The reason is that these harmonic spectra give rise to extraneous frequencies in the spectral analysis and the signal synthesis based thereon.

In the first-order spectral analyzer stage 1210, a high-pass spectrum L _{0 is} separated from G ₀ . This high pass behavior is essentially accomplished by low pass filtering Go and delaying G ₀ from its timing at which it comes out of the A / D converter 1205 by the same amount that the low frequency components of G ₀ in the low pass filter output delay and subtracting the low pass filtered output signal from the delayed signal G ₀ . Assuming that the spectral analysis is octave-wise, the cut-off frequency of the two-dimensional low-pass spatial frequency filter 1211 is set equal to the uppermost frequency of the next octave bandwidth bandpass spectrum L ₁ to be analyzed, ie four-thirds of its center frequency. In the decimation circuit 1212 alternate rows and columns of samples are eliminated to sample the low-pass filtered signal G ₀ with the spatial frequency rate of R / 2, and this signal with a reduced sampling rate is supplied as Tiefpaßausgangssignal the step 1210 for further spectral analysis. The low-pass-filtered signal G ₀ with a reduced sampling rate is then interpolated according to the methods described by RW Schafer and LR Rabiner in their article "A Digital Signal Processing Approach to Interpolation" on pages 692 to 702 of the journal PROCEEDINGS OF THE IEEE, Volume 61, 6, June 1973. In expansion circuit 1213, the samples eliminated in decimator 1212 are zerosed to form an input to another two-dimensional low-pass spatial frequency filter 1214. This filter may use the same sample weight coefficients as the initial one The resulting signal has an equally sized sample matrix as that of the signal Go delayed in the delay circuit 1215, and this is obtained from the delayed signal G ₀ in the subtractor 1216 subtracts to a high-pass output signal L ₀ . Not only is L ₀ the high pass portion of G ₀ , but it also contains low frequency phase error correction terms, as mentioned above, which are used in the re-synthesis of the video signal from spectral analysis, by the error introduced by the resampling G ₀ at the low sampling rate in the decimator 12 to compensate. This separation of the signal into a low-pass part which is resampled at half rate and into a high-pass part is repeated in each spectral analyzer stage. Each successive spectral analyzer stage receives as input the newly sampled lowpass output signal from the previous spectral analyzer stage, halving the sample rate in each successive spectral analyzer stage from that of the previous stage. The high pass output of each spectral analyzer stage 1 220,1 230,1 240,1 250,1260 after the initial stage 1210 has an upper bound determined by the low pass characteristic of the previous stage, and therefore these "high pass" output signals are in fact bandpass spectra The decimation of the output signals of the initial low-pass filters in each stage, which is by a factor of 2, and the cut-off frequency of the low-pass filters in each stage, which is two-thirds of the center frequency of the spectral analysis it effects, are factors which The decimated low-pass output G, the spectral analyzer stage 1210, is supplied from its decimator 1212 as an input to the next spectral analyzer stage 1220. The spectrum analyzer stage 1220 has elements 1 221,1 222,1223,1224 and 1 226 analog the elements 1 211, 212, 213, 1214, 1215 and 1216 of the spectral analyzer stage 1210; The differences in operation result from the fact that the sampling frequency in stage 1220 is halved in both dimensions with respect to stage 1210. The Taßpaßfilter 1221 and 1224 have weight coefficients equal to those of the low-pass filters 1211 and 1214; However, halving the sample rate in stage 1220 compared to stage 1210 halves the cutoff frequency of filters 1221 and 1 224 as compared to filters 1 211 and 1214. The delay before the subtraction in the delay circuit 1225 is twice as long as in the delay circuit 1215; Assuming that these delays are caused by clocking in a shift register or the like, the delay structures are the same, with the 2: 1 delay ratio given by the ratio 1: 2 of the respective delay clock rates in the delay circuits 1225 and 215. The high pass output signal Li of the spectrum analyzer stage 1220 is a bandpass spectrum of spatial frequencies immediately below the spectrum L ₀ . The decimated low-pass output G _{2 of} the spectrum analyzer stage 1220 is supplied from its decimator 1222 as an input to the spectrum analyzer stage 1230. The bandpass spectrum L ₂ one octave below Li is the high pass output of the spectrum analyzer stage 1230 due to its input signal G ₂ . The spectral analyzer stage 1230 includes elements 1231,1,232,1233,1234,1235 and 1,236, respectively, corresponding to the elements 1221,1222,1223,1244,225 and 1226 of the spectrum analyzer stage 1220 except for the halved sampling rates.

The decimated low-pass output signal G _{3 of} the Spektralanalysatorstufe 1 230 is supplied from its decimator 1 232 as input to the subsequent Spektralanalysatorstufe 1240. The bandpass spectrum L ₃ one octave below L ₂ is the highpass output of the spectrum analyzer stage 1240 due to its input signal G ₃ . Spectral analyzer stage 1240 includes elements 1241, 1224, 1224, 1224, 1245 and 1246, respectively, corresponding to elements 1231, 1232, 1323, 1234, 1235 and 1236 of spectral analyzer stage 1230, except for halved sampling rates. The decimated low-pass output G _{4 of} the spectrum analyzer stage 1240 is supplied from its decimator 1242 as an input to the next spectral analyzer stage 1250. The bandpass spectrum L ₄ one octave below L ₃ is the highpass output of the spectrum analyzer stage 1250 due to its input signal G ₄ . Spectral analyzer stage 1 250 includes elements 1 251, 1 252, 1 253, 1 254, 1 255, and 1 256 corresponding to elements 1 241, 1242, 1224, 1224, 1224, 1245, and 1246 of spectrum analyzer stage 1240, except for halved sampling rates.

The decimated low-pass output signal G _{6 of} the spectral analyzer stage 1250 is supplied from its decimator circuit 1 252 as an input to the subsequent spectral analyzer stage 1260. The bandpass spectrum L ₅ one octave below L ₄ is the highpass output of the spectrum analyzer stage 1260 due to its input signal G ₅ . The spectral analyzer stage 1 260 includes elements 1 261.1 262.1 263.1 264.1 265 and 1 266 corresponding to the elements 1251.1 252, 1 253.1254, 12525 and 1 256 of the spectral analyzer stage 1 250 except halved sampling rates. The decimated low-pass output signal Gn supplied by the decimation circuit of the last spectrum analyzer stage, here G _n G ₆ , supplied by the decimator circuit 1 262 of the spectral analyzer stage 1 260, is a residual spectral low-pass output signal. It serves as the basis for the resynthesis of the signals by summing interpolated spectral bandpass signals of the later spectral analyzer stages and the "capstone" high pass spectral output signal of the initial spectral analyzer stage L ₀ , L ₁ , L ₂ , L ₃ , L ₄ and L ₅ are time shifted and become The remaining low-pass spectrum G _n (here G ₆ ) follows in time the last band-pass spectrum L _n -I (here L ₅ ) with an opposite time shift.

As described herein, the methods of signal synthesis from spectral components also require that the spectral components L ₀ , L ₁ , L ₂ , L ₃ , L ₄ and L ₅ have this opposite time shift from each other. Before describing the performance of the spectral analysis and synthesis of the signals obtained therefrom, the structure of the spectral analyzer stages is explained in more detail. First, the initial two-dimensional low-pass filters are described.

As is known in the filter art, two-dimensional filters can not be separable nature or alternatively separable nature. Separable filtering in the first and second dimensions may be performed by first filtering in a first direction using a first one-dimensional filter and then filtering in a second direction perpendicular to the first direction by a second one-dimensional filter is used. Since the respective low-pass filter characteristics of two separate series-connected one-dimensional filters forming a separable two-dimensional low-pass filter are completely independent of each other, the core or trunk function and structure of each of these low-pass filters can be similar to those described in connection with FIGS. 2a and 2b and Figures 3 to 11 has been described. In the case of television images formed from the horizontal scan line grid, the two orthogonal directions of a separable filter are preferably the horizontal and vertical directions. Using separable two-dimensional low-pass filtering in the practice of the invention, certain advantages in performing horizontal low-pass filtering prior to vertical low-pass filtering can be achieved while providing other benefits when performing vertical low-pass filtering prior to horizontal low-pass filtering. For example, assuming horizontal filtering and decimation first, then the number of pixel samples per horizontal deflection line to be processed by the vertical kernel function during subsequent vertical filtering reduces by half. However, taking the vertical filtering first, one can use the same delay structure required to give the relatively long delay required for vertical fading and also by the respective compensation delays (1 215,12, 12, 12, 12, 12, 24). 1255 and 1265) for developing the respective signals Go to G ₅ to the positive terminal of each respective subtracting circuit 1216, 1226, 1236, 1246, 1256 and 1266 of the stages 1210, 1220, 1230, 1240, 1250 and 1260 of the one shown in FIG To give spectral analyzer.

The overall filter response (distribution of the input samples in a position matrix) of a separable two-dimensional spatial frequency filter can be square or rectangular in cross section parallel to the spatial frequency plane. However, filter addresses of non-separable filters may have different cross sections. Circular and elliptical cross-sections are of particular interest for the filtering of raster-scanned television signals, since filtering approaches with such cross-sections can be used to reduce excessive diagonal resolution in the television signals. The uniformity of image resolution in all directions is important, for example, in television systems where the image is rotated between the camera and the player.

Given below is a matrix of filter weights with a pattern having quadrant symmetry and linear phase behavior, filter characteristics particularly suitable for use as the 2-D low pass filters 1211, 1221, 1231, 1241, 1251, 251, and 1261, respectively 2-D low pass filters 1214, 1224, 1, 234, 1, 24, 1, 25, 1 and 264 of FIG. 12 are suitable. ABCBA

A kernel function matrix having this pattern of weighting factors, in turn, processes each of successive image samples, each image sample, when processed, corresponding in position to a centrally located weighting factor J of the matrix. In a low-pass filter, the weighting factor J has the relatively highest magnitude value, and each of the other weighting factors has a magnitude value which becomes progressively smaller the farther it is from the center position. Therefore, the weighting factors A in the corners have the lowest size value.

In the case of a non-separable two-dimensional filter, the specific values chosen for the level sizes of A, B, C, D, E, F, G, H and J are completely independent. However, in the case of a two-dimensional separable filter, the level sizes of the weighting factors are the cross product of the respective values of the horizontal and vertical one-dimensional core weighting factors, and the respective values A, B, D, D, E, F, G, H and J are not complete independently of each other.

An arrangement for synthesizing an electrical signal from component spectra, as generally shown in Fig. 13, is important to the invention. The spectral components G ₆ ', L ₅ ', L ₄ ', L ₃ ', L ₂ ', L ₁ ' and L ₀ 'are outputs of their non-primed counterparts supplied by the spectrum analyzer of FIG. The spectral components L ₀ , L ₁ , L ₂ , L ₃ r L ₄ / G ₆ and L ₅ are supplied later in time increasingly from the spectrum analyzer of FIG. 12 and must be differentially delayed to G ₀ ', L ₅ ', L ₄ ', L ₃ ', L ₂ ', L ₁ ', and L ₀ 'increasingly later for the signal synthesizing circuit of FIG.

Fig. 13 shows a signal synthesizing circuit having a plurality of consecutive signal synthesis stages 1360, 1365, 1370, 1375, 1330, 1385. When used for interpolation, each stage expands the sample matrix of a spectral component to have the same extent as the next highest spectral component in the spatial frequency, such that it increases

D e F e G H J H D e F e A B C B

this spectral component can be added. The expansion of the sample matrix is done by interleaving the sample points in the matrix with zeros and lowpassing the result to remove harmonic structures. The low-pass formation preferably has the same filter characteristic as the low-pass filtering in the corresponding interpolation process in the spectrum analyzer according to FIG. 12.

The low pass filtering in the interpolation in the signal synthesizing circuit suppresses harmonics of the nonlinear processing signals Gn or Lk which may occur in the varying circuits (as described in connection with Fig. 3) between the spectrum analyzer of Fig. 12 and the synthesizing circuit are inserted according to FIG. 13. Such non-linear processes cause visible aliasing errors in the synthesized composite video unless the low-pass filtering is performed by the interpolation processes performed in the signal synthesis. In the synthesizing circuit of Fig. 13, zeros are inserted between the samples of the low-pass spectrum G ₆ 'in the expansion circuit 1361, and then passed through the two-dimensional low-pass spatial frequency filter 1362, which is similar to the filter 1265 in the spectrum analyzer of Fig. 12. The samples of the output of filter 1362 are added in an adder 1363 to samples of L ₅ 'to a signal G ₅ ' which is similar or identical to the hypothetical time-delayed image of G ₅ . Then the samples G ₅ 'in the expansion circuit 1366 are nested with zeros. This signal is passed through the low-pass filter 1367, which is similar to the low-pass filter 1 254 of FIG. 12, and added to L4 'in an adder 1 368, producing G4' which is the same or identical to a delayed-lag image of G4. The samples of G4 'are zeroed in expansion circuit 1 371, and the result is low pass filtered in a filter 1 372, which is similar to filter 1 244 in FIG. The output of the filter 1372 is added to L ₃ 'in an adder 1373 and the resulting signal G3' is similar or identical to a delayed image of G3. The samples of G3 'are interleaved with zeros in expansion circuit 1376, and the result is low-pass filtered in a filter 1377, which is similar to filter 1234 in FIG. The output of filter 1377 is added to L ₂ 'in adder 1378 to produce G ₂ ', which is similar or identical to a delayed image of G ₂ . In an expansion circuit 1381, zeros are inserted between the samples G ₂ , and the result is low-pass filtered in a filter 1382. The output of the filter 1382 is added to L / in an adder 1383, giving Gi 'which is similar or equal to Gi with delay. The samples of G / are applied to interpolate an expansion circuit 1386 and a low pass filter 1387, which is similar to the filter 1214 of FIG. The output of filter 1387 is added in an adder 1388 with L ₀ 'to Go', the synthesized signal representing the same image, possibly with changes, which is described by G ₀ . While the two-dimensional implementation of the invention is particularly useful for image processing of the spatial frequency spectrum of images in real time, it should be understood that the two-dimensional information to which the invention relates is not limited to the spatial frequency spectrum of two-dimensional images. For example, one of the two dimensions of the spatial frequency information and the other of the two dimensions may correspond to a time frequency information.

Furthermore, the invention is suitable for analyzing the real time frequency spectrum of information defined by more than two dimensions. For example, in the case of three-dimensional information, all three dimensions may correspond to spatial information, or alternatively, two of the dimensions may correspond to spatial frequencies while the third dimension corresponds to time information. Of interest in this context is an image processing device that responds to the occurrence of motion in a reproduced television picture. In this case, the spatial frequency spectrum of the reproduced image corresponding to the stationary objects remains the same from video frame to frame of the video information, while the part of the spatial frequency spectrum of the reproduced picture corresponding to moving objects changes from frame to frame of the picture information. A spectrum analyzer according to the invention may also be used in such image processing equipment using 3-D low pass filters. Two of the three dimensions of these low-pass filters are spatial and correspond to two spatial dimensions of the two low-pass filters in each stage of the two-dimensional spectrum analyzer of Figure 12. The third dimension is temporal and corresponds to the fine structure characteristics of the three-dimensional spectrum due to changes caused by the movement of objects in the three-dimensional spectrum Values of the amplitude levels of the respective picture elements of the playback picture from frame to frame.

In the above description of embodiments of the invention, it has been assumed that the temporal signal Go is a baseband signal having a frequency spectrum which defines information of one or more dimensions. As is known, such baseband information is often transmitted in frequency division multiplex format, the baseband information being represented by the sidebands of a carrier frequency modulated with a baseband information component. By using suitable modulators and demodulators with respect to the transmitters 100-1 ... 100-N of Fig. 1, Go and / or any of the signals G ₁ ... Gn and / or any of the signals L ₀ ... Ln _i may be frequency division multiplexed ,

The term "shift register" is used in the claims for devices that perform the equivalent function, such as a memory to be serially stored and read out.

Claims (40)

(1) the single temporal signal is formed by a particular stream of information component samples defining the frequency spectrum of the information having a given number of dimensions with a particular sample density in each of these dimensions, Signal processing means for analyzing the frequency spectrum of an information component (Go) of a given temporal signal into (N + 1) separate frequency bands, said component corresponding to information having a given number of dimensions, and N is an integer greater than one and the highest one of interest Frequency in the frequency spectrum is not greater than a frequency f _o , characterized in that for analyzing the frequency spectrum in real time delayed real time, the device a pipeline structure (Figures 1,1 a, 1 b) with a set of N arranged according to the train transmission facilities (100 -1 ... 100 N) for the sampled signal, that each of the transmission means (Figure 1 a) has first and second input terminals and first and second output terminals, that the given time signal (G ₀ ) is supplied to the first input terminal of the first transmission device of the set, in that the first input terminal of each of the second to Nth transmission means of the set is coupled to the first output terminal of the immediately preceding transmission means of the set for forwarding a signal (G ₁ , G ₂ , etc.) from either one of the transmission means to the immediately subsequent transmission means of the set . a separate sampling frequency clock (CL 1, CL 2, etc.) is supplied to the second input terminal of each of the transmission means of the set for deriving at the first and second outputs of said transmission means signals sampled at a rate equal to the sampling frequency of the clock supplied thereto in that each of the transmission means of the information component set has a lowpass transfer function between its first input terminal and its first output terminal, and that the low pass function of that set of nominal set point transmission means is a direct function of the sampling frequency of the second input terminal The clock supplied to this transmission means of the set is that the clock supplied to the second input terminal of the first transmission means of the set has a sampling frequency which is (a) twice as large as f ₀ and (b) for the carry component gives a nominal cut-off frequency of the low-pass transfer function of the first transmission means of the set smaller than f ₀ , that the clock supplied to the second input terminal of each of the second to N-th transmission means of the set has a sampling frequency which is (a) less than (b) is at least twice the maximum frequency of the information component of the signal applied to the first input terminal and (c) gives a nominal cutoff frequency for its low pass transfer function smaller than that of its immediately preceding transmission means of the Sentence is, and in that the information component of the signal derived at the second output terminal of each of the transmission means of the set is the difference between the information component of the signal applied to its first input terminal and a direct function of the information component of the signal derived at its first output terminal, such that the N respective signals are applied to the signal second output terminals of the N-transmitting devices together with the signal at the first output terminal of the N-th transmission device (N + 1) occupy separate frequency bands. (2) forming the first (Lo) of the series of N distinct signals arranged in order by a stream of information component samples which define an upper portion of the frequency spectrum of the information at a sampling density substantially the same as the particular sample density in each of Dimensions is, 2. A device according to claim 1, characterized in that the clock supplied to the second input terminal of each of the second to Nth transmission means of the set has a sampling frequency relative to the sampling frequency of the clock fed to the second input terminal of the immediately preceding transmission means of the set The information component of the signal supplied to its first input is sampled at half the rate as that with which the corresponding dimension of the information component of the first terminal of the immediately preceding transmission means of the set is sampled. (3) each of the second through the (N-1) th of the N separate signals (L ₁ ... L ₅ ) of the sequence arranged in sequence is formed by a stream of information component samples representing an individual part of the frequency spectrum of the information in defines each of its dimensions which is below that of the corresponding dimension of the spectrum of that part, which is defined by the immediately preceding separation of the signals of the set and above the corresponding dimension of the spectrum of that part which defines from the immediately following separate signal of that set is 3. A device according to claim 2, characterized in that the clock supplied to the second input terminal of each of the second to Nth transmission means of the set has a sampling frequency relative to the sampling frequency of the clock fed to the second input terminal of the immediately preceding transmission means of the set to have a nominal Limit frequency of their low-pass function for each dimension of the information component of the signal supplied to its first input terminal, which is substantially half of the nominal cutoff frequency, which results for the corresponding dimension of this information component by the low-pass transfer function of the immediately preceding transmission means of the set, and in that the information component of the signal derived at the second output terminal of each of the transmission means of the set is in each of its dimensions of another octave of the frequency spectrum of the information component of the given temporal signal in this dimension. (4) the stream of information component samples corresponding to each of the second through (N-1) th of the N separate signals (L ₁ ... L ₅ ) of the ordered set has a sample density for each of its own information dimensions, less than the sample density of the corresponding information dimension of the stream of information component samples corresponding to its immediately preceding separate signal of that set, 4. Device according to claim 1, characterized in that the given temporal signal is an analog signal having an information component corresponding to a one-dimensional information. (5) the respective streams of the information component samples occur with a predetermined temporal shift relationship to one another, and in that said means (Fig. 3) comprise a set of (N-1) sampled signal combining circuits (363-353) each of which (e.g., 363, 362) are individually connected to one (e.g., L ₀ ) of the first to ( N-1) -th order sequence signals (L ₀ -L ₅ ) of the set of separate signals for combining that order-following signal (e.g., L ₀ ) of the set of separate signals associated with the combining circuit with the cumulative set (e.g., Gi) of all those separate signals (for example L ₁ , L ₂ ... GiI) which follow a separate signal of the sentence in line with the sequence, and in that each of the combination circuits (for example, 362, 361) associated with the first (L ₀ ) and the (N-2) th (L ₄ ) order-related signal of the set of separate signals comprises an adder circuit (eg 363), a first arrangement ( for example, 340) for forwarding its associated series-separated signal as the first input signal to the adder circuit, and a second device (eg, 362) for forwarding the output of the adder circuit (eg, 361) of the combiner circuit (eg, 361) associated with that separate signal (eg, Gi) which immediately follows its sequence-specific separate signal as a second input signal to its adder circuit with the same sample density, as it has their separate sequence according to the sequence, in that the combining circuit (353, 352) associated with the (N-1) th separate signal (L ₅ ) of the set comprises an adder circuit (353), the first arrangement (350) for feeding the (N-1) th separate one Signal as the first input to its adder, and a third arrangement (352) for supplying the Nth separate signal (GiI) as a second input to its adder (353) having the same sample density as the (N-1) th separate signal has, contains, and the respective first arrangement (340, 341, etc.), the second arrangement (362, 360, etc.), and the third arrangement of the (N-1) combining circuits of the group respectively insert predetermined amounts of time delay in forwarding the time-shifted separate signals of the set, such that for each of the respective (N-1) combination circuits, corresponding information samples of the respective streams of information component samples at the first input and the second input of their adder circuit coincide substantially in time so that the synthesized single time signal at the output of the adder circuit the first separate signal of the set associated with combination circuit occurs. 5. A device according to claim 1, characterized in that the given temporal signal is a video signal which defines a two-dimensional image information. 6. Device according to claim 5, characterized in that the video signal corresponds to successive frames of scanned television images. 7. Device according to claim 1, characterized in that each of the transmission means (10Oa-K, 10Ob-K in Figs. 1 a and 1 b) of the sentence comprises: a first array (102, 104) coupled to said first and second input ports and a first output port of said one transmission means for forming a low-pass transfer function of said transmission device, comprising an m-tap convolution filter (102), where m is a given integer greater than one for convolving the information component of the signal supplied to the first input terminal of this transmission device with a predetermined core function at a sampling frequency equal to that of the signal applied to the second input port of that transmission device, the kernel function and the sampling frequency of the convolution filter of these transmission devices being the shape or cutoff frequency of the Determine the low-pass transfer function of this transfer device in each dimension of the information component, and a second arrangement (109, 110), coupled to derive the difference signal at the second output terminal of said transmission means with the first arrangement and the second input terminal and the second output terminal of said transmission means, comprising a sample substray means (110) and a delay means (106, 108, 109, Figs 1 b and 1 c) in order to couple the sample subtractor to the first array via the delay means, the sampling subtractor being in time alignment with the sampling frequency of the convoluted samples of that transmitter each of the successive respective sample levels of the convolved samples of that transmitter of each the respective successively occurring respective level of the information component of the signal supplied at the first input terminal of the transmission device as prior to its convolution with the predetermined kernel function of the convolution filter of that transmission means, the output of the sample subtractor containing each of the consecutively occurring respective difference sample levels at the sampling frequency of the convolved samples of that transmitter and the respective difference sample levels forming the information component of the signal originating at the second output terminal of that transmitter. 8. A device according to claim 7, characterized in that the predetermined kernel function of at least one of the transmission means of the set defines a low pass transfer function for that transfer means with a gradual drop extending beyond the nominal filter cutoff frequency. 9. Device according to claim 7, characterized in that the respective core functions of at least two of the transmission means of the set are substantially equal to each other. 10. Device according to claim 7, characterized in that the information component has at least two dimensions and that the folding filter is at least one of the transmission means in at least the two dimensions non-separable filter. 11. A device according to claim 7, characterized in that the information component has at least two dimensions and that the folding filter is at least one of the transmission means is a separable in the two dimensions filter. A device according to claim 7, characterized in that the first arrangement (102, 104) is at least one of the transmission means of the set of a given type and this type comprises the convolution filter (102) and a decimator circuit (104) connected in series between the output the convolution filter and the first output terminal of this transmission means of the set is switched such that the convolution filter of the given type of the first arrangement gives at its output a special sample density in each dimension of the information component which is the sampling frequency of the clock supplied to the second clock input of this transmission means, and in that the decimator of the given type of the first array in each dimension of the information component passes only certain but not all convolved samples appearing at the output of the convolution filter of the given type of the first array to the first output port of that transmitter, and the decimated sample density passes folded samples in each of the dimensions of the information component at the first output terminal of this transmission device is reduced with respect to the specific sample density of the corresponding dimension of the information component at the output of the convolution filter of that transmission device. A device according to claim 12, characterized in that the decimating circuit of the given type of the first arrangement in each of the dimensions of the information component forwards every other one of the samples occurring at the output of the convolution filter of the given type to the first output terminal of that transmission means; decimated sample density in each of the dimensions of the information component is reduced to one half the specific sample density of the corresponding dimension of the information component. 14. A device according to claim 12, characterized in that within at least one of the transmission means (206 bK, Fig. 1 b), the third arrangement includes a fourth array connected between the output of the convolution filter and the sample substray means for convolving the folded information component from the convolution filter directly to the sample subtractor (110). 15. A device according to claim 12, characterized in that the third arrangement (106,108,109 Fig. 1 a) further includes a fourth arrangement (106,108) which is connected between the decimator and the Abtastubtubtiereinrichtung for expanding the decimated sample density at the first output terminal of this transmission device in each dimension of this information component, back to the particular sample density of the folded samples in that dimension occurring at the sample subtractor, the fourth array comprises a sample expanding circuit (106) for inserting additional samples included in its Occurring each folded sample at the output of the convolution filter which is absent in the decimated sample density, each of the inserted additional samples having a zero value level, and further including interpolation means (108) providing an interpolation value sample level for the zero value level of each of the inserted additional samples starts. A device according to claim 14, characterized in that the decimating circuit of the given type of the first arrangement in each of the dimensions of the information component forwards every other sample appearing at the output of the convolution filter of the given type of the first arrangement to the first output terminal of that transmission means and in that the expansion circuit inserts an additional sample between each pair of successive folded samples of the decimated sample density in each dimension of the information component, and in that the interpolation circuit comprises an η-tapped interpolation filter (where η is an integer greater than one) and having a low-pass transfer function. 17. A device according to claim 14 or 15, characterized in that the information component of the signal at the first input terminal of this transmission means of their Abtastunterubtrahiereinrichtung is supplied via its delay means and that the delay means of this transmission means gives a time delay which is substantially equal to the total delay time, by the convolution filter, the decimator and the fourth arrangement of this transmission device are conditional. 18. A device according to claim 12, characterized in that each of the first to (N-1) th transmission means of the set comprises a first arrangement of the given type (10Oa-K or 100b-K). 19. Device according to claim 18, characterized in that the Nth transmission device (Figure 1 c) of the set also contains a first arrangement of the given type. Apparatus according to claim 18, characterized in that the Nth transmission means (Figure 1c) of the set includes a first arrangement of an alternative type in which the output of the convolution filter is fed directly to the first output port of the Nth transmission means. 21. A device according to claim 20, characterized in that the information component of the signal (Gn-i) at the first input of the Nth transmission circuit of the switch of their Abtastunterubtrahierschaltung via their delay means (109) is supplied and that the delay means of the Nth transmission means of Sets a time delay that is substantially equal to the delay caused by its convolution filter. 22 device (Fig. 1) for performing a real-time spectral analysis, characterized by a cascade connection of low-pass sampling filters (102, 104 in FIG. 1a, 1b within 100-1, 100-2, etc.), which are operated at increasingly lower sampling rates (CL1, CL2, etc.), wherein an input signal (G ₀ ) of this cascade is the spectral analyzing signal and the output signal (G _n ) of the cascade represents a residual low pass spectrum, an arrangement (106, 108 in Fig. 1a) for interleaving the samples of a decimated form of the output signal of each of the lowpass sampling filters (102, 104) with zeros and for low pass filtering the result a corresponding interpolation result, means (109) for delaying the samples of the input signal of each low-pass filter in this cascade by an amount equal to the sum of the delays in the output of that filter and the low-pass filtering of the zero-interleaved output, and subtraction means (110) the delayed samples of the input signal of each low-pass filter in the cascade circuit with the interpolation result derived therefrom to form one signal (L _K .i) of the spectral analysis of the input signal of the cascade circuit. 23 device (Fig. 1) for performing a real-time spectral analysis of an electrical signal (G ₀ ), which is sampled at a rate R regularly, characterized by a plurality of η analyzer stages (100-1,100-2, etc.) sequentially numbered with base numbers from 0 to η, each of which (Figure 4) has a first output signal (G (K ₊ d) due to the lower frequency components of its input signal (Gk) and a separate second output signal (Lk) due to the higher-frequency components of its input signal (G _K ), wherein the analyzer stage (100-1) numbered 0 is supplied with the electrical signal for spectral analysis as an input signal, and each of the other analyzer stages is supplied as an input signal with the first output signal of the analyzer stage with the next lower basic number, that the second output signals of all stages and the first output signal of the analyzer stage numbered with η form the result of the spectral analysis, wherein each of the plurality of analyzer stages (eg, Fig. 4) includes a first m-stage shift register (470) (where m is an integer greater than one) whose input is supplied to the analyzer stage input signal (Gk) at a clock rate is clocked by R / 2 ^k (where k is the base number of the analyzer stage), means (471) for weighting the input signal (Gk) of the analyzer stage and the input signal delayed in each stage of the first m-stage register with a set of coefficients and summing the weighted signals to produce a linear phase low pass filtered output signal (Gk +1), which represents the first output signal of the analyzer stage, based on its input signal, a multiplexing circuit (472) operable to select, alternately at the rate R / 2 ^(k), the first output of the analyzer stage and a zero value, another m-stage shift register (473), whose input is supplied with the signal selected by the multiplexer and which is clocked at the clock rate R / 2 ^(k ~ ¹⁾ , means (474) for weighting the selected signal of this analyzer stage and the signal delayed in each stage of the further m-stage register with a set of weighting coefficients and summing the weighted signals to form a resampled first output of that analyzer stage and means ( 475) for subtractively combining the resampled first output signal of this analyzer stage with its delayed input signal to produce the second output signal (L _K ) of that analyzer stage. 24. Device according to claim 23, characterized in that m is the same for each analyzer stage and that each analyzer stage uses weight factor sets of the same values. 25. Device according to claim 23, characterized in that the delayed input signal of each analyzer stage is derived from the m-th stage of its first m-stage shift register and additionally delayed (by element 476). 26. Digital filter (Fig. 1) for supplying at least one output signal, characterized by a plurality of tapped clocked delay lines (eg, 470 in Figure 4 in each of the devices 100-1, 100-2, etc.) which are numbered sequentially and increasing numbering sequence at progressively lower rates (R / 1, R / 2 etc.) are clocked, a device for supplying an input signal (G ₀ ) to be filtered to the input of the first of these delay lines, Means (eg, 471 in each of the circuits 100-1, 100-2, etc.) for respectively weighting the samples at the taps of each delay line and for combining the weighted samples to form respective filter output signals (Gi, G ₂ ) and means for supplying the respective filter output signals derived from the samples taken from each delay line except those having the highest order number as input to the delay line having the next higher order number, wherein at least a part (G _n ) of the respective one Filter output signal derived from the sampled values taken from the highest order number delay line used to generate the overall output signal. 27. A digital filter according to claim 26, characterized in that the weighted samples from the taps of each delay line to form corresponding filter output signals (G ₁ , G _2, etc.) are combined with low-pass character. A digital filter according to claim 27, characterized in that the filter output (G _n ) obtained by weighting and combining the samples taken from the delay line with the highest order number is used as the output of the digital filter. The digital filter of claim 27, characterized by another tapped clocked delay line (473) clocked at the same rate as the selected (470) of the plurality of tapped delay lines, by means (472) for selectively supplying the output signal of the selected delay line and of zeros to the input of the further delay line, means (474) for weighting samples from the taps of the further delay line and for combining the samples to form a low pass filter output; and means (475) for difference combining the low pass filter output thus obtained with the output of the plurality of selected delay lines to produce an output signal (474); Lk) of the digital filter. A digital filter (Fig. 5) according to claim 27, characterized in that the weighted samples selected from the taps of one of the plurality of tapped delay lines (570-0,570-1) are delay line (570-1) having the sequence number (1) which is 1 higher than the sequence number (0) of the previous delay line, (a) is differently weighted every other one of the clock cycles of the previous delay line, and (b) combined into a low pass filter output signal on each of these clock cycles and that the thus obtained low-pass filter output signal is combined with the output of the preceding delay line (570-0) in differential form (in 575-0) to form an output signal (Lo) of the digital filter. A digital filter according to claim 26, characterized by another clocked clocked delay line (473) which is clocked at the same rate as the delay line (470) selected from the plurality of tapped delay lines. means (472) for selectively supplying the output signal of the selected delay line and of zeros to the input of the further delay line, means (474) for weighting samples from the taps of the further delay line and combining the samples into an output signal and means (475) for combining the thus obtained output values with the delayed input signal (Gk) of the preceding delay line to form an output signal (Lk) of the digital filter. 32. Digital filter according to claim 31, characterized in that the delayed input signal of the preceding delay line is obtained by inserting the delay (476) at one of its taps. A digital filter according to claim 32, characterized in that the weighted samples differ from the taps of one of the plurality of tapped delay lines selected delay line having a sequence number of 1 higher than a preceding delay line, every other one of the clock cycles of the preceding delay line are weighted and combined every other clock cycle, and that this combination result is combined with the delayed input signal of the previous delay line to form an output signal of the digital filter. 34. Digital filter according to claim 33, characterized in that the delayed input signal of the preceding delay line is obtained by inserting the delay at one of its taps. 35. Signal processing means (Figure 3) for synthesizing a single time signal (Go) from a successively arranged set of N separate time signals (Lo-Gfl), where N is an integer> 1, characterized in that for synthesizing the single time signal on a delayed real-time basis 36. Device (Figure 6) according to Claim 35, characterized in that the second arrangement (for example 362 in Figure 3) of the respective combination circuit, which is individually assigned to each of the first to (N-2) th series-sequential signals (for example L ( KD) of the set of discrete signals, a sample expander circuit (692,693,694) which inserts additional samples into the passed current due to the low sample density stream of the information component samples (Gk) which are passed to the output of the adder circuit Input of the adder circuit (695) of this combinational circuit to the sample density of the orderly separate signal (L ( _K- d) associated with that combination circuit, each of the added additional samples having a zero level, and including interpolation means (693, 694) an interpolation value sample level l is substituted for the zero level of each of the inserted additional samples. A device (Fig. 6) according to claim 36, characterized in that the N th separate signal (GO) of the set has a lower sample density than the (N-1) th separate signal (L ₅ ) of the set and the third arrangement (352) includes a sample expander and an interpolator (692,693,694) equal to those of the second arrangement for passing the Nth separate signal to the second input of the adder of the third arrangement. 38. Apparatus according to claim 37, characterized in that the N th separate signal (GiI) of the set has substantially the same sample density as the (N-1) th separate signal (L ₅ ) of the set and that the third arrangement the Nth separate signal is forwarded directly to the second input of the adder circuit of the third arrangement. 39. A device according to claim 36, characterized in that the stream of information component samples corresponding to each of at least the second (L ₁ ) to (N-1) th (L ₅ ) of the sequence of N separate signals arranged in order of a sample density for has each of its own information dimensions, which is half the sample density of the corresponding information dimension of the stream of information component samples corresponding to its immediately preceding set point sianal. and in each of the combinational circuits (Figure 6), the second array expander (692) adds an additional sample between each pair of consecutive samples of the lower sample density in each dimension of the stream of information component samples into the output (G _K ,) of the adder circuit to be forwarded and that the expander is formed by an interpolation filter (693) with n taps (n is an integer> 1) with a low-pass transfer function. 40) Apparatus according to claim 35, characterized in that the third arrangement and each of the respective second arrangements of the group of N-1 sampled signal combining circuits assign their own predetermined amount of time delay in forwarding their stream of information component samples as a second input signal their adder circuit inserts, and that each of the first arrangements of the group of N-1 sampled signal combining circuits includes a delay means (340, 341, etc.) which inserts a particular amount of time delay in forwarding its sequential separate signal as its first input to its adder circuit, which depends both ( 1) from the respective time shift between its sequence-specific separate signal and each of those separate signals of the set following its sequential separate signal, and (2) the total amount of time delay imposed by the third arrangement and all the second arrangements of that combination circuit, associated with the separate signals of the set following their sequential separate signal and that the particular amount of delay is such that corresponding information samples of the respective streams of information components Samples occur at the first input and the second input of their adder circuit in substantially coincident coincidence with each other.