DD239481A1 - DEVICE FOR PROTOCOLING PROGRAM TASKS - Google Patents

Abstract

The invention relates to a device for logging program sequences, a tracer, for real-time testing of software and is advantageously preferably applicable in the test mode of microcomputers in extensive and interrupt interruptible program systems, when the flow of particularly long or highly branched programs are tested in context should. The goal is to store only the information that is absolutely necessary, to reduce test times, and the technical task is to block all redundant information for tracking the program flow, otherwise the same storage capacity of a logging device. This is achieved by passing the information into the logging device's own memory field before the information to be logged passes through the information, which only allows a memory operation in a memory field when conditions have occurred that interrupt the consecutive command execution. figure

Description

For this 1 page drawing

Field of application of the invention

The invention is used for testing software for digital computers under real-time conditions, especially in complicated and extensive interrupt interruptible program systems, preferably in microcomputers and advantageous if the flow of particularly long or highly branched pieces of program should be tracked and tested in connection and if In the reliability test of software for the largest possible number of input variables and their combinations as quickly as possible an overview of extensive program sequences must be obtained.

Characteristic of the known technical solutions

Solutions are known that perform logging with software support in which certain utilities take over storing the necessary protocol information at defined times. These solutions violate the real-time conditions. Also known are solutions that force the storage of the protocol information by appropriate circuits that do without software support and therefore do not violate the real-time conditions. The storage is done, as is known, with each bus cycle or periodically at constant time intervals (Microcomputer Development System MRES20 of the VEV Kombinat Robotron and DD-WP 155215). This results in the following disadvantages:

- Each bus cycle is saved at least once or during scheduled recording several times, regardless of whether the information contained therein is necessary or superfluous for the program tracking.

- The evaluation of the stored information during logging is relatively expensive, since the relevant information must first be selected from the entire recording mass.

- For longer recordings memory with very large capacities is required.

Known logging facilities draw z. B. a fixed number of signals in fixed time, associated with these disadvantages mentioned.

Another logging device operates with a record clock, which is obtained by special combination of signals to be always scanned, which is selected so that when used on the microcomputer at the end of each bus cycle, a signal is generated. Such real-time memories (REAL) have the advantage over logic analysis that the amount of information is recorded in a pre-compressed manner. Other known program trackers are based on comparisons between a set sequence with an actual sequence of addresses of the current computer. However, these solutions proposed in DE-OS 2002166 and OS 3242502 do not serve to improve the record of the work order of the computer. An information compression is shown in DD-WP 210776, in which all addresses of the command loop cycles in the address protocol and block commands, as multiply identical operations with different data, are stored in real-time only once. The interruption is not exactly detectable in this way.

Object of the invention

The aim of the invention is to simplify the testing of software. For this purpose, only the absolutely necessary information must be stored for the program trace, that is to say the number of information must be substantially reduced and the storage of useless information avoided.

The essence of the invention

The technical problem which is solved by the invention

It is to provide a means for logging program flows, which treats the information stream before storage by a suitable filter so that all information redundant for the tracking of the program flow is blocked.

Features of the invention

In detail, the logging device according to the invention consists of a memory array, a filter for the passage of the information with signal for a memory operation, when the konsekutive program flow was left, a buffer for the function of a filter, a cyclic address counter and a start-stop device for Protocol I beg.

The protocol device according to the invention functions as follows. For the memory field of sufficient width, the memory width being determined by the number of signals to be recorded representing the instruction flow, preferably instruction addresses and ancillary information, the preselected depth is determined by the number of consecutive program sequence interrupts to be recorded. A filter has the task of evaluating the flow of information from the computer and then output a signal when the Konsekutive program flow is left, or when selected signals change their logical value, the signal triggers an information storage in the memory field.

For microcomputers with a bus structure of known type in which the bus is composed of address bus, data bus and control bus and the filter represents a logic circuit, the signals of the control bus are linked so that an output signal is generated when a command loop cycle is executed. In this case, a comparison is activated, which compares the command data, which occupy the data bus at this time, with predetermined data patterns. Upon coincidence, a validity signal is output, such that the predetermined data patterns correspond to the command data or command codes that trigger a jump command in the computer or interrupt the consecutive command processing. This validity signal transmits the assignment of the address bus in the memory field. Optionally, the address bus occupancy is cached for safe transfer to the memory array and further a supplementary logic circuit part is inserted into the filter which combines the control bus signals and then triggers the validity signal if external conditions such as maskable and / or unmaskable interrupt interrupt the consecutive instruction execution and do not perform this interruption the described analysis of the instruction stream can be determined by comparison.

It is advantageous for the reduction of information redundancy in the protocol if the filter suppresses the store operation as long as a command that acts as a jump on itself is executed.

In computers whose signals are accessible only by multiplexing, the construction of the filter can be made possible in an inexpensive way.

The buffer added to the filter then has the task of keeping the information to be evaluated by the logger constant for the function of the filter until the output signal of the filter is valid and the possibly successful storage of the relevant information in the memory field is completed when the consecutive program sequence is interrupted is.

It is also advantageous if the buffer also stores selected information over the duration of the processing of a plurality of instructions, if this information contains the reference to a leaving of the consecutive command processing occurring at a later time. This information would then be deleted only after actually leaving the consecutive command sequence. As a result, all information is transferred from the buffer in the memory field, which are valid for all commands, which are processed in the period from caching the hint information and clearing the hint information by the actual interruption of the consecutive program flow.

The additional information stored in parallel with the relevant jump address, in suitably coded form, determines the cause for leaving the consecutive program sequence. This makes the evaluation of the protocol easier or only possible. A start-stop device, which serves the defined switching on and off of the protocol process, wherein the signals for starting / stopping are preferably generated by a suitable hardware or by software, limited so that the protocol process can be limited to program sections of interest.

It is advantageous to determine the start and end times of logging both by external control signals and by tag commands.

A peculiarity is when the buffer picks up certain signals and the filter can refer to them as the signals change their logical value and thus their logging of the currently running command is enforced. This not only triggers the protocol at the time when the consecutive program sequence is interrupted, but it can thus be logged even if external signals change their significance, which can be recorded in the minutes and the time at which external signals only after a certain reaction time trigger the abandonment of the consecutive program sequence, so about interrupt applications.

embodiment

The invention will be explained below using an exemplary embodiment. In the figure, the logging device according to the invention is shown. It is designed for an 8-bit microcomputer. For this purpose, the memory array 1 was constructed for a recording width of 16 bits, the width of an address bus and additionally an 8-bit width for additional information with a memory depth of 2 K bytes. The operation of the filter 2 in conjunction with the latch 5 was chosen so that two memory locations are described in the memory array 1 per interruption of the consecutive program flow. The memory location η is occupied by the address at which the consecutive program sequence was interrupted and the memory location η + 1 contains the following address after the interruption.

Next there is a logic that organizes a standard bus connection to the memory array 1, with the help of which, after completion of the logging process, the content of the memory array 1 can be read out by the microcomputer and suitably evaluated. The address counter 6 is realized by a standard circuit. The count is 11 bits. The start-stop device 7 acts in the example performed on the filter 2 in the manner proposed above. For this purpose, an externally supplied signal is evaluated, equal to the presence of the operation code of two selected commands. These selected commands do not change the state of the CPU.

According to the possibilities of interrupting the consecutive operation of the microcomputer used, the selection of additional information was set to 8 bits. In this case, 3 bits in coded form indicate the occurrence of jump instructions, subroutine calls and restarts. The remaining bits are used to identify the following independently and partially concurrent program interrupt conditions:

- Maskable interrupt

- Request a non-maskable interrupt

- Execution of a non-maskable interrupt

- Start-stop of the logging process by an initial signal or software conditions.

The filter 2 was executed as follows: A command decoder analyzes the signal play of the microcomputer bus and sufficiently and appropriately executes the instruction flow of the CPU. Among other things, it recognizes the beginning of a new command execution cycle. At this time, the instruction ADRs are cached. If, further, the instruction decoder recognizes selected instructions that are relevant to the leap in the course of a program, then in the sense of the function of the filter 2, the transfer of the instruction ADR from the buffer 5 is caused in the memory array 1 and also automatically take over the command -ADR of the next instruction following in the instruction execution: Logging of the jump and jump target ADR.

Due to the function, the address counter 6 is advanced by 2 positions during this process. The additional information written into the memory field 1 synchronously with the storage of the addresses is likewise supplied by the command decoder. Interrupts and the influence of the start-stop device 7 can not be completely recognized by the command decoder and are therefore evaluated in terms of the function of the filter 2 by an additional logic and causes the acquisition of the corresponding command addresses in the memory array 1 in the same manner as above was described in the recognition of relevant to the jump events commands.

In order to increase the effectiveness of the filter when used on the microcomputer, additional jumps are also detected by additional circuits on themselves and holding states and for the address transfer into the memory field 1 suppressed, although it is also a deviation from the consecutive program sequence. This is useful to further reduce information redundancy in the protocol.

Since the CPU of the microcomputer used does not output a signal game upon acceptance of an NMI which is clearly different from a normal instruction processing, each pulse is latched on the NMI line and from that time a log mode is activated in which each instruction is recorded. The start of the NMI routine is signaled by an address comparator, thereby clearing the NMI cache, which returns to normal log mode.

Claims (8)

claims: 1. A device for logging program sequences for real-time testing of software, characterized in that before the acquisition of the information to be logged in the logger own memory array (1) the information passes through a filter (2), which only allows a storage operation when conditions occurred are that interrupt the consecutive instruction processing, which is signaled by a validity signal (4), wherein the memory field (1) and filter (2) a latch (5) and a start-stop device (7) is switched on. 2. Device according to claim 1, characterized in that for microcomputer with bus structure of known type, in which the bus is composed of address bus, data bus and control bus and the filter is a logic circuit, the signals of the control bus are linked so that an output signal is generated when a command loop cycle is executed and this output signal activates a comparator which compares the command data occupying the data bus at that time with predetermined data patterns and, if necessary, the command data into a buffer upstream of the comparator for safe operation of the comparator be buffered and the comparator then outputs a validity signal (4) when command data and predetermined data pattern match, such that the predetermined data pattern corresponding to the command data or command codes that trigger a jump command in the computer or the consecutive command processing u Interrupt and this validity signal (4) transmits the assignment of the address bus in the memory array (4) and possibly the address bus assignment for safe transfer into the memory field (1) is latched and further a supplemental logic circuit part is inserted into the filter (2) which links the control bus signals and then triggers the valid signal (4) if external conditions such as maskable and / or unmaskable interrupt interrupt the consecutive command execution and do not interrupt can be determined by the described analysis of the instruction stream by means of comparators. 3. Device according to claim 1 and 2, characterized in that the filter (2) suppresses the storage process as long as a command is executed, which acts as a jump on itself. 4. Device according to claim 1 to 3, in which the filter (2) a buffer (5) is added, characterized in that all information necessary for the operation are cached and this information to the filter (2) are available until its output signal (4) is valid and until the possible storage of the relevant information in the memory array (1) is completed upon interruption of the consecutive program sequence. 5. Device according to claim 1 and 4, characterized in that the buffer (5) cached selected information over the duration of the processing of a plurality of commands, if this information includes the reference to a entering at a later time leaving the consecutive command processing and this information only after the actual leaving the consecutive command sequence are deleted and thereby all information from the buffer (5) in the memory field (1) are accepted, which are valid for all commands, which in the period of time from caching the hint information and deleting the hint information by the actual interruption of the consecutive program sequence are processed. 6. Device according to claim 1 and 2, characterized in that additional information is stored in parallel with the relevant jump address, which record the cause of the · leaving the consecutive program sequence in a suitably encoded form. 7. Device according to claim 1 and 2, characterized in that the times for the beginning and end of the logging can be determined both by external control signals and by marking commands. 8. Device according to claim 1 and 4, characterized in that the buffer (5) receives certain signals and the filter (2) by reference to these cached signals forms a protocol request, if these signals change their logical value and thus the logging of this time is being enforced.