DD235751A1 - METHOD FOR MANUFACTURING VOLATILE INDEPENDENT CAPACITORS IN INTEGRATED MOS CIRCUITS - Google Patents

Abstract

The invention relates to a method for producing voltage-independent capacitors, which is particularly suitable for MIS technologies. The aim of the invention is to improve the structuring of the contact holes of the transistors in the manufacture of voltage-independent capacitors. This will be solved by minimizing the contact holes. The essence of the invention is that a two-step process for contact hole placement is used. Fig. 3

Description

For this 1 page drawings

field of use

The invention relates to a method for producing integrated, voltage-independent capacitors and is suitable for semiconductor technologies for manufacturing integrated circuits, in particular for the silicon gate technology.

Characteristic of the known technical solution

For some applications, integrable, largely voltage-independent capacitors are required. A known method for producing voltage-independent capacitors is set forth in patent WO81 / 00171, H01 L21 / 283. It is proposed here that openings are etched in a phosphorus-containing oxide layer (phosphosilicate glass) located on highly doped polysilicon up to the underlying polysilicon in which an oxide is subsequently produced by tempering and aluminum is deposited thereon. This process has the disadvantage that, to form the oxide, an additional high temperature process becomes necessary, e.g. increases the depth of the drain and source of the MOS transistors. This limits the reduction of the MOS transistors and thus the increase in the integration density. The method according to WP 213554, H 01 L29 / 78 eliminates this disadvantage by the use of a protective layer for the capacitor dielectric. A disadvantage of both methods, however, is that after the etching of the contact holes in the phosphosilicate glass (PSG) into thermal S1O2 must still be removed from the contact holes. As a result, the PSG contact holes widen, which also precludes an increase in the integration density.

Object of the invention

The object of the invention is to improve the patterning of the contact holes of the MIS transistors in the manufacture of integrated voltage-independent capacitors.

Explanation of the essence of the invention

The object of the invention is to provide a method for producing voltage-independent capacitors in integrated MOS circuits, in which the contact holes are produced with little undercut.

The following known method steps are used: By means of selective oxidation, field oxide is generated in places on a semiconductor substrate of a first conductivity type.

Then, a gate oxide is formed by thermal oxidation on the field oxide-free areas. Polysilicon gates are now applied to the gate oxide and polysilicon areas are applied to the field oxide. This is followed by a short oxidation step. This is followed by a high-dose implantation of ions of a second conductivity type, whereby the field oxide-free silicon is highly doped. Now it comes to the deposition of a special insulating layer, which is much more resistant to etching compared to the gate oxide.

The inventive solution of the object of the invention is now in the following:

The etching of contact holes of the MOS transistors into the special insulating layer and into the gate oxide takes place by means of a resist mask.

- After removing the paint, a glass layer, z. B. Phosphorsilikatglas deposited.

By means of another resist mask, the glass layer is removed in the contact holes, on the polysilicon areas and on the non-gate-covered, field oxide-free areas.

It is expedient that in the etching by means of the further resist mask after removal of the glass layer and the special insulating layer is removed.

Finally, it is expedient to use silicon nitride as a special insulating layer, since it is substantially more etch-resistant than SiO 2 in wet-chemical etching.

The solution according to the invention has the advantage that the gate oxide is first etched in the contact holes. Therefore, removal of the phosphosilicate glass, which is less etch resistant than gate oxide, can be achieved with optimum etch time, i. h., With minimal undercut under the resist mask, executed.

In further manufacturing steps, capacitors can now be produced on the highly doped silicon covered by gate oxide by applying a cover electrode.

embodiment

The invention will be explained below using an exemplary embodiment. The accompanying drawing shows in Figure 1 to Figure 3 the schematically illustrated process flow for the simultaneous production of MIS transistors and voltage-independent capacitors.

According to figure 1, on a semiconductor substrate 1 (z. B. p-type silicon with a doping concentration of 5 x 10 cm ^{l4 "3)} the field oxide 2 (0.5 ... 1 \ μπ thick) produced by selective oxidation and the Gate oxide 3, the polysilicon gate 4 and the polysilicon region 5 are formed, followed by a brief oxidizing annealing (eg 1000 ° C., 30 min), whereby an approximately 50 nm-thick oxide layer 9 is formed on the polysilicon region 5. Ion implantation ( eg with dose 10 ¹⁶ cm ~ ² dose, energy 150 keV) polysilicon gate 4, polysilicon region 5, source 6 and drain 7, and silicon region 8 are made η-conductive ₃ N ₄ (20 nm thick), the contact holes 11 are then etched via a resist mask (not shown) For this purpose, there are etchers (for example a mixture of phosphoric acid and borofluoric acid) containing the special insulating layer 10 a attack Si ₃ N _{4 in the} same way as the gate oxide 3.

According to FIG. 2, a glass layer 12 (eg, phosphorosilicate glass) is now deposited. Then, the contact holes 11, the polysilicon region 5 and the n-silicon region 8 of phosphorus silicate glass 12 and the special insulating layer 10 of Si ₃ N _{4 are} etched free with a further, not shown resist mask. This is done in two steps. First, phosphorosilicate glass is etched (eg with a mixture of HF and NH ₄ F) and then the Si ₃ N ₄ so that the underlying oxide layer 9 or the semiconductor substrate 1 and the remaining phosphosilicate glass 12 are not attacked (eg with 160 ⁰ C hot phosphoric acid). If necessary, according to claim 1, the method without an etching of the special insulating layer 10 can be performed.

According to FIG. 3, an aluminum or polysilicon conductor layer 13 is now deposited and patterned. During the formation of the MIS transistors (polysilicon gate 4, source 6, drain 7), voltage-independent capacitors are thus simultaneously formed over the polysilicon region 5 and the n-silicon region 8.

Claims (3)

-1- 745 Invention claim: 1. A method for producing voltage-dependent capacitors in integrated MOS circuits such that field oxide is produced by means of selective oxidation on a semiconductor substrate of a first conductivity type, on the feldoxidfreien areas a gate oxide is formed by thermal oxidation, are applied to the gate oxide polysilicon gates and on the field oxide Polysiliciumbereiche , an oxidation is carried out and then a high-dose implantation of ions of a second conductivity type and a special insulating layer, which is much more etch-resistant compared to the gate oxide, is deposited, characterized in that Contact holes {11) of the MOS transistors are etched into the special insulating layer (10) and into the gate oxide (3) by means of a resist mask. A glass layer (12) is deposited, - By means of a further resist mask, the glass layer (12) from the contact holes (11), from the Polysiliciumbereichen (5) and is removed from the not covered with Polysiliciumgates field oxide-free areas. 2. The method according to item!, Characterized in that by means of the further resist mask after removing the glass layer (12) and the special insulating layer (10) on the Polysiliciumbereichen (5) and on the not covered with Polysiliciumgates field oxide-free areas is removed. 3. The method according to item 1 and 2, characterized in that as a special insulating layer (10) silicon nitride (Si ₃ N ₄ ) is used.