DD235148A1 - ARRANGEMENT FOR CONTROLLING A DIODE MATRIX WITH LUMINESCENCE DIODES - Google Patents

Abstract

The arrangement for controlling a diode matrix and its monitoring is used in process automation and monitoring systems. The aim of the invention is the flexible, secure status display of measured values. The object of the invention is the development of a simple autarkic drive arrangement for a diode matrix, which is connected via address, data and control lines to a microprocessor. According to the invention, the address and control lines are connected to a counter which is connected to a clock generator. On a memory circuit, both the address signal from the output of Zaehlers, as well as control and data signals from the bus out, whose output signal via a logic circuit and a monitoring circuit is connected to a drive matrix. To realize the different displays two flashing frequencies are led to the logic circuit. Fig. 1

Description

Field of application of the invention

The invention relates to an arrangement for controlling a diode matrix with light-emitting diodes for displaying measured values and is used in process automation and monitoring systems as part of the communication system "plant-human"

Characteristic of the known technical solutions

In DE 16 23872 a device for displaying measured values with optional excitable light-emitting cells is described in which the light cells are grouped into successive groups, each group has a common exciter circuit, which is activated by a group switch has, and all groups connected to common individual switch A measuring signal is converted by a voltage-frequency converter into a proportional frequency and given to a payer, at the outputs of a decoder for controlling the group and individual switch is connected. Furthermore, the payer can be followed by a measured value memory, the in the payer The measured value is then still fixed, even if a new value is already shown in the payer. The device is provided to generate light bands, the length of the light band being proportional to a measured value. The disadvantage is that the advantageous use of the group and Einzelschaiter by the task of creating a quasi-analog display device, only offers the possibility to control the light cells with 0 or 1 and also offers no possibility to individually control each light cell A self-monitoring of the device is not possible display errors remain unrecognized in DE 2118222 is a Electro-optical display device described, the two parallel columns of display segments, which are arranged offset in the longitudinal direction, used The control is carried out via a matrix in which the display segments are used as light emitting diodes The matrix is controlled by a logic circuit as input signals are two decimal data groups The device is intended to represent the height of measured values by means of a geometric figure - ζ B of a triangle - on the display columns. The drawback is that the display columns are used exclusively for the representation of the height of an M In DE 2940745 a luminescence display device for displaying analog values is described via AD converter and decoder takes the control of the display in addition to the quantitative representation of the value is also a qualitative possible by varying the luminous intensity and color The analog signal is also switched for this purpose on triggers whose output signals depending on the level of the analog signal and the specified trigger thresholds a voltage generator and payer act, in turn, the decoder for the individual color anodes of the light emitting diode driver voltages in the form specify in amplitude high and duty cycle variable pulse trains

A disadvantage nerbei is the relatively high cost of displaying a measured value, so that a meaningful use only for the representation of? In addition, the solution requires the use of multicolored luminescence

Object of the invention

The aim of the invention is to improve the flexible, secure status display of measured values. Explanation of the essence of the invention

The object of the invention is an arrangement for driving a diode matrix with light-emitting diodes for status display of measured values

Use find circuits of microelectronics

The arrangement is connected via address data and control lines to a microprocessor without constantly burdening it. According to the invention, the address and control signals from the computer-controlled bus are connected to the parallel inputs of a counter which is connected to a first frequency output of a clock generator A memory circuit on whose address input the parallel outputs of the payer and from the bus, the data signals are guided.

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On a logic circuit, the data outputs of the memory circuit and a second and third frequency output of the clock generator are connected to the outputs then the luminous cell signals are available. These and the line signals from the output of a decoder are fed via a monitoring circuit to the drive matrix. The parallel outputs of the counter circuit are connected to the inputs of the decoder.

The logic circuit is constructed of logical switching elements, wherein in each case three are arranged for the formation of a luminous cell signal. The control matrix is constructed by means of line amplifiers and each status display from the series connection of a resistor and a diode or the series connection of a memory, the diode and the resistor. The monitoring circuit includes a flip-flop, on whose inputs the first and last line signal are routed. With the last line signal, the flip-flop is set and reset with the first line signal, so that at the output a pulse train is formed. The output of the flip-flop is connected via a capacitor to a filter, wherein the input of the filter is connected via a resistor and a diode to the supply voltage. The time constant of the RC element must be greater than the time between two pulses of the pulse train. The filter time must be dimensioned so that a single pulse does not take effect. At the output of the filter is a first error signal, which is simultaneously connected to gates, abut at the second input of each one of the luminous cell signals. The outputs of the gates are routed to the control matrix in order to cause a dark control of all the light cells or the connection of Lo ... Ln / 2 in the event of a fault. To form a further error signal, a comparator is arranged, at the first input of which the luminous cell signals and at its second input, evaluated by a comparator, the luminous field current applied. The operation of the arrangement will be explained with reference to the embodiment.

embodiment

Show it:

Fig. 1: Block diagram of a display device according to the invention

2 shows a logic circuit for forming luminous cell signals and a driving matrix with luminous cells

3 shows another drive matrix with a high number of light cells

4 shows a block diagram of a monitoring circuit for the display device

Fig.5: Timing diagram for the logic circuit.

The address signals Ao ... Am are switched to the parallel inputs of a counter 1 with the control signal S applied from the computer-controlled bus. A memory circuit 3 (2 ^m * ¹ times n) lies with its address inputs to the parallel outputs AO ... A'm of the counter 1 and is occupied at its data inputs with the data signals Do ... Dn from the bus. The control signal S is also fed to the memory circuit 3. Further outputs of the clock generator 2 are connected to a logic circuit 4, to which also the data outputs DO ... D'n of the memory circuit 3 are applied and at the outputs of which luminous cell signals Lo .. Ln / 2 pending. These are routed to the control matrix 6 via a monitoring circuit 14. The address signals AO... A'rrv from the counter 1 are furthermore connected to the drive matrix 6 and the monitoring circuit 14 via a decoder 5. For the described arrangement of the modules of the block diagram of FIG. 1, the operation of the device for displaying the status of measured values with luminous cells will be explained. For each measured value, the status is to be displayed with a light cell, whereby each light cell can emit the following optical signals: Light cell dark corresponds to the status "measured value is within the tolerance." Light cell fast flashing: "measured value is out of tolerance"

 Light cell flashing slowly: "Measured value was temporarily out of tolerance." Bright light cell: "Measured value is out of tolerance, error has been detected and acknowledged".

In the exemplary embodiment, the status has been assigned these meanings; for another application, the assignment could also be different in principle. In memory 3, the status is stored for every measured value in 2 cells each. With the data D _o ·. · D _n and an address AO... A'm, the data for a luminous cell row consisting of n / 2 luminous cells is written in the memory circuit. The number of rows of luminous cells results from the memory depth corresponding to the address AO... A'm with 2 ^{m + 1} . In a memory of the format 2 ^{m + 1} times η, the status can accordingly be stored for 2 ^{m + 1} * n / 2 measured values and displayed with light cells. In the exemplary embodiment, the data D ₀ ... D _n for controlling a row of luminous cells have been occupied as follows.

1.LZ D ₁ 2.LZ D ₃ n / 2 LZ D _n Light cells dark D ₀ O D ₂ O D _n -I O Light cells flashing fast O O O O O O Light cells slowly blinking 1 1 1 1 1 1 Bright cells bright O 1 O 1 O 1 1. Light cell dark 2. Light cell fast flashing n / 2. Light cell bright 1 O 1 O 1 1 O 1 1

LZ = illuminated cell

To "write memory" with control signal S when changing a measured value is rubbed the data signals D ₀ ... D _n the corresponding line of an address signal Ao ... Am switched to the parallel inputs of the counter 1. This takes over the address signal "memory write" Ao ... Am, so that at its parallel outputs and thus to the

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Address inputs of the memory circuit 3, the address AO ... A'm (identical Ao ... Am) is pending. After every "memory write" activity, the clock generator 2 supplies the counter with the clock frequency f 1, so that all the address signals A'o... A'm are counted through cyclically, corresponding to the current address signal A'o The data signals D'o ··· D ' _n for controlling a row of luminous cells are respectively applied to the memory circuit 3. The luminous cell signals L ₀ are used in conjunction with the frequency f 2 for rapid flashing and the frequency f3 for slow flashing in the logic circuit 4. .. L _n / 2 is formed. About the decoder 5, the address signal A'O ... A'm in 1 OFF2 ^{m + 1} and decodes the signals Z ₀ ... Zg a light emitting cell row is in each case activated. by the cyclical Run each row of light cells and thus each light cell after the time

T = -. 2 ^{m + 1}

newly addressed.

By means of FIG. 2, the logic circuit 4 and the control matrix 6.1 are to be described with the luminous cells 61. To form the luminous cell signal L ₀ , the stored data signals D ' _o , 0 \ are given to logical switching elements 41, 42 and 43 for a row of luminous cells. With DO at each one input of the switching elements 41 and 42 and D ', each having an input of the switching elements 43 and 42 and the frequency f 2 at the second input from the switching element 41 and frequency f 3 at the second input from the switching element 43 is achieved that the Light cell signal L ₀ at the data signals L ₀ , D ₁ equals 0.0 to "1" (corresponds to inactive signal) In the case of D ' _o , D i i equal to 1.1 L ₀ switches to "0" (corresponds to active signal) , With D ' _o , D i i equal to 1.0, the luminous cell signal is activated in each case in the positive half-wave of the fast flashing frequency f 2. Accordingly, at D ' _o , D', equal to 0.1, the switching through of the slow flashing frequency f 3. In Fig. 5, the two cases are shown again in the timing diagram. In the same way, the formation of the luminous cell signals Lidurch through D ' ₂ , D' ₃ to L _{n / 2} by DV ₁ , D ' _n . With the line signals Z ₀ ... Z _q , a line amplifier 60 is switched on via the control matrix 6 with luminous cells 61. Active luminous cell signals control the light-emitting diodes lying at the crossing point from Z and Lo to L _{n / 2} . Due to the cyclical run, each light cell will become smaller

the time χ ζ = - ^{2 m +} for the duration of t = - driven in accordance with the memory circuit 3 stored status. Around

To ensure a well-visible afterglow of the memory cell until the next cycle, the clock frequency f 1 should be as high as possible and the dimensioned by the resistors 62 for the luminous cells stream the max. permissible pulse current correspond.

By means of FIG. 3, a further embodiment variant of a control matrix 6.2 with a high number of luminous cells 61 is to be described. This variant is preferably used where, due to the large number of luminous cells, the cyclic passage becomes so long that a clearly visible afterglow of the luminous cells is no longer possible.

An active line signal Z ₀ ... Z _q causes the luminous cell signals Lo- · L _{n / 2 to be written} into a memory 63 per luminous cell. With each cyclic run, the memories 63 are updated according to the status stored in the memory circuit 3.

The frequency f 1 must ensure here only the switching of the fast flashing frequency, i.

f,> f ₂ -2 ^{m + 1} .

The activation of the luminous cells 61 is thus static and the dimensioning of the luminous cell current is determined by the permissible continuous current. Destruction of the light _cells in case of failure of the clock frequency ί _Ί , as in the control _matrix 6.1, control with maximum pulse current, 6.2 can not occur in this embodiment. As memory static memory and clock edge controlled memory can be applied.

In Fig. 4, the monitoring circuit 14 is shown for signaling of display errors and thus to avoid false indications in clock defect, breakage of an address line and failure of a light cell or its control.

A memory circuit 7 is set with the line signal Z _q and reset with the signal Z ₀ , so that the memory output a pulse train with a duty ratio 1: (q + 1) appears. This, given by a capacitor 8 to the input of a filter 12, at the input of a resistor 9 and a diode 10 are connected to the supply voltage, causes an error signal F1 is delivered in case of failure of the pulse train. Prerequisite for this are the following conditions.

The time constant of the RC element 8.9 must be greater than the time between two line signal pulses Z _q , that is, between two pulse generator formed at the flip-flop pulse train. The filter time of the filter 12 must be above the duration of the pulse Z _q . A single impulse must not take effect. The error signal F1 is simultaneously used by the gate 11.0... 11... / 2 with the luminous cell signals L ₀ ... L _{n / 2} for dimming control of all the luminous cells.

To check the individual luminous cells, the luminous field current I of the control matrix 6 is applied via a current comparator 13 to a first input of a comparator 15 and the luminous cell signals L ₀ and O ₀ combined via decoupling diodes.

Ln / 2 are switched to its second input. The comparator 15 emits an error message if no luminous field is present at the time of application of a signal L ₀ ... L _{n / 2} . A defective light field or its activation can thus be identified by the assignment of address and data no occurrence of the error signal.

The arrangement for status display of measured values with light cells allows in the simplest way and with economical use of components, the optional output of four optical signals, such as dark, fast flashing, slow flashing and bright per light cell. The arbitrary change of the optical signals for a group of light cells is effected by a program-controlled microprocessor or a central unit.

A further advantage is the autonomous operation of the arrangement, as long as there is no change in a measured value. With the simple monitoring circuit of the control matrix with light cells false readings can be avoided. It allows the detection of a clock defect, the break of an address line and the failure of a light cell. The self-diagnosis of the assembly allows its use in microprocessor-controlled devices.

Claims (2)

1 arrangement for driving a diode matrix with light-emitting diodes for status display of measured values, which is connected via the address data and control bus to a microprocessor, using microelectronic circuits, characterized in that the address signals (Ao Am) and control signals (S) to a payer (1), which is connected to a first frequency output (f 1) of a clock generator (2), and the control signals (S) and data signals (D ₀ D _n ) to a memory circuit (3) and the parallel output of the payer ( 1) for an address (A'o A'm) are also connected to the memory (3) and a decoder (5), that the data outputs (D ' _o D' _n ) of the memory circuit (3) to a logic circuit (4 ), the input side further connected to a second and third frequency output (f 2, f 3) of the clock generator (2) that the cell signals (Zo Z _q ) at the output of the decoder (5) and the cell signals (Lo L _{n / 2} ) at the exit of the L ogikschaltung (4) via a monitoring circuit (14) on the drive matrix (6) are guided -1- 738 Invention claim: 2 arrangement for driving a diode matrix according to item 1, characterized in that (the first and last) cell signals (Z ₀ , Z _q ) of decoder (5) are guided to a flip-flop (7), the output side via a capacitor ( 8) is connected to a filter (12) whose input is connected via the parallel circuit of resistor (9) and diode (10) to the supply voltage, that the output of the filter (12) for a first error signal (F 1) on the Entrance of gates (11) is guided, at whose second input in each case a luminous cell signal (L ₀ L _{n / 2} ) is applied and its outputs for dark control on the Ansteuermatnx (6) drove, and that the cell signals (L ₀ L _n / ₂ ) and the luminous field current of the drive matrix (6) via a comparator (13) to a comparator (15) are guided For this 5 pages drawings