DD220439B1 - PROCEDURE FOR QUICK BLOCK DATA TRANSMISSION BETWEEN THE STORES OF TWO COMPUTERS - Google Patents

Description

For this 3 pages drawings

Field of application of the invention

The invention relates to a method for fast blockwise data transmission between the memories of computers whose internal data buses are located on bus units on a common data bus, the Initiativrechner performs read or write commands to the memory of the target computer. ^: .

Characteristic of the known state of the art

The coupling of computers generally has the exchange of data to the content. This data exchange may be desired so that memory or I / O units of another computer are shared directly, but the general and interesting for a work sharing operation case is that the result data and command instructions are exchanged, so that a relatively autonomous operation of each computer is possible.

This results in the desire to transport data from the memory of a computer as directly as possible to the memory of another computer.

This problem is solved in a known multi-computer system (DT-OS 2713304) by the address and data rails of the individual computers are connected to each other via tri-state two-drive driver blocks and circuit measures are provided, which allow the write and read control signals to both the own as also to the memory of the computer to lead, with the data to be exchanged. Each computer has its own memory area in the read-write memory of every other computer, into which it can write or read the data to be transmitted by means of direct memory access.

This arrangement offers the possibility of free addressability of the exchange memory in the target computer due to the direct memory access. This property is paid for by a relatively high amount of tristate two-way driver components and bus lines, since the electrical transmission of address information of 10... 16 bit width is required. In addition to the high cost, this variety of interconnections and driver blocks has the disadvantage of lower reliability or greater susceptibility to interference and a more complicated troubleshooting.

Another known circuit arrangement (DD-PS 137627) proposes a similar computer connection arrangement, which uses a coupling bus, consisting of address, data, control and request bus. In addition, a special communication computer is proposed, which should organize the initiation of the data exchange with little time and the order of the computer. Basically, here are the same, already noted in the previously described multi-computer system disadvantages.

In another multi-computer coupling (DD-PS 142135) is proposed to connect each arithmetic unit via an input / output gate to common buses for data and address information, each I / O gate via a special control circuit for transmitting the control signals to a bus to asynchronous, direct and conflict-free data exchange is connected. The data exchange itself takes place with I / O operations in the handover procedure by means of acknowledgment operation.

This process noticeably reduces the data exchange rate since several operations of both computers involved are required for the transmission of a data byte. Furthermore, it must be considered a disadvantage that a special address bus must be routed to each arithmetic unit in order to enable a selection of the partner.

In another known Mikrororechnerkopplung (DD-PS 133482) is sought to realize a peripheral-like Mikrororechnerkopplung with parallel interface modules so that at low cost nevertheless a high data exchange rate, flexibility and universality is achieved. For this purpose, in addition to the programmable parallel I / O interface modules, a double additional waiting logic generating on both sides of the data exchange waiting signals is provided. This solution still has the disadvantage that the action of the wait signals on both sides has reduced the maximum possible data exchange rate result.

Another known device (DT-OS 3026362) suggests a fully synchronous and block-oriented data exchange to create a low-cost but faster microcomputer link with I / O devices. By a command / control device, the data exchange on both sides at the beginning should be initiated once and then run synchronously. With uniform clock supply of the exchanging computers, the data block to be transmitted can be of any length. With different clock supply, the maximum block length depending on the relative clock accuracy may only be so large that transmission errors are excluded with certainty.

This property is a major disadvantage. In addition, the necessary synchronous operation of both computers for different reasons is not always given. Furthermore, it is disadvantageous that the data transfer method works with input / output errors on both sides, wherein for the transmission of a byte on the transmitter side even a memory read operation and then an output operation to the transfer port is required. This has a low data exchange rate compared to the direct memory access result.

Object of the invention.

The aim of the invention is to achieve a block-wise data exchange between two computers with a high data exchange rate with a low circuit wall. There should be no restriction on the block length and there are no time problems arising when accessing the memory cells of a block located further back.

Explanation of the essence of the invention

The invention has for its object to provide a method for fast block-by-block data transfer between the memories of computers whose internal data buses are connected to a common data bus via bus units, the block data exchange only with separate Taktakt the computer without their cyclic synchronization Output commands of the Initiativrechners and with less hardware overhead, in particular to enable bus lines and Tristaie Zweiwaftreiberbausteinen.

According to the invention the object is achieved in that the target computer is offset by the Initiativrechner via control signals in an address mode in which the processor of the target computer on its address bus in incrementing operation outputs an address that is used as a pointer for the respective memory cell of a data block and is held at this address by a wait control signal until the data transmission for this memory cell is completed. The Initiativrechnert at the end of its transmission cycle, the wait control signal so long that the processor of the target computer leaves its waiting state and generates the next address and outputs.

Preferably, in the initiator computer, a first address part for the memory of the destination computer is output as a block entry address for selecting the beginning of the data block and buffered in the destination computer and combined with a second address part issued by the destination computer. An advantageous embodiment of the method is that the address mode is generated by a command generator whose output gives a NOP command to the data input of the processor, wherein the access of the processor is interrupted to its program memory.

A further embodiment of the method is that for the data transmission between more than two computers, a computer work as Initiativrechner and the remaining computers as a target computer, the data being transferred via the memory of the Initiativrechners.

Another favorable possibility for the data transmission between more than two computers provides for a computer to operate as a target computer and the remaining computers to work as an initiator computer, the data being transferred via the memory of the target computer.

embodiment

In the drawings, an embodiment of the invention is shown. Showing:

1 shows a block diagram with the basic structure of the data transmission; FIG. 2 shows a circuit arrangement for the data exchange; FIG. 3 shows a circuit variant for the address formation

In Fig. 1, the basic data transfer method is first illustrated by the effect context. An initiating computer 1 and a target computer 2 are connected to each other via a bus unit 3 and a data bus DAT.

A connection control circuit 5 supports the initiation, execution and termination of the data exchange. The initiator computer 1 should be the data exchange wishing and the target computer 2 the desired partner. The Initiativrechner 1 therefore takes over the active function.

The initiation of the data exchange implies that the central processing unit ZRE2 of the target computer 2 is put into a NOP mode by being cut off from its program memory by a control of its control signal inputs (INT, RESET ₇ WAIT) and by a NOP commander 6 Continuous NOP command gets imposed. This has the consequence that the central processing unit ZRE 2 outputs on its address bus an incrementing address A beginning with "zero", which is used as a pointer for the memory cell ZEL to be exchanged.

At each address, the central processing unit ZRE 2 of the target computer 2 is held by a WAIT control until the data exchange for the relevant memory cell ZEL is completed.

Simultaneously with the address A, the central processing unit ZRE2 transmits the required memory control signals in the NOP mode, so that the memory Sp2 of the target computer 2 transmits the content of the memory cell currently being addressed.

The initiative computer 1 and in particular its central processing unit ZRE1 thus has the possibility of receiving the data output by the memory Sp 2 directly via the bus separation unit 3, which is preferably to take place with a read operation L1. Subsequently, the central processing unit ZRE1 store this data in its memory Sp 1, in FIG. 1 by a write operation S1. Thus, the transport of a date ypm memory Sp 2 of the target computer 2 in the memory SpI of

Initiativrechners 1 completed. Conversely, the arrangement also has the possibility to perform the Datenentranspnrt also in the opposite direction, which is illustrated with the read operation L2 and the write operation S 2. The write control of the memory Sp2 in the target computer 2 takes place with a read / write control signal R / W of the initiating computer 1 via the connection control circuit 5.

The incremental addressing manner of the memory SP2 by the central processing unit ZRE 2 advantageously favors a block-oriented command executed block-oriented by the instruction structure, which most microprocessors have and which offers a quick and convenient data transfer. From the point of view of the central processing unit ZREI, the memory Sp2 of the foreign target computer 2 is treated like its own, the memory SP2 apparently allowing an even faster access since the address access time in the target computer 2 is eliminated, as described in more detail below. To further increase the exchange rate, the central processing unit ZRE1 can also commission its own non-illustrated DMA unit, which is available as a purchased part, with the block transfer.

The access problem to in the exchange block further behind data is inventively solved by block division, each block can be reached directly via a separate block entry address BEA. The block entry address BEA is output by the initiative calculator 1 via the data bus DAT at the initiation of the data exchanger in a Adreßspeicher7. This address memory 7 adds its contents to the most significant part of the address effective in the target computer 2, thereby causing a shift of the start address. In Fig. 1, two examples of the block entry address BEA1 and BEAn are shown, which in each case points to the beginning of the sub-block and the low-order address part of the central processing unit ZRE2 of the target computer 2 is provided and the current memory cell ZEL of the sub-block addressed.

The circuit arrangement (FIG. 2) shows how the specified data exchange method can be implemented, based on the widespread processor Z80. Other processor types have similar signals and can be used analogously.

The main part of the inventive circuit arrangement is located on the side of the target computer 2.

The central processing unit ZRE2 is connected in known manner via data driver circuits 21, 22 and address driver circuits 23a, 23b to their memory and I / O units, wherein only the read / write memory Sp2 of interest for the data exchange is shown in FIG , The bus separation unit 3 is a parallel bidirectional tristate driver circuit, e.g. from two integrated circuits 8216, which connects the internal data bus 20 of the target computer 2 via the data bus DAT with the Initiativrechner 1.

The address memory 7 is used to transfer, storage and connection of the block entry pointer for data exchange.

About a state logic 19, consisting of an activation flip-flop 26 and a status flip-flop 27, the desired data exchange partner (target computer 2) is requested at more than two arithmetic units. All other functional elements are used for sequential control of the data exchange.

In this case, no address bus from Initiativrechner 1 is passed to the target computer 2, but the coupling is made via the common data bus DAT, which must have the data width of the system. Moreover, for flexibly selecting the time for the data exchange depending on the state of problem processing, there are provided a destination call line ZRA, a call line RUF and a request line FRA, and for data exchange control a cycle control signal line ZYK and a read / write control line R / W.

In the following, the interaction of the switching elements based on the sequence of a data exchange connection will be shown. In the initial state, both the initiator computer 1 and the target computer 2 are to process their programs independently of each other. This state should be marked on the side of the intended target computer 2 by an L signal at the output of the activation flip-flop 26. Via a status flip-flop 27, the bus unit 3 and the address memory 7 are then high-impedance and the data and address driver circuits 21,22,23 active, so that an undisturbed operation of the central processing unit ZRE2 at its memory Sp2 and their I / O units is possible.

In the case of a specific program processing state, the initiative computer 1 creates the desire to transfer data with another computer, eg a computer. B. exchange the target computer 2. At this time, there should be no requirements for a data exchange from other computers. For this purpose, the initiative calculator 1 requests the target computer 2 for data exchange via a special output operation.

The output includes that via a first part 24a of the data bus DAT the address of the target computer 2 to the detection circuit 25 and a second part 24b, the block entry address BEA is output to the address memory 7. For an 8-bit data bus DAT, e.g. 4 bits for the address of the target computer 2 and also 4 bits for the block entry address BEA be assigned. Thus, 15 target computer addresses - all 4 bits LOW should have reset function - and 16 block entry addresses are encoded, which already allows the construction of extensive multi-computer systems.

The Zielrechneraufrufleitung ZRA represents the output of a Ausgabentschlüsslers on the Initiativrechner 1 and is performed in parallel to each target computer 2 and there on the one hand for writing the block entry address BEA in the address memory 7, if a release to its input E1 by activating the detection circuit 25 in the case of the correct destination address. On the other hand causes the Zielrechneraufrufsignal ZRA at the clock input T of the activation flip-flop 26, the storage of the output of the detection circuit 25 on its own se output. At the appropriate destination computer address appears at the output of the detection circuit 25, and after being transferred to the activation flip-flop 26 at the output of the activation flip-flop 26, a Η signal that remains there even after completion of the output. The target computer call signal line ZRA continues via an inverter 28 and a gate 29 to the interrupt input INT of the central processing unit ZRE2 of the target computer 2. In the subsequent interrupt handling routine, the central processing unit ZRE 2 can decide whether it is ready for data exchange and possibly preparations for make the data exchange. In the case of readiness, the central processing unit ZRE 2 enters a programmed "STOP" state which activates state logic 19 via its corresponding HALT output and negator 30, and one of NAND gates 31, 32, 33 , Winding connections 34 and drawing resistors 35 existing password generator 50 and the data bus DAT notifies the Initiativrechner 1. The Initiativrechner 1 asks this periodically by means of the inquiry line FRA, which is controlled via an input decoder on the Initiativrechner 1, the data bus DAT, if the password for the This password can be realized, for example, by a simple word coding with the NAND gates 32, 33 and the selectable winding connections 34 in conjunction with the drawing resistors 35.

If the desired password does not appear up to a maximum allowable time, the initiating computer 1 assumes that no data exchange is desired, and clears its request by issuing the fictitious LOW address to the detection circuit 25, resulting in the deactivation of the activation flip-flop 26. In this case, the target computer 2 would continue its own program processing and the initiator computer 1 could possibly seek data exchange with other computers or edit an autonomous program. At a later date, the data exchange request could be repeated.

If the password has appeared, then the target computer for data exchange is ready, in the target computer 2, the following expiration is effective.

The activated HALT output from the central processing unit ZRE 2 leads via the negator 30 and a UN D-gate 36 and a monoflop 37 to a reset pulse at the reset input RESET of the central processing unit ZRE 2. This causes the central processing unit ZRE 2 to be in its home position and, in particular, the instruction address counter Zero reset. At the same time, the switch-on edge of the "STOP" signal via negator 30 in state logic 19 effects the transfer of the output of activation flip-flop 26 into status flip-flop 27 by activating its clock input T. The inverted output of status flip-flop 27 For this purpose, a first switching operation is triggered on the data driver circuits 21, 22 by the data driver circuit 22 being switched off via its enable input E (high-resistance state) and the data driver circuit 21 being reset via its reset input R for reading to be LOW at the outputs connected to the data inputs of the central processing unit ZRE 2, which corresponds to the instruction code for the NOP instruction, which is indicated at the central processing unit of the processor Z80 that no data processing takes place, but an Au refreshing process and the command address counter is increased by "one".

Another switching operation with respect to the switching of the target computer 2 in the data exchange state leads to the shutdown of the gates 23 b and thus a portion 38 b of the address bus 38, so that only the time required for addressing the Datenblockanfangesjm memory Sp2 part of the address to a digital addition circuit 39 arrives. Furthermore, the output of the status flip-flop 27 activates the address memory 7 via a negation element 42, and the WAIT logic element 46, so that the wait input WAIT of the central processing unit ZRE 2 is called by an L signal. In addition, the password flip-flop 27 is activated by the status flip-flop 27 via the NAND gate 31. The following procedure results for the central processing unit ZRE2:

The reset pulse of the monoflip 37 brings the central processing unit ZRE 2 into its basic position, whereby the HALT output is switched off. The central processing unit ZRE 2 now starts its first cycle at the instruction address "zero" and receives the NOP instruction code imposed by the data driver circuit 21 embodied as an instruction generator unit, but the activation of the wait input WAIT results in the central processing unit ZRE 2 reading The initiator computer 1 can then immediately start the data exchange, which is carried out in the form of normal read or write operations, after successfully requesting the password via the password.

The data exchange should e.g. have the goal of first loading a number of data words from the memory Sp2 of the target computer 2 into the memory Sp 1 of the initiative calculator 1. According to the principle explained at the outset, the initiating computer 1 carries out read commands to the foreign memory Sp2 and write commands to its own memory Sp 1. To increase the data exchange security, the first data word may contain a passkey for rechecking the correct target computer. ·

Further following data words may contain information about the status, the character or the quantity of the following data words. For the actual data is an organization that takes into account that frequently needed or exchanging data are closer to the beginning of the block, in particular z. B. Status and control words.

The connection control circuit 5, the target computer side consisting of the switching elements 40 ... 45, realizes the following functions: Each read but also write cycle to the target computer 2, which can be executed only with a single address and thus requires virtually no address space, leads to the activation of the cycle control signal The cycle control signal activates the bus disconnection unit 3 via the AND gate 43, enables the read / write logic via the NAND gate 44 and the AND gate 45, and controls a WAIT logic element 46 on. The read / write control signal supplied simultaneously via the read / write control line R / W applies the read or write state to the write / read input of the memory Sp 2 via the NAND gate 44 and the AND gate 45 and to the direction control input Dl of the bus separation unit 3 Data switching direction fixed, d. H. in the case of the read cycle, the data switching direction from the target computer F 2 to the initiator computer 1,. .

The WAIT logic element 46 has the task at each activation by the cycle control signal in the course of a read or write cycle to the target computer 2, the wait control signal at the WAIT WAIT input of the central processing unit ZRE2 briefly

for the central processing unit ZRE2 to increase its instruction address counter by "one" by transition from the current to the next NOP instruction, thereby preparing the addressing of the next data to be exchanged, in case the target computer 2 operates at a higher system frequency than the initiator computer 1 or also for step operation by means of "WAIT" in Initiativrechner 1, a monostable timer 47 is inserted in the cycle signal line ZYK before the WAIT logic element 46 to ensure that until the next cycle of Befehlsadreßzähier is increased only by "one".

The proposed Adreßbildung.für the exchanged memory cell ZEL in the target computer 2 is made by combining two components by means of the digital addition circuit 39. This receives via an address bus 48 from the address memory 7, the block entry address BEA, which identifies the first memory cell ZEL of the data block to be exchanged, and on the Address bus 38 is supplied to the incremented address part starting from "zero" from the central processing unit ZRE2, which takes over the consecutive addressing. The address composed by the addition circuit 39 passes to the memory Sp2 via an address bus 49.

A simple embodiment with little circuit complexity is shown in FIG. 3, which, however, already allows 16 individual data blocks of 256 data words on the example of a 16-bit address bus. In the data exchange state, the higher part of the address bus 38 b of the central processing unit ZRE 2 is switched off by means of the gates 23 b and is partially acted upon by the address memory 7. The remaining address busbars 48, which are permanently assigned via pulling resistors 51, offer additional flexibility for the position of the memory cell ZEL to be addressed in the memory Sp2. The data exchange takes place in the form presented due to the incrementing addressing advantageous block-oriented, d. H. In the case of an exchange, it is always possible to transmit a plurality of adressively contiguous data words at the same time. This favors the use of the block transfer commands implemented in the customary processors or the use of special powerful DMA blocks in the initiator computer 1. In this case, the full speed of the processor or the DMA unit can be used because the target computer 2, because it always has only one NOP Command has already incremented its address before the next cycle occurs on it.

As a result, the memory Sp2 of the target computer 2 seems to have a lower access time than actually from the perspective of the initiating computer 1, since only the release time of the bus separation unit 3 takes effect and not the address access time.

Of course, the exchange of single bits is possible. Furthermore, read and write cycles can be performed to the target computer 2 in any order.

After exchanging the desired data, the connection between the initiating computer 1 and the target computer 2 is canceled by the initiating computer 1 outputting the fictitious target computer address "zero" via the data bus DATanden target computer 2. The activation flip-flop 26 and thus also the Status flip-flop 27 is cleared and a reset pulse is triggered at the inverted input of monoflip 37. As a result, the central processing unit ZRE 2 is switched to normal operation, whereby the reset pulse can be used to execute a start routine now be further processed there.

However, a start address, which was stored by the Initiativrechner 1 during the data exchange in the target computer 2, are taken into account.

In the following, further possibilities for the construction of multi-computer systems with the proposed data exchange method will be explained. With more than two computers, it is advantageous to provide a single initiator computer and to connect the others as a target computer.

The computers can have different structure in memory, peripherals and other components to solve their assigned task. To address data exchange, each individual computer is assigned its own destination address, which is recognized by the destination address decoder.

The Initiativrechner has a different structure, which has mainly the purpose to be able to act on the control lines. The data driver circuit buffers the data bus towards the coupling bus. The input / output decoder forms the signals on the target computer call line and the request line from certain I / O addresses.

Analogously, the memory decoder forms the cycle signal for the memory access in the target computer. A driver circuit switches the read / write signal of the central processing unit of the Initiativrechners to the target computers and the interruption logic forms from the call signal of the target computer an interrupt signal for the central processing unit of the Initiativrechners.

All control lines are routed in parallel to all computers, as is the data bus. Internally, the Initiativrechner has an exchange memory area, which is constructed as a read / write memory and is preferably used for data exchange throughout the system.

Other possible structures are:

- "Master-slave" system: The Initiativrechner works as a "master" computer with all "slave" computers (target computers) together.For this purpose, the Initiativrechner the entire data exchange according to programmable Zeltregime or / with request to the partner as described above to organize.

Another possibility uses the "RUF" line, wherein the "slave" computer desiring the data exchange enters a programmable "STOP" state and by activating its "STOP" output and further via the "RUF" circuit and the interrupt logic tells the "master" computer its data exchange request. This allows greater flexibility over time.

- Coupling computer system with buffering:

The Initiativrechner works as a specialized data exchange computer, which handles mainly the exchange of data between the individual function computers, with a dynamic programmable priority algorithm can apply. The individual target computers are independently functioning computers. The data exchange takes place with intermediate storage in a read / write memory area of the coupling computer.

- Coupling computer system without caching:

The Initiativrechner transports the data directly from one to the other computer. For this purpose, the two computers in question are to be controlled in the data exchange state, wherein the one either a read and the other a write signal must be supplied.

Claims (5)

claims: 1. A method for fast blockwise data transmission between the memories of computers whose data buses are connected to a common data bus via bus units, wherein the Initiativrechner performs read or write commands to the memory of the target computer, characterized in that the target computer (2) from the Initiativrechner ( 1) is put into an address mode via control signals, in which the processor (ZRE 2) of the target computer (2) outputs on its address bus (38) in an incrementing manner an address (A) which acts as a pointer for the respective memory cell (ZEL ) of a data block is used and held at this address (A) by a wait control signal until the data transmission for this memory cell (ZEL) is completed, the Initiativrechner (1) at the end of its transmission cycle blanking the wait control signal, that the processor (ZRE 2) of the target computer (2) leaves its waiting state and generates the next address (A) and spend. 2. The method according to claim 1, characterized in that that of the initiativrechner (1) a first address part for the memory (Sp 2) of the target computer (2) as Blockeinsprungadresse (BEA) for selecting the data block beginning Ausgab.wird and in the target computer (2) is cached and assembled with a second output from the target computer (2) address part. 3. The method according to claim 1 and 2, characterized in that the address mode is generated by an instruction generator unit (6) whose output is a NOP instruction on the data input of the processor (ZRE2), wherein the access of the processor (ZRE2) its program memory is interrupted. 4. The method according to claim 1 to 3, characterized in that for the data transmission between more than two computers, a computer as Initiativrechner (1) and the other computers as a target computer (2) work, the data on the memory (Sp 1) of the Initiativrechners (1) are transmitted. 5. The method according to claim 1 to 3, characterized in that for data transmission between more than two computers, a computer as a target computer (2) and the remaining computers as Initiativrechner (1) work, the data on the memory (Sp 2) of the Target computer (2) are transmitted.