DD216340A1 - CIRCUIT ARRANGEMENT FOR SIMULATING A LOGICAL SYSTEM - Google Patents

Abstract

The invention relates to the simulation of complicated logic systems, preferably with master-slice circuits for the purpose of circuit inspection and commissioning. The invention solves the problem, in particular to replace the wiring of a logical system to make using the so-called circuit simulators the complete system of a simulation on the basis of the principles of operation zugaengig. The solution is essentially that the output levels of the circuits are calculated in simulators, then sampled and stored and subsequently assigned as sources to the consumers. The circuit contains an address memory, which is called simultaneously to the circuit contacts and whose cells contain addresses of an information and a DOT memory, in which the contact information is entered and from which they are retrieved.

Description

Title of the invention

Circuit arrangement for simulating a logical system

Field of application of the invention

The invention relates to the simulation of the logic connections of circuits, preferably master-slice circuits, in a complex logic system for the simulation and logical commissioning of such systems.

Characteristic of the Known Technical Solutions The simulation of logic circuits on large conventional computer systems requires, in addition to a high computational time expenditure, the creation of special simulation examples related to the basic logic elements. The specificity of such examples requires detailed knowledge of the logical complex in its structure and effect. In addition, large amounts of data are necessary to capture as many as possible for the functional requirements bit constellations at the circuit inputs.

In the European patent application 21 404 a logic simulation machine is described, which performs the calculation of the logic gates decentralized by special processors. These processors are centrally controlled by two additional processors, which are responsible for the interaction of the special processors and which also control the exchange of logical signal values between the processors.

For the application of the logical simulation machine, two computers are additionally required to implement the "conventional functions" such as status display, interface control, code conversion and provision of test sequences, replication of large memory areas, fault simulation, etc.

The simulation engine is able to handle all the basic logic functions and is therefore applicable to the most general case. The realization of such a simulation machine is relatively complicated in connection with the necessary software and requires a special program system, which is often not available to the users or can not be used for reasons of process organization.

The patent application G06F / 238 592/4 describes a programmable device for simulating complex logical structures, which is suitable as a replacement for such logical structures. The use of such devices in an arrangement to simulate the complete system requires the hardware implementation of the wiring of these devices. This has a disadvantageous effect in the development process for such logical structures (master slice circuits) or for devices.

Object of the invention

The aim of the invention is to simplify and cheapen such a simulation device for rationalizing the development process of logical systems.

The invention is based on the object - to provide a simulation device for simulating logic circuit structures and complete logical systems based on the use of function-oriented simulation examples, wherein no wiring of the circuits under 'one another is required.

According to the invention, this object is achieved by

that the logical output levels of logical structures (iviaster slice circuit replicas) are entered in an information memory,

that the addresses of all logical contacts of a master-slice circuit simulation are contained in an address memory,

in that the address of a memory cell of the information memory is defined by the content of a memory cell of the address memory,

- That in a DOT memory, the individual logical output levels are stored on the output side interconnected contacts,

-that the logical state of a DOT is determined by reading a DOT memory line in parallel and then ANDing it,

that in a first stage all levels of the output contacts are sampled and entered into the information memory or DOT memory,

- That in a second stage, the distribution of the logic levels of the output contacts to the input contacts of i \ laster Sl ice circuit replicas by serial call all information storage cells according to the address provision is made by the address memory,

- that in subsequent calculation cycles

the calculation of the level values of the output contacts by master-slice circuit replicas takes place.

embodiment

In the drawing represent:

1 shows a device configuration for simulating and commissioning logical complexes,

FIG. 2 shows the block diagram of the simulation device with the lo-circuit structures ('Jaster-Sl ice-Schalikreisen') simulated by circuit simulators. FIG.

3 shows the structure of the address memory,

Fig. 4 shows the structure of the information memory, Fig. 5 shows the structure of the DOT memory, Fig. 6 shows the basic structure of a cell of the address memory for the addressing of the information memory

Fig. 7 shows the structure of a memory cell of the address memory

for a specific application, Fig. 8 shows the algorithm for detecting and distributing the

logical level. ^:

, The simulation device (SIiVlE) 1 of Fig. 1 is ver. buTiden with an operator and service processor (BSP) 2, which establishes the communication relationships with the SIME 1 and a computer 4. The computer 4 provides the data for loading the memories of the SIME I _{1 of} the central memory 3 and of the device simulator 5, the BSP 2 serving to realize the interface conditions between the computer 4 and the devices of the device configuration as shown in FIG. The SIME 1 is suitable for the simulation of logical complexes. It can take on the function of both central processing units and device control units. When used for simulating central processing units, the central memory 3 serves as a data memory and as an instruction memory in the sense of the principles of operation of the logical unit to be simulated and also as an intra-routine program memory. It is therefore connected to the SLViE 1 in a functionally appropriate manner. The device simulator 5 is needed for the simulation of device control units. He implements the functions of the external device. It is also possible to connect the external device instead of the device simulator. The replica of realizing the central unit standard interface is, in the prior art, often an integral part of a device controller for performing internal diagnostic functions. Otherwise, the BSP, 2 hardware or / and softwarenäßiq the functions, zur'nachbilduna the standard interface.

The realization of the device-side and the central unit-side interface is not the subject of the invention. Oeder Master-Slice Circuit (MS-SK) of a logical complex is replaced by a Circuit Simulator (SKS). These are summarized in a circuit simulator block 208. All logical contacts are connected together in the form of a BUS structure, so that all contacts of the same number are connected in parallel logically

 The technical design for this is realized in the data amplifier block 205. The addressing for the selection of the SKS is done by the address block 212 and for the contacts (data inputs and outputs) by the address block 210

 Both address blocks are connected to the central address counter 209, which controls the initial loading of the individual memories in the SKS, the central memory 3, and possibly the device simulator 5 in connection with the central logic block 211. The central logic block 211 is correlated with the BSP 2 The address memory (ADRS) 201 also receives its load data from the BSP 2 via the central logic block 211, the address providing being performed by the central address counter.

On the output side, the ADRS 201 is connected to the information store (INFS) 3 and the DOT memory (DOTS) 7 via the register 202 for address provision

 The data amplifier block 205 is connected on the input side to the OR circuit 204, to which the output data from the INFS 203 and the DOTS 207 are supplied via the AND circuit 206. ·

The operation of the SIME 1 will be explained with reference to FIGS. 2 to 8. '

It is assumed that for the logical complex to be imitated max. 512 SKS are used. ' Oecleia logical contact of these SKS is assigned a memory cell consisting of 17 bits in ADRS 201 (see Fig. 3). The ADRS

is organized like a matrix and contains in the vertical plane 512 addresses (9 bits) for addressing the 512 SKS and in the horizontal plane 56 lines for addressing z. For example, 56 logical contacts of an SKS. The INFS 3 (see Fig. 4) with the matrix structure 512 (vertical) χ 36 (horizontal) bits is used to store the contact information (log level) of z. B-. 36 possible outgoing contacts of a SKS. Calling a line in ADRS '201 simultaneously addresses an SKS. The content of a cell in the ADRS 201 also serves to address the INFS 3.

The source-consumer relationships are arranged in the ADRS 201 so that when addressing a consumer contact of a SKS the associated memory cell is called in ADRS 201 simultaneously. Its content is the address of the INFS 203, on whose memory the logical level of the addressed SKS contact is stored. This means that the corresponding 'source address in INFS always appears in the memory locations of the consumer contacts in the ADRS 201. The logical output contacts of an SKS are assigned to specific memory locations in the INFS 203. In the ADRS 201 is used to distinguish between an address for the INFS 203 and. DOTS 207 one flag per memory cell provided (see Fig. 6a). Another tag bit is necessary to define a "true" source address, 9 bits form the row address and 6 bits the column address for the INFS, which are identical to the SKS address or the contact address of the SKS.

For handling output side interconnections of contacts of SKS, DOTS 207 (see Fig. 5) is required, which is called for such links in place of INFS 203. It has the task of providing the logical state of a signal network, which is determined by one of the connected sources, in a memory cycle. For this purpose, such signal networks each have an address of the DOTS

assigned.

The DOTS is organized so that bit-by-bit addressing is implemented for write cycles and line-by-line reading for read cycles. The transmission of the level values from the SKS to the DOTS according to stage 1 thus takes place 'analogously to the INFS. , ,

For addressing the DOTS, starting from the principle, 17 bits are required (see Fig. 6b). Two bits are required to identify a particular source (master) and memory selection (INFS or DOTS), and 4 bits are used to address the output-side interconnected sources (16 max.).

If fewer than 16 sources are connected, make sure that all unused bits in a row contain a logical "1".

The assignment of an address for the DOTS to a signal network is selected so that the higher part of the row address of the matrix-like DOTS matches the SKS address of one of the output side interconnected source contacts (9 bits of the address are bound to it). The remaining 2 bits are used to distinguish the signal networks per SKS.

For the interconnected source contacts, the master-slave principle is used: In the ADRS, the master contact is the source address for interconnections on the output side, while the slave contacts (all other source contacts) are treated as consumers.The iviaster contact is identified by the flag bit in a memory cell in the ADRS In a memory cycle, the logic level is taken from the contact into the DOTS and the read information from the DOTS is conjunctively linked (within the memory read cycle) for stage 2. The logic level at the output of the AND circuit 206 is identical to the logic state of the output side interconnection of the SKS, and it is entered in the memory flip-flop of

addressed contact (identical to the address for the ADRS).

In the case of programming replication of the logical connections of MS-SK, it is important to detect once the connection of a signal network and, secondly, to determine its logical state. This happens in two stages: Stage. .1: Sampling of the SKS output level

- Addressing an SKS and calling the associated. row of the memory matrix of the ADRS

- Serial addressing of the contacts of the SKS and calling the respective memory cells of the ADRS

Calling of the storage space addressed by the memory cell in the INFS or DOTS and acceptance of the contact information (logical level).

Stage 2: Distribution of the logical levels of the sources to the consumer contacts of the signaling networks

- Addressing an SKS and calling a line of the ADRS

- Serial addressing of the contacts of the SKS and call of the relevant memory cell in. ADRS

- Calling of the addressed memory space in the INFS or DOTS and transmission of the level value in

the memory flip-flop of the addressed contact

of the SKS. , . '

; After completion of stages 1 and 2, the logic level at all the load contacts is present at time t and the release of a calculation cycle for all SKSs is given. "

If all the SKS has the end message for a calculation cycle, stages 1 and 2 are processed as described above. Is the system stable, i. h., no level changes were detected by any SKS, the release of the following clock phase. In the other case, the procedure described here will be repeated (possibly several times).

Any part of the logic within the logical system '(remainder logic) realized in TTL / STTL technology is converted into pseudo-MS-SK so that this residual logic can be handled on the basis of SKS. For the realization of this residual logic there are essentially two possibilities:. ·

- Manual implementation of TTL / STTL logic in function blocks of MS-SK

- Implementation with programmatic support.

One or more pseudo-MS-SKs can be defined, which are then treated as "normal" MS-SK. To simulate local memories in a logical system, a storage complex is to be created which meets the general application in terms of capacity and organizational form. This complex is implemented in TTL / MOS technology on plug-in units and must have the following capabilities or meet conditions: '- the control is analogous to the SKS

- Storage possibility of the addresses

- Storage possibility of the output data with bitwise addressing

- Storage of the input data with bitwise correction option

- Inputs and outputs analogous to the MS-SK (number, tristate values).

The local memories are present within the simulation device in a corresponding number.

The internal memory of MS-SK is handled programmatically in a calculation cycle of the SKS. The data store (DAS) in the SKS serves as storage. The data of the Speieherstrukturen in the MS-SK are to be serialized for the DAS, resp. they can only be retrieved serially by the DAS.

The calculation of the output levels of MS-SK by means of SKS is controlled by the central logic block 212. It is always started a calculation cycle when in the. Memory flip-flops of all SKS input contacts at time t

valid level value was entered. ,

Before entering the levels in these memory flip-flops, the SKS checks whether there is a level change. If this is the case, at the end of stage 2, the release of a further calculation cycle for the SKS takes place without a continuation of the cycle. The clock advance takes place only when no level changes were detected. A level change at the contacts of an SKS is stored in a flipflop in the SKS and reset at the end of a calculation cycle by the SKS itself. The addressing of the SKS is realized in groups. The central address counter controls 16 groups in address block 212. Oede group is able to address 32 SKSs. In the exemplary embodiment, 512 SKS can thus be addressed. The addressing of the contacts of a SKS is realized by the address block 210 by 6 address lines from the address counter 209 are amplified according to the SKS out. The addresses for the SKS contacts differ from the corresponding ADRS addresses only in the lowest position due to buffering (-1). They are stored or are to be provided by other circuitry measures. So it is always the cell t _n and the contact t ^ addressed. In terms of the circuit, it is ensured that the ADRS is activated in every possible memory cycle (except for DOT functions). This means that the data from the ADRS must be read into a register 202 which, depending on its contents (memory selection bit), drives the INFS or the DQTS. The register 202 consists of 2 sub-registers each 17 bits wide, which are alternately operated by the ADRS.

FIG. 7 shows a variant of the structure of a memory cell of the ADRS, which takes into account the design requirements of a logical system to be simulated. It can be seen from this that the adaptability of the circuit arrangement described here is given for many concrete applications by a suitable structure of the memory cell of the ADRS.

Claims (6)

-Ii-invention claim 1. Circuitry for simulating a logical
System, where master-slice circuits are replaced by circuit simulators, with an operating and service processor, characterized by an address memory (201) for storing addresses for one or more data memories (203/207), - A downstream register (202) for buffering
two memory cells of the address memory (201), - An information memory (203) for receiving logic levels, the address side with the register (202) and the data side via an OR circuit (204)
connected to a circuit simulator block (208), - A DOT memory (207) for storing logical
Level of output-side connections, which is connected in parallel to the information memory (203) on the address side and to the data side via an AND circuit (206).
connected to the OR circuit (204), an address counter (209) for providing the addresses for the address memory (201) and for the circuit simulator block (208), a logic block (211) for controlling the simulation device and for communicating with the operator and service processor. 2. Circuit arrangement according to item 1, characterized in that the information memory (203) is bitwise addressable for storing all logic output levels of the circuit simulator block (208) and structurally adapted to be simulated fviaster-slice circuits. 3. Circuit arrangement according to item 1, characterized in that the DOT memory (207) in the call width coincides with the number of output side parallel circuits allowed in a system and can be addressed by the contents of a cell of the address memory (201) and that the DOT memory (207) performs the write operations bit by bit and the read operations line by line. 4. Circuit arrangement according to item 1, characterized in that the number of inputs of the AND circuit (206) with the call width of the DOT memory (207) correlates. 5. Circuit arrangement according to item 1, characterized in that the circuit simulators in the circuit simulator block (208) are logically connected in parallel and are driven in contact. , For this 6 pages drawings