DD214506A1 - CIRCUIT ARRANGEMENT OF A SYNCHRONOUS 5: 1 FREQUENCY DISTRIBUTOR - Google Patents

Abstract

The aim and object of the invention is to provide a circuit arrangement of a synchronous 5: 1 frequency divider, which can be realized with the least possible component cost, as well as high Stoerfestigkeitigkeitsanspruechen sufficient. Furthermore, by the realization as a synchronous frequency divider the Zaehlfrequenz should be as high as possible. This is achieved according to the invention in that only three D flip-flops are used as memory elements, in which the clock inputs are interconnected in a known manner and their connection point simultaneously represents the input of the frequency divider, and that the negated output (5) of the first D Flip-flops (1) with the D input and the return input of the second D-type flip-flop (2), the output (6) of the second D-type flip-flop (2) with the D input of the third D-flip Flops (3) and the output (7) of the third D flip-flop (3) are connected to the D input of the first D flip-flop (1). The 5: 1 frequency divider can be used with advantage in the broad field of frequency processing technology, especially in the carrier generation of TF technology and the frequency generation of PCM systems as well as in measuring devices and devices of data processing and transmission.

Description

Title of the invention

Circuit arrangement of a synchronous 5: 1 frequency divider Field of application of the invention

The invention relates to a circuit arrangement of a synchronous 5: 1 frequency divider, which can be used in the wide field of frequency processing technology. Especially in the carrier generation of TF technology and in the frequency generation of PCM systems and in measuring devices and devices of data processing and data transmission, the frequency divider is suitable.

Characteristic of the known technical solutions

Implementations of synchronous frequency dividers with the divider ratio of 5: 1 are known in many forms. In the journal "Funkamateur" No. 11/1974, p 543 ff. And in "Handbook Integrated Circuits" by Kühn-Schmied, VEB Verlag Technik * 3erlin 1979, Chapter 12, proposals for implementation are listed, the expenses are economical and exclusively OK Use master slave flip-flops. Less commonly, there are 5: 1 frequency divider circuits with D flip-flops, all of which provide additional logic gates to provide the required feedback conditions

need. The disadvantage of these solutions is the increased expense for the realization of the feedback in the case of the use of D flip-flops. Furthermore, synchronous dividers that operate on the Oohnsonzählerprinzip, with D-flip-flops for division factors (2n-l): 1 for η ^ 2 not previously feasible. If the divider is realized with 3-K master-slave flip-flops, one must take the disadvantage of lower noise immunity into account and in the case of the synchronous divider with D flip-flops additional wiring and linking costs.

Object of the invention

The aim of the invention is to achieve the realization of the circuit arrangement according to the invention with the lowest possible component complexity at higher immunity to interference and to achieve a high counting frequency.

Explanation of the essence of the invention

The invention is based on the object to provide a circuit arrangement of a synchronous 5: 1 frequency divider, which increases the relatively low immunity to interference that is the OK master-slave flip-flops, and the additional logic for the feedback conditions, such as it was previously necessary when using D flip-flops, saves. Furthermore, to be brought to a maximum value by the circuit arrangement according to the invention, the upper limit frequency of the frequency divider.

According to the invention, this object is achieved in that there are only three D flip-flops as memory elements

are in which the clock inputs are interconnected in a known manner and their connection point simultaneously represents the input of the 5: 1 frequency divider, and that the negated output of the first D-type flip-flop with the D input and the reset input of the second D-flip Flops, the output of the second D flip-flop to the D input of the third D-type flip-flop and the output of the third D-type flip-flop to the D input of the first D-type flip-flops are connected. A 5: 1 frequency divider supplied positive edge of the input signal sets the second memory in working position, the second clock edge sets the third memory in working position, the second memory remains in working position, the third edge sets the first memory and thus is via the reset input the second D flip-flop also reset this. The third store is still in working order. With the fourth edge of the third D-flip-flop is now reset, the first D-flip-flop remains set, the second remains reset. The fifth positive edge of the input signal resets the first memory, the other two D flip-flops remain reset, so that so that the starting position is reached again. This results in a 5: 1 frequency division,

Advantageously, one uses as the output of the 5: 1 frequency divider either the output or the negated output of the first or third D-type flip-flops, since the outputs of the second D-type flip-flops are subject to greater system jitter. The functionality of the circuit according to the invention is ensured at all times, since the reset input of the second D-flip-flop one clock period before re-setting goes back to high potential and correct all unwanted Einschaltkorabinationsen after one clock period.

- 4 embodiment

The invention will be explained in more detail below using an exemplary embodiment. In the accompanying drawings: FIG

5 shows a circuit arrangement of a 5: 1

Frequency Divider Fig. 2: Pulse sequence diagram of the 5: 1 frequency divider

The 5 '' - frequency divider of Figure 1 consists of three D-Flxp-flops 1; 2; 3, in which the clock inputs C are connected in parallel in a known manner and their connection point simultaneously represents the input 4 of the 5: 1 frequency divider. At this input 4 is the input pulse train fp-_. The negated output 5 of the first D flip-flop 1 is connected to the D and R input of the second D-type flip-flop 2 and the output of which is connected to the D input of the third D-type flip-flop 3. The output 7 of the third D flip-flop 3 is connected to the D input of the first D flip-flop 1. This output also represents at the same time the output 8 of the synchronous 5: 1 frequency divider, at which the output pulse train f _out can be removed. But it can also be any output of the D flip-flops 1; 2; 3, z. B. the output 9 of the first D-type flip-flop 1 or the negated output 10 of the third D-type flip-flop 3, as output 8 of the 5 !! - frequency divider can be used. Between the two pulse sequences f _£ - _n and f _f . the following relationship exists:

OUT

^{f on}

Out

s

In Fig. 2 is the pulse timing of the inventive circuit arrangement of the synchronous 5: 1 frequency divider

posed. Fp- _n shows the input pulse sequence, f. the output pulse train, f the pulse train at the negated output 5 of the first D flip-flop 1 and f the pulse train at the output 6 of the second D flip-flop 2. The positive edges of the input signal f-. are marked with Tl to TlO. The operation of the synchronous 5: 1 frequency divider can be seen from Fig. 2.

Claims (2)

- 6 claim of invention 1. Circuit arrangement of a synchronous 5: 1 frequency divider, characterized in that only three D-type flip-flops are present as memory elements whose clock inputs (C) are zusaratnengeschaltet in a known manner and their connection point simultaneously the input (4) of the 5: 1 Frequency divider, and that the negated output (5) of the first D flip-flop (1) is connected to the D- and R- ^ q input of the second D-type flip-flop (2), the output (6) of the second D-type flip-flop (2) leads to the D input of the third D-type flip-flop (3) and the output (7) of the third D flip-flop (3) is connected to the D input of the first D flip-flop (1), wherein preferably one of the outputs (7; 9) and the negated outputs (5; 10 ) of the first D-type flip-flop (1) or the third D-type flip-flop (3) is also output (8) of the synchronous 5: 1 frequency divider. 2. Circuit arrangement according to item 1, characterized in that any desired output of the D flip-flops (1, 2, 3) optionally serves as output (8) of the synchronous 5: 1 frequency divider. For this 1 sheet drawing