DD208725A1 - LOGIC COMMUNICATION SWITCHING AND AND TYPE - Google Patents

Abstract

The AND logic type logic circuit is used to process logic signals, especially in integrated circuits, when the signal propagation time for an input is not increased. The task is to reduce the space requirement and the average power consumption by using transfer transistors. According to the invention, the inputs are connected to the output via transfer enhancement and depletion type transistors, the gate of the depletion transistor being connected to the output. The gate of the enhancement transistor is connected to the other input.

Description

U / Ö J

Logical combination circuit of the TJJTD-T yp field of application of the invention

The invention relates to a circuit implemented in MOS technology for the logical combination of two "binary switching variables". The circuit is used in electronic information processing devices, in particular in highly integrated electronic MOS circuits.

Characteristic of the known technical solutions

A known logic circuit of the UKD type in MOS technology consists of two series-connected negators, wherein the first inverter includes two series-connected enhancement switching transistors. The gate of the switching transistors are assigned to the Singangssignalen.

In total, the circuit contains five transistors. The average power consumption is I = I, where I is the saturation current of one of the two depletion load transistors.

Furthermore, it is known to avoid dei? Series connection of the Snhancement switching transistors in the first inverter to use a NOR gate with negated inputs.

25th JUK. 1982 * 018 510

This circuit contains seven transistors and the average power consumption is 'at the same statistical frequency of the input variables I = 1.25 I'

Another option is to connect two serially connected snubber switching transistors to the operating voltage U "" and to a ground via a depletion transistor "

A disadvantage here is that the output voltage is the operating voltage reduced by the threshold voltage and that the subsequent stages are delayed discharged via the depletion transistor, which corresponds to a poor high-low envelope. In the known circuits, the signal propagation time is from one input to the output is the same and is influenced by the load capacitances at the output and at the other gate-source node e'η of the respective depletion transistors. "

There are applications, ζ * Β »in clock-controlled circuits, where the same signal propagation time from both inputs to the output is not required.

Object of the invention

The object of the invention is to provide a logical combination circuit of the UTJD-TYP for two variables, which at the same time has a lower average current consumption at least from one of the two inputs (11) to the output with fewer elements at low signal propagation time.

Explanation of the essence of the invention

The object of the invention is to provide by means of transfer transistors a logical combination circuit of the UiTD type, which has a lower mean power consumption with fewer elements »

Features of the invention

The HND-type logic operation has two inputs and is single-stage.

In accordance with the invention, the first input E1 is connected to the output via a first transfer transistor of the enhancement type and the second input E2 is connected to the output via an aplete transfer transistor of the depletion type. In this case, the gate of the first transfer transistor is connected to the second input Ξ2 and the gate of the second transfer transistor to the output A »

If the potential at Ξ2 corresponding to the logical quantity "ü" is approximately 0 ToIt ₅ , the transistor 1 is blocked ₉ ie the signal at Si has no influence «A potential is established at the output A which is equal to the potential at S2 is about 0 volts.

If there is a capacitance with respect to the reference potential at the output A and this was charged, the potential of O YoIt at the output A only gradually sets in, as the capacitor discharges via the second transfer transistor.

If the potential at Ξ2 assumes an amount which is assigned to the logical quantity "1 ⁿ , the first transfer transistor is current-permeable and its conductance is substantially greater than that of the second transfer transistor." As a result, the potential at the output A assumes approximately the same value as at the entrance S1.

However, the first transfer transistor blocks again as soon as the potential at the output A is greater than at the input Ξ2, reduced by the threshold voltage of the enhancement transistor. Then the second transfer transistor provides for the remaining increase of the output potential to the full value of the Singangspotentiales at the input 32nd

The signal transit time from input J & i to output A "is

\ = ° fl ^Έ ^; ^U 2 ' ^ϋ Τ · switching)'

Where G is the load capacitance at the output A and / 3 is the transconductance of the first transfer transistor. The factor E ¹ is determined by the voltage values at the inputs Ξ1; Ξ2 (IL; U ₂ ) j from the enhancement threshold voltage (Um) and

from the defined threshold (U-, -, tj.) _} the

tocnaJ-u *

separates logical states 0 and 1, determined * This factor is different for different operating cases

It is essential that this signal delay is not mathematically related to the static current consumption. By choosing a suitable fb value of the first transfer to - / sistor-, one reaches the desired low signal propagation time from input E1 to A.

In contrast ^is the signal propagation time from the input S2 according to the output; A significantly longer,

The ÜITD circuit according to the invention consumes power only in one operating case, namely, when the input El to "low" and the input 32 to "high" are »Since this case is one of four possible, is at the same statistical frequency, the average power consumption I ^ O ₅ 25 I * '

Execution sb e i sp i e 1

The invention is explained in more detail in an embodiment and with reference to a drawing. FIG. 1 shows the logic circuit according to the invention.

The IMD type logic combination circuit according to the invention consists of a first and a second transfer transistor 1; 2. The input Ξ1 is connected via the first transfer transistor 1 and the input B2 via the second transfer transistor 2 to the output A, which is followed by a capacitor G simulating the following circuit. The gate of the transfer transistor 1 is connected to the input Έ2 and the gate of the transfer transistor 2 is connected to the output A »

Claims (1)

Erfi ndimg S anf ucii Logical combining circuit of IMD TjTp with two inputs «, characterized in that the first input (E1) via a first transfer transistor (1) of the enhancement type and the second input (Ξ2) via a second transfer transistor (2) of the depletion type is connected to the output (A), wherein the gate of the first transfer transistor (1) to the second input (Ξ2) and the gate of the second transfer transistor (2) to the output (A) is connected. For this 1 sheet drawings