DD206857A1 - METHOD AND CIRCUIT FOR ELECTRICAL PROGRAMMING OF FIXED STORAGE MEMORIES - Google Patents

Abstract

THE APPLICATION IS CARRIED OUT IN MICRORECHNER SYSTEMS TO CARRY OUT THE PROGRAMMING OF SEMICONDUCTOR STORAGE STORAGE MEMORIES (EPROM) ON A JACK AND ALSO IN THE BEGINNED CONDITION FOR TICKET AND MULTI-CARD COMPUTER ARRANGEMENTS. OBJECTIVE OF THE INVENTION IS TO REDUCE HARDWARE EXPENSES AND PRICES FOR MICRORE-PROGRAMMED PROGRAMMING ACCESSORIES AND TO PROGRAM VOB EPROM'S ANY MEMORY CAPACITY IN THE BEGINNED STATE FOR CARD MICRO-COMPUTERS. BY LOCATING THE EPROM'S AND DELETING THE UNCERTAIN JACKS, THE RELIABILITY FOR SAFETY WITH SHOULDER STRENGTH IS IMPROVED AND THE USE OF PRECIOUS METALS IS REDUCED. THE TASK IS THAT THE EXCHANGE OF INFORMATION BETWEEN THE CPU AND PROGRAMMING EPROM DIRECTLY COMES WITH THE CPU'S WRITE READING INSTRUCTIONS. THE PROGRAMMING PULSE FOR AN EPROM CELL IS RELEASED BY A WRITE COMMAND OF THE CPU ADDRESSED TO THIS CELL. THE ADAPTATION OF THE EPROM PROGRAMMING CYCLE TO THE CPU WRITE CYCLE IS THROUGH THE WAIT CONTROL SWITCHING AND CONTROL OF THE WAIT STATUS OF THE CPU. THE EPROM'S SELECTION SHOULD HAVE THE CHOOSING FEATURE "NOT SELECTED", "WRITING (PROGRAMMING)" AND "READING" AS POSSIBLE.

Description

Title of the invention

Method and circuit arrangement for the electrical programming of read-only memories 5

Field of application of the invention

The application of the method and the circuit arrangement is in the field of microelectronics, in particular micro-technology. It is used in microcomputer systems to enable the programming of electrically programmable semiconductor read only memories (EPROM) on a jack and also in the soldered condition for one-card and multi-card microcomputer arrangements.

Characteristic of the known technical solutions

It is known from DD-WP 14-9 278 .the programming of EPROMs using autonomously operating program-controlled "programmer" perform. It is also known to carry out the programming of EPROMs with the aid of programming accessories to be connected to microcomputer configurations

 Also, methods and circuit arrangements for programming EPROMs in the soldered state on the memory card are known for multi-card computer arrangements. In this case, the data and address bus and the lines required for the selection of the individual memory circuits must be led from the memory card.

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In all known microcomputer-controlled programming method, the communication between the central processing unit (CPU) and the EPROM to be programmed is not directly via read and write commands of the CPU, 5 but indirectly via before the EPROM switched buffer register and input-output commands of the CPU, via the buffer registers and corresponding access controls, the speed adaptation between the fast CPU and the very slow EPROM for the programming access takes place.

The known methods require by the buffer registers used a relatively high amount of hardware. The programming of the EPROMs on the printed circuit board in the soldered state is not possible with single-card computers in which the data and address buses are not routed from the card. By constantly improving the performance of the microcomputer circuits, and above all also increasing the storage capacity of EPROMs. Circuits, the number of applications for the economically favorable use of one-card computers, In many microcomputer applications such. B, in mechanical engineering, in transportation and military technology, where it depends on high resistance to shaking, the required reliability can not be secured by the use of EPROM's on jacks, The soldering and programming of the EPROM's is not possible for single-card calculator for the reasons mentioned , When using the EPROM's on jacks high demands are placed on the contact material of the EPROM's and the jacks, which make the use of precious metals necessary.

Object of the invention

The aim of the invention is to substantially reduce the hardware complexity and price in the case of microcomputer-controlled programming accessories and to program the programming of EPROMs of any desired memory capacity in the soldered state for single-card

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By eliminating the unsafe jacks, the reliability of the microcomputer arrangements is to be improved, especially with regard to the shaking resistance. By soldering the EPROM's the Kontaktprobiene between EPROM and jack are bypassed and the necessary use of precious metals are significantly reduced.

Explanation of the essence of the invention

The invention has for its object to provide a method and to implement the method to provide circuit arrangements with which the stated object of the invention is achieved.

According to the invention, the object is achieved in that the EPROM to be programmed is handled by the CPU as a RAM, for the write cycle time »read cycle time applies. For the write cycle (programming cycle of the EPROM), the WAIT state of the CPU is controlled via a circuit arrangement according to the invention and thus the adjustment of the EPROM to the clock scheme of the CPU write command is performed. The selection circuit of the EPROMs must make the selection possible for the states "not selected", "writing (programming)" and "reading". The important technical implications are that microcomputer programming add-ons can be built without additional buffer registers since the CPU-EPROM communication is through the CPU's read and write commands. The software required for programming is very simple, with the corresponding block commands result in short programs, EPROM circuits of one-card computers can be programmed by the own CPU in the soldered state. In this case, an additional circuit for selecting the programming state is required for each EPROM. The circuit arrangement for generating the programming pulses and for monitoring the WATT state of the CPU is required only once, irrespective of the number of EPROMs present on the board.

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lent, The erasure of the EPROM's is done in the soldered state, while the PCB is to be accommodated in the extinguisher; EPROMs which are not to be erased are screened against the UV radiation, 5

embodiment

The invention will be explained in more detail below with reference to exemplary embodiments of the 8 K EPROM U 555 and the 16 K EPROM 2716.

In the accompanying drawings show:

1 is a block diagram for explaining the method according to the invention, 15

2 shows a process-related circuit arrangement for a microcomputer based on the U 880 CPU.

Fig. 3: A selection circuit for 8 K EPROMs to implement the programming access.

Fig. 4: A selection circuit for 16 K EPROMs to implement the programming access.

The ordered according to the essential functions block diagram of the inventive method is shown in Fig. 1. The central processing unit 1 is connected to the address decoder 5 and the EPROMs 4 in a known manner via address bus 3 and data bus 2 and the memory access required signals MREQ and R ~ ü The driver and decoupling circuits required for larger systems are not for the sake of simplicity shown with

 In the CH line of each EPROM a CS ~ / WE-Tr is inserted via 7, which allows the selection of the programming state by means of the programmer permission signal (PGE),

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If there is a read or write access to one of the EPROMs, then the corresponding ÜS signal and thereby also the signal memory active (MAK) is activated. In the case of a read access, the "RÜ signal is also active, the IVAIT control 8 and thus the programming permission signal (PGE) are not activated, as a result of which the ÜÜ signal is directly switched through.

During a write access of the CPU, the signals MFfEÜJ, WR "and MAK are active, the" RÜ signal remains inactive under these conditions the WAIT control 8 is activated. As long as WAIT is active, the CPU remains in the write command, ie. H. on the address bus 3 is the address of the EPROM ZelIe to be programmed and on the data bus 2 are the data to be programmed. Since the PGE signal is active, the UE / WE driver 7 sets the +12 V level required for programming to the ÜSVWE input of the EPROM 4. Timers in the WAIT control S circuit will become the ones for programming The programming signal ("Fu") controls the programming pulse generator 9, which generates the 26 V programming pulses and parallel to the PR inputs of the EPROMs The pulse remains ineffective on EPROMs not selected for programming The +26 V voltage for the programming pulse generator 9 can be generated in a transverter, for example, from the +12 V supply voltage.

In terms of software, only the number of programming accesses for each EPROM cell is to be checked; Fig. 2 shows a circuit arrangement according to the invention for a programming accessory with programming pulse generator 9. With the aid of this programming accessory, the programming of EPROMs in the soldered state can also take place on single-card and multi-card computer arrangements. The cards must have the appropriate ÜH / WE drivers 7,

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The programming add-on consists of the control logic 10 of the WAIT control 8 with WAIT and PGE signal drivers (G S / G 10), the CW / WE control logic (G 6 / G 7) and the known programming pulse generator 9.

First, the work will be described as a programming addition, in which the EPROM to be programmed 4 is plugged into a jack, the EPROM is connected via data and address bus and the necessary driver directly to the CPU and occupies 1 K of the address space., In the example last K from address FCOO ...

In this working mode, the memory active signal (MAK) is inactive and always at H level. In a read access mode, the signals A 10 - A 15, MREQ and "RÜ are active, the WAIT control 8 is not activated and the" CS / WE input of EPCOM 4 is set to L potential.

In the case of a write access (programming access), the signal TTÜ is inactive and the WAIT control 8 is activated via the control logic 10. With the H-L edge at the A "inputs, the monoflops MF 1 and MF 2 are set simultaneously - The hold time of MF 1 is * v 10 ps and that of MF 2 is t 0.5 ms.

By setting MF 2, the D-flip-flop T 1 is set via the static set input and the WAIT signal is activated via G 10. MF 1 sets the required 10 ps settling time for the address, data and CÜ / WE signal for the EPROM 4. If MF 1 tilts back, MF 2 is still set, programming pulse generator 9 is activated via G 5, the pulse duration is determined by MF 2. When tilting down MF 2, the L-H edge at B input MF 1 sets it again, thus fixing the hold time of the EPROM control signals after switching off the programming pulse. It is equal to the response time and thus greater than required by the manufacturer, but brings a simplification of the circuit. If MF 1 returns, T 1 is reset via the dynamic input, as MF 2 is reset. This WAIT becomes inactive and the CPU 1 can execute the following command,

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As long as IVAIT is active, the EPROM 4 is selected for programming since the gates G 6 and G 7 + 12 V are oeleated to the SS / IE einqano.

If the programming accessory is used for programming soldered EPROMs on single-card or multi-card computer arrangements, then the gates G 1, G 6 and G 7 shown in FIG. 2 are not required, no EPROM 4 may be plugged into the socket. Fig. 3 shows the required on boards with soldered EPROMs additional circuit for selecting the programming state, it consists of the CÜ / WE drivers 7 and the circuit for forming the signal memory active (MAK). 6

 If an EPROM is accessed by a read or write command, the corresponding decoder output switches to the L potential and the signal MAK becomes active. If it is a read access, "RÜ is active, then the WAIT control 8 is not activated and the signals WAIT and PGE remain inactive. Thus, the L potential from the decoder is directly connected to the ÜS / üE input of the The access time increases only by the switching times of the D 126 gate and the D 204 inverter

 In a write access, MAK is active and TTD inactive., The WAIT control 8 operates in the manner already described and activates the WAlT and PGE signals. the programming pulse generator 9 applies the programming pulse to the PR inputs of the EPROM's. Since PGE is active, the selection input of the EPROM is set to + 12 V by the üS / V / E driver 7 and thus the programming state is selected.

4 shows the additional circuit required on the card for selecting the programming state for 15 K EPROMs. It consists of the "CT / PGM and UE drivers 11 and the switch to form the SoSicher active δ, the active signal FF indicates that the programming voltage (+ 26V) is present at the Vpp inputs of the EPROMs PG * is a TTL signal and is output

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of the gate G 9 shown in FIG. 2. In the case of a read access, the signals PG * remain inactive and the L potential of the corresponding decoder output is switched through to the CE / PGM and UE inputs of the EPROM.

When programming is accessed, the FF and PGE signals are active and the PG * signal goes to l-1 level for 50 ms. The ÜE * input of the EPROM is characterized by! -! - potential and the positive TTL programming pulse of 50 ms length acts on the CE / PGM input. To generate the 50 ms programming pulse, the RC elements are as shown in FIG. 2 Monoflops MF 1 and MF 2 to be measured accordingly,

Claims (4)

238070 2 Invention claim 1, method and circuit arrangement for the electrical programming of read-only memories with central processing unit, data bus, address bus, address decoder, programming pulse generator and a plurality of EPROMs characterized in that the information exchange between the CPU (1) and EPROM to be programmed (4) directly via write-read commands of the CPU ( l), wherein during the write command (programming cycle) on the address bus (3) the address' of the EPROM cell and on the data bus (2) is the cell information to be programmed and the programming pulse for the EPROM cell addressed by the addressed to this cell Write command of the CPU (l) is triggered and the adjustment of the EPROM programming cycle to the CPU write cycle by controlling the WAIT CPU s zu tan de s (1) via a WAIT control (3) and the selection of the programming state for the EPROM (4) via CS "/ WE driver (7) or" CE / PGM and ÖE driver (11), wherein the selection signal for one of the EPROM 's (4) is transmitted via the circuit for forming the memory active signal (6) or directly from the address decoder (5) to the WAIT control (8). 2. Circuit arrangement according to item 1, characterized in that the soldered or arranged on jacks and to be programmed EPROMs (4) directly or via intermediate driver and decoupling 38070 2 via data bus (2) and address bus (3) are connected to the CPU (l) and between address decoder (5) and EPROM's (4) CS / WE driver (7) or "CE / PGM and ÜE * driver ( 11), wherein the address decoder (5) is connected directly or via a circuit for forming the signal memory active (6) to the WAIT control (8) and the control of the programming pulses and the selection of the programming state for the EPROMs (4 ) via the WAIT control (8) consisting of two or three timers and a control logic (10) connected in front of it and comprising a plurality of gates, wherein the WAIT control (8) communicates with the CPU (1) via the signals for the memory access and the WAlI signal is connected and by a connection to the programming pulse generator (9) triggers the programming pulses. Circuit arrangement according to items 1 and 2, characterized in that the CH / WE driver (7) for an 8 K EPROM consists of a negating driver, a non-negating driver and a resistor combination, and the driver inputs with two outputs of one or two two address decoders (5) are connected and the driver outputs are connected to the resistor combination, wherein a request signal for the programming access is taken directly from the address decoder (5) and serves as an input signal for the WAIT control (8), 4. Circuit arrangement according to item 1 and 2, characterized in that the "CF / PGM and UE driver (11) for a 16 K EPROM consists of a logical combination with four inputs and two outputs whose outputs are connected to the" CT / PGM and ÖT inputs of the EPROM (4) are connected and whose inputs are connected to the address decoder (5) and the WAIT control (8), wherein a request signal for the programming access directly from the address decoder (5) is removed and as an input signal for the WAIT control (8) or between address 38070 2 decoder (5) and WAIT control (8) a circuit for forming the signal memory active (6) is connected. Here are the drawings