DD206596A1 - ARRANGEMENT FOR PROCESS-ORIENTED PROGRAM CHECK IN REAL-TIME OPERATION - Google Patents

Abstract

THE INVENTION ALSO RELATES TO A PROCESS-ORIENTED PROGRAM CHECKS IN REAL-TIME OPERATION IN THE MONITORING AND STORAGE OF SELECTED DATA. OBJECT AND OBJECT OF THE INVENTION IS TO DETECT AND EVALUATE IN PROCESS-ORIENTED DATA ACQUISITION AND EVALUATION IN REAL-TIME OPERATION BY SELECTION FROM A DATA STREAM OF PROCESS-SPECIFIC DATA. THE CORE PIECE OF THE ARRANGEMENT IS MADE BY A MAKING MEMORY AND TWO MORE RAM STORES CONNECTED TO A MICRO-COMPUTER. THE MAKING MEMORY IS PARALLELLY OPERATED TO THE PROGRAM MEMORY OF THE MICRO-COMPUTER. THE MARKING OF ANY BYTE IS PROGRAMMED IN THE PROGRAM. IN STORAGE STORAGE THE TYPE OF EXHAUSTIVE STORAGE ACTIVITY IS STORED. IN REAL-TIME OPERATION THE INTERESTING DATA AND THE BRANDS WILL BE IN THE FIRST OR CENTURY. SECOND RAM MEMORY WRITTEN. POSSIBLE APPLICATIONS OF THE INVENTION ARE THE PROGRAM REQUIREMENTS FOR MICRORECHNERS IN GENERAL AND THE PROCESSING TECHNOLOGY IN PARTICULAR.

Description

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Arrangement for process-oriented program sequence control in real-time operation

Field of application of the invention

The invention relates to an arrangement for process-oriented program flow control in real-time operation in the monitoring and storage of selected data. It is used in process analysis and program corrections in conjunction with a microcomputer design system.

Characteristic of the known technical solutions

The hitherto known solution is based on the use of logic analyzer in the implementation of program corrections, wherein the logic analyzers are connected to the system bus of a microcomputer and store in dependence of certain control signals, the data stream without further selection. In this case, the possibilities of data selection are limited, so that the storage capacity is usually reduced so much by the storage of redundant data that not enough payload can be stored. This disadvantage is due to the fact that logic analyzers are not designed for a process-oriented program sequence control (Döring, H .: Logic Analyzers - Devices of the Digital Testing Technology, Telecommunications Electronics H. 1/81, Verlag Technik, Berlin).

17.DELt981 * 978596

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Object of the invention

The aim of the invention is to propose an arrangement which allows the control of a program sequence in real-time operation. "

Explanation of the essence of the invention

The invention has for its object to develop an arrangement that detects and evaluates process-specific data in the process-oriented data acquisition and evaluation in real-time operation by selection from a data stream ©

According to the invention, the object is achieved by using a microcomputer and DA converter for data representation in that an address bus of the microcomputer is connected both to the address input of a tag memory, to an input of a control logic as well as to an input of an address multiplexer · A second input of the address multiplexer connected to the output of an address counter ·

On the output side, the address multiplexer is connected to both address inputs of a first and second RAM memory. «

A data bus of the microcomputer is associated with a data input of the tag memory, the second RAM memory, the DA converter, a second input of the control logic and with a data output of the first and second RAM memory, the address counter and a data input of a reset counter, while a Input of a data multiplexer is connected to a data output of the tag memory.

On the output side, the data multiplexer is connected to a data input of the first RAM memory and a second input of the data multiplexer is connected to the data bus of the microcomputer. «

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The tag memory and the two RAMs form the core of the array. The tag memory is addressed by the microcomputer addresses and operated in parallel with the program memory of the microcomputer. Thus, marking of any byte in the progamra is enabled.

The type of storage activity to be triggered and a corresponding mark are stored in the marker memory. These markers are written into the marker memory in a preparation phase. During the real-time run, the information of interest is stored in the second RAM memory and the associated mark in the first RAM memory when the Markeraspeicher a corresponding marker has been detected.

In the real-time run, both RAM memories are addressed by the address counter. The DA converter enables the analog representation of data both in real-time operation and in the evaluation phase of the second RAM memory. The entire process is coordinated by the control logic.

embodiment

The invention will be illustrated by way of example in connection with a development system for the 8-bit processor U 880 ·

The figure tends the circuit example ·

According to the figure, the arrangement consists of the microcomputer (1), marker memory (2), the RAM memories (3; 4), the control logic (5) »the DA converter (6), address counter (7), address multiplexer (8 ), Reset counter (9) and the data multiplexer (10) ·

The address bus (AB1) of the microcomputer (1) is connected both to the address input (AE2) of the marker memory (2), to an input (SE53) of a control logic (5) and to a

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Input (AE81) of the address multiplexer (8). The second input (AE82) of the address multiplexer (8) is connected to the address output (AA7) of the address counter (7), while the address multiplexer (8) output side with the two address inputs (AE3, AE4) of the first and second RAM memory (3 ; 4) is linked «

The data bus (DB1) of the microcomputer (1) is connected to the data input (DE2) of the marker memory (2), the data input (DE4) of the second RAM memory (4) ι the data input (DE6) of the DA converter (6), a second input (SE51) of the control logic (5) and the data outputs (DA3, DA4) of the first and second RAM memories (3; 4) _t the data output (DA7) of the address counter (7) and the data input (DE9) of the reset counter (9) linked. A data input (DE1O1) of the data multiplexer (10) is connected to the data output (DA2) of the tag memory (2), while the data output (DA10) of the data multiplexer (10) to the data input (DE3) of the first RAM memory (3) and the other data input (DE102) of the data multiplexer (10) is linked to the data bus (DB1) of the microcomputer (1) «

The control outputs (SB1) of the microcomputer (1) are connected to the control inputs (SE54) of the control logic (5), while the control output (SA51) of the control logic (5) to the input (SE2) of the marker memory (2), their control output ( SA52) is connected to the control input (SE8) of the address multiplexer (8), its control output (SA53) to the control input (SE3) of the RAM memory (3) and its control output (SA54) to the control input (SE10) of the data multiplexer (10) is "

Furthermore, the control output (SA55) of the control logic (5) to the control input (SE4) of the RAM memory (4), its control output (SA56) to the control input (SE6) of the DA converter (6) and its control output (SA57) both with the control input (TE9) of the reset counter (9) and with the

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Control input (TE7) of the address counter (7) interconnected. The reverse carry output (RA9) of the reset counter (9) is linked to the control input (SE52) of the control logic (5) «

In the example given, three 4K-deep RAMs are used. The marker memory (2) is 5 bits wide, the RAM memory (3) 3 bits and the RAM memory (4) 8 bits wide © To select despite the marker memory (2) of 4 K depth every possible address range »Provided a software-programmable address switchover of the 4 most significant address bits,

The tag memory (2) can be used to program various activities other than the tag, such as: B. Time measurement between two program locations, frequency count of command and loop calls and start of the analysis mode (cyclic storage of the data bus from a specific address).

With the help of a command in the preparation phase, it can be determined whether the first 4 K or the last 4 K data activities are recorded in the RAM memories (3) and (4) after the end of the real-time history «

Another possibility of commanding allows with high probability the recording of events in the immediate time environment of the occurrence of a random error »For this purpose, a special type of marking is provided, which sets an event counter (React counter, 9) to a preselectable value. Between two such markings, the data bus of the microcomputer (DB1) is stored for each machine cycle. These markings are distributed in the program so that an overflow of the reset counter (9) can not take place in an undisturbed sequence. If the instruction sequence is disturbed by a random error, the intended program sequence is generally left and overflow of the reset counter (9) occurs. which in turn is used to abort the real-time run. An additional command causes the display of equidistant time stamps in the RAM memory (4).

Claims (1)

invention claim Arrangement for process-oriented program execution control in real-time operation using a microcomputer and a DA converter for data representation, characterized in that - an address bus (AB1) of the microcomputer (1) connected both to the address input (AE2) of a marker memory (2), to an input (SE53) of a control logic (5) and to an input (AE81) of an address multiplexer (8), a second input (AE82) of the address multiplexer (8) is connected to the address output (AA7) of an address counter (7) and the address multiplexer (8) has an output side with the two address inputs (AE3, AE4) of a first and second RAM memory (3; 4) is linked, - A data bus (DB1) of the microcomputer (1) with a data input (DE2) of the marker memory (2) and with a data input (DE4) of the second RAM memory (4), a data input (DE6) of the DA converter (6) a second input (SE51) of the control logic (5) and a data output (DA3; DA4) of the first and second RAM memory (3; 4) »a data output (DA7) of the address counter (7) and a data input (DE9) of a Resetting counter (9) is linked, while a data input (DE1O1) of a data multiplexer (10) with a data output (DA2) of the tag memory (2) is interconnected and the data output (DA10) of the data multiplexer (10) to the data input (DE3) of the first RAM memory (3), another data input (DE102) of the data multiplexer (10) to the data bus (DB1) of the microcomputer (1) is connected « 235896 2 - All S expensive output e of the microcomputer (1.) to the control inputs (SE4) of the control logic (5) are interconnected, while a first control output (SA51) of the control logic (5) with the input (SE2) of the marker memory (2), a second control output (SA52) to the control input (SE8) of the address multiplexer (8), a third control output (SA53) to the control input (SE3) of the RAM memory (3), a fourth control output (SA54) to the control input (SE10) the data multiplexer (10), a fifth control output (SA55) to the control input (SE4) of the RAM memory (4),. a sixth control output (SA56) to the control input (SE6) of the DA converter (6) and a seventh control output (SA57) both to the control input (TE9) of the reset counter (9) and to the control input (TE7) of the address counter (7 ), the reverse carry output (RA9) of the reset counter (9) is linked to the control input (SE52) of the control logic (5) β For this 1 page drawing