DD206450A1 - ADJUSTMENT MARK FOR THE AUTOMATIC POSITIONING OF A SEMICONDUCTOR SUBSTRATE AND METHOD FOR THE PRODUCTION THEREOF - Google Patents

Abstract

THE INVENTION CONCERNS AN ADJUSTMENT MARK FOR THE AUTOMATIC ADJUSTMENT OF A SEMICONDUCTOR SUBSTRATE WITH LACQUER MASK RELATIVE TO AN ASSOCIATED TEMPLATE BY OPTOELECTRIC ADJUSTMENT SYSTEMS USING MONOCHROMATIC PROJECTION IMAGING AND A METHOD OF MANUFACTURING THE SAME. The alignment IS ERFINDUNGSGEMAESS FROM AT LEAST TWO ARE CRUISING, GRABENFOERMIGEN WELLS, THE VERTICAL AND BALANCED TO THEIR AXES DIFFERENT LONG STRUCTURE ELEMENTS IN PERIODIC REPEAT HAVING, THE ADJACENT STRUCTURE EDGE converge and roughened etched sidewalls FOR AGAINST ON THE SUBSTRATOBERFLAECHE SAME OR lowered PROFILE OWN. THE ADVANTAGES OF THE ADJUSTMENT BRAND ARE PARTICULARLY IN A TARGETED UTILIZATION OR SUPPRESSING INTERFERENCE EFFECTS FOR EXACT ADJUSTMENT AND POSITIONING THE TEMPLATE TO THE SUBSTRATE BEFORE EACH EXPOSURE STEP. THE FIELD OF APPLICATION IS PREFERRED TO THE SEMICONDUCTOR INDUSTRY WHICH OTHER FIELDS OF THE TECHNOLOGY ARE POSSIBLE.

Description

Alignment mark for automatic positioning of a semiconductor substrate and method for its production

Field of application of the invention

The invention relates to an alignment mark for the automatic positioning of a semiconductor substrate relative to an associated mask or template by means of opto-electrical adjustment systems using monochromatic projection imaging and a method for producing the same.

The field of application of the invention extends to the production of microelectronic components in the semi-conductor industry ·

Characteristic of the known technical solutions

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By means of opto-electrical adjusting systems, markings arranged on a semiconductor substrate are illuminated by the projection object, for example a projection lithography apparatus, which transmits the structural image corresponding to the respective method step to the substrate on a mask or stencil, the alignment mark illumination being effected by means of monochromatic light. which differs by the wavelength of the light used for the exposure · By the illumination of the alignment mark this is imaged in transparent markers of the intermediate template

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Bas resulting image is optically divided perpendicularly to the measuring direction in two image halves and photoelectrically compared "The time required for the comparison of the partial images Überdeokung is effected by a displacement of the alignment mark in x ~ or y ^ direction * to the reflected light output of the partial images is equal to _0. The for Recording the reflected luminous flux used photoelectric measuring heads serve as measuring elements for a control loop whose actuator represents the table system with the semiconductor substrate »The loop gain is automatically adjusted by the Meßsignalgrb'ße, the adjustment accuracy of the rise of the measuring signal in the vicinity of the zero crossing is dependent ₀ The increase in the measurement signal is determined by the contrast of the mark sum environment, by the ratio of the reflectance of the area around the alignment mark and reflectance in the mark area itself. "

It is known (DB »OS 25 39 206), by an anisotropic etching process in an alkaline etching solution on a crystallographically oriented (100) surface of a silicon substrate pyramids« · or to produce V-shaped etching structures or ₀ wells for high-contrast and process-stable Adjustment structures can be exploited ©

By illuminating such relief marks with light of narrow spectral bandwidth j which are coated with a photoresist, interference patterns _s produced by the superposition of the reflected light waves are produced in the region of the alignment mark. The surroundings of the brand structures produced in this way can be so strongly developed in that their contrast is not sufficient for a precise adjustment process, since the etching pits in the silicon have a relatively high degree of reflection

Furthermore, there is a drawback in that as a result of the etching process in the etching pits

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due to technological reasons remaining plateaus between individual squares of the grotto also interference phenomena occur * which lead to a further weakening of the surface contrast.,

The formation of interference structures in Justiermarkenumfeld and within the Justiermarke can be avoided according to DE-OS 24 22 982 and the Justiergenauigkeit be increased if by a photolithographic intermediate step, an exposure and free development of Justiermarkengebietes eg ₀ in 1: 1 contact or ₀ proximity method The delamination removal and consequent elimination of the interference features in the alignment mark region improves the registration accuracy of successive patterns by eliminating the coverage errors caused by the adjustment to anisotropically etched mask patterns with alternating resist mask. As a condition for the application of this method However, it is necessary to optimize the layer production on the substrate surface to relatively small permissible fluctuations and at the same time to use the layer thicknesses on optically well-reflecting regions for the technology refill ink. Furthermore, measures to produce a high degree of reflectivity in the brand environment, for example by applying contrast-promoting layers, are required, whereby a considerable complication of the structuring technology occurs, which contradicts the concern of low-defect structure generation for the projectile exposure process. For the reasons given, an automatic adjustment with the required technological coverage accuracy is not possible.

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- 4 Object of the invention

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The object of the invention is to allow "automatic adjustment of semiconductor wafers relative to a mask or stencil using monochromatic projection imaging and without paint removal in the alignment mark environment.

Object of the invention

The object of the invention is to develop an alignment mark and a method for producing the same, which make it possible to adjust the alignment process between the mask or stencil and the semiconductor substrate by means of opto-electrical alignment systems using monochromatic projection imaging with the highest precision and reproducibility at varnish-covered alignment mark "

Features of the invention

According to the invention, the object is achieved in that the alignment mark has at least two intersecting, trench-shaped recesses _s in which their axes orthogonal and symmetrically arranged _s differently structured elements are provided in periodic repetition, with touching the adjacent structural edges and the surface of the Etched edges is roughened. An advantageous design for the application results from the fact that the number of Xtzgrabenflenken is increased by a division of the long trenches or by a doubling of the short trenches.

Furthermore, the intersecting region of the etching trenches has the same level with the rest of the substrate surface. The calibration trenches of the alignment mark according to the invention preferably have a width of 3yH ^ n and a transverse trench spacing of 2 μm , the length of the long trenches after

the etch process is preferably 2 + 0.5 iun less than the width of the transparent mark in the intermediate template is β

In one embodiment of the invention in the axial direction of the etch trenches in pairs lined up short trenches are provided, which correspond with each adjacent to these axially and symmetrically arranged long trenches »

Furthermore, it is possible to make the short trenches so that they form a unit radially or that they are provided in a simple arrangement in the axial direction ©

In a further embodiment of the invention, the profile of the axially touching structural edges is lowered relative to the surface of the substrate, and the lowered, profile-highest points have the same level.

In accordance with the method according to the invention, the alignment mark transferred to the surface of the substrate provided with a layered material by means of lithographic imaging methods is etched isotropically etched as a mask on the semiconductor material and exposed to an anisotropic etching until adjacent structural edges are touched or under targeted lowering of the profile a roughening of the silicon surface in the etching trenches is simultaneously connected with the isotropic after-etching. The etchant used here is preferably polysilicon etcher.

It is also possible to perform the isotropic post etching simultaneously with the anisotropic etching by using the components of the anisotropic etcher with the isotropic etcher.

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embodiment

The invention will be explained in more detail with reference to an embodiment and of 13 drawings in which: Pig, 1 shows the geometry of an alignment mark, schematically;

Fig. 2 shows the arrangement of the short and long transverse trenches in the design 5

Pig x. 20.1 shows the section through an anisotropically etched semiconductor substrate;

FIG. 3 shows the lateral structure of the transverse trenches after the etching process; FIG.

FIG. 3d shows the section through the transverse trenches along the etch pit axis; FIG.

Fig. 4.1 'to 4 · 7 variants of the transverse trenches;

5 shows the section through the transverse trenches with a resting mask after the anisotropic etching process;

Fig. 5o1 a profile reduction after the isotropic etching process in section ·

Fig. 1 shows the schematic representation of an alignment mark 1 according to the present invention with in the x- and y-direction perpendicular to each other and intersecting axes, as the etching pits 3; 3 × 1 and how it is used for the automatic positioning of a (100) -oriented semiconductor substrate by means of monochromatic projection imaging.

The etching pits 3; 3 · 1 of the alignment mark 1 consist of radially to the axes x; y mutually consecutively arranged short and long marks, which are transmitted by means of a suitable imaging method on the provided with an oxide mask 9 semiconductor substrate 2. The alignment mark is executed in the design stage ao that the intersecting region of the etching trenches 3; 3 · 1 remains free. When enlarging a section of the etching pits 3 or 3d, it can be seen that the markings consist of short ones

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Trenches 4 and consist of long trenches 5, which in Pig «, 2 ira. Draft ", The dimensions of the trenches 4? 5 are selected according to the invention ₉ so that they have a distance of preferably 2 Lm and a width of 3l » ^m with each other» The length of the long trench is formed so large that preferably after a subsequent machining process 2 + 0 * 5 M ^ - smaller as the width of the transparent mark is in an intermediate template, not shown.

After the transfer of the design pattern of the alignment mark into the photoresist layer by means of a suitable exposure * process and subsequent development process and after generation of the etch mask by removing the applied in a previous step on the semiconductor surface technological layer «preferably a thin oxide layer - in the free-wound areas of the resist mask etched the underlying surface of the semiconductor substrate 2 under the respective openings anisotropically, so that due to the (100) orientation of the crystal structure, a V-shaped recess 10 is formed under each opening of the oxide mask 9, the four oblique (111) surfaces or, Itzflanken 6, whose angle to the surface of the semiconductor substrate 2 is about 55 ° (FIG. 2.1)

During a running adjustment process, the surface of the semiconductor substrate 2 is illuminated via an optical adjustment device, not shown, wherein the incident on the wafer rays 11 are reflected by the unstructured surface almost perpendicular to the lens, not shown. On the Ätzflanken 6, however, the beams 11 are reflected according to the angle of incidence so that only a small amount of light intensity enters the object, so that in the imaging beam path for adjustment, the Ätzflanken against the semiconductor surface appear optically dark, but at a relatively high reflectance.

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To increase the contrast, the anisotropically etched structure is etched isotropically "

During brief action of the etchant on the Ätzflanken 6 is a roughening 6 ₀ 1 thereof, so that the proportion of light reflected in the lens due to scattered reflections within the etch trenches 3? 3 <> 1 is significantly reduced, whereby a reduction in the reflectance is achieved.

The etching process is advantageously carried out so far that the etching mask 9 is undercut without influencing the profile cross-section until adjacent structural edges touch (Pig ₀ 3 * 1).

Further etching causes the profile to be lowered below the surface of the semiconductor substrate 2 (Mg.sup.-5) for the alignment marks according to Pig.sup.4.sup.-4. 4 * 7 such that an overall profile according to Pig «5 * 1 becomes apparent. The profile lowering further leads to a flattening of the profile, wherein the angle, which include the (111) surfaces, is changed so that the incident light is reflected approximately in the original direction and thus visually brightened. As a result, the etching edges 6 enclosing the adjacent area contrast in high contrast with the brightened area. When using the alignment marks in the technological semiconductor manufacturing process, it is advantageous if the alignment mark area is exposed in each processing plane simultaneously with the exposure of the image field so that a layer structure over the alignment mark area is prevented by the subsequent preparation steps, which would lead to a weakening of the brand contrast "

In the case of exposure and free development of the alignment mark region, a free etching is given by the technological layer of the respective structuring plane, while in the case of paint covering, growth of a subsequent layer is prevented.

Claims (3)

invention claim 1β alignment mark for the automatic positioning of a semiconductor substrate relative to an associated mask or template by means of opto-electrical Justiersysteme consisting of in the semiconductor substrate surface by appropriate process steps of the Beschichtung, development and Itzung for patterning of coated semiconductor material generated, preferably pyramidal depressions »characterized in that the Recesses are formed as at least two, preferably vertically stacked, crossed etch pits (3; 3 * 1), wherein the etching pits (3; 3 «1) have perpendicular and symmetrical to their axes periodically juxtaposed recesses of different dimensions, touching the adjacent structural edges · Adjusting mark according to item 1, characterized in that the recesses in the etching pits (3; 3d) are formed as short trenches (4) and long trenches (5) whose etching flanks (6) are provided with a roughening 3. Justiermarke according to item 2, characterized in that the number of planks by dividing the long trenches (5) in the axis of the etching trenches (3; 3 * 1) erhb'ht. 4o alignment mark according to items 2 and 3, characterized in that the number of planks by doubling the short trenches (4) is increased. Alignment mark according to item 2, characterized in that the etching trenches (4; 5) preferably have a width of 5 μm after the etching process, the length of the trenches (5) being preferably 2 ± 0.5 μm smaller than the width of the transparent marking in FIG the intermediate template is 242963 I 6. Justiermarke according to the points 2 to 5, characterized in that the profile of between the long trenches (5) arranged short trenches (4) relative to the surface of the substrate (2) has the same level, Alignment mark according to item 1, characterized in that in the axial direction of the etching pits (3; 3 · 1) are provided one behind the other and paired short trenches (4) corresponding respectively to these axially and symmetrically arranged long trenches (8) _o 8 _e alignment mark according to point 7, characterized in that the short trenches (4) radially form a unit (7o1) < 9. alignment mark according to item 8, characterized in that the short trenches (4) are provided axially in a simple arrangement. 1Oo Justiermarke according to the points 7 to 9i characterized in that the profile between the axially and symmetrically arranged long trenches (8) relative to the surface of the substrate (2) is lowered and the lowered profiles (4 «1) within the etching pits (3; 3 · 1) have the same level ο registration mark according to item 1, characterized in that the intersecting area (1 <> 1) of the pits (3; 3 * 1) with the surface of the substrate (2) has the same level. ; 12 »method for producing an alignment mark for the automatic positioning of a semiconductor substrate relative to a template by means of opto-electrical adjustment; systems using monochromatic projection; 1, wherein the structure of the alignment mark is passed through a mask by means of lithographic imaging methods onto the surface of the layered layer. transferring the imaged structures to an anisotropic etching process, characterized in that the produced structure is isotropically replenished until adjacent structural edges within the etching pits (3; 3 * 1) touch and the surface of the Etching flanks (6) has a roughening (6 _e 1), 13o method for producing an alignment mark according to item 12j, characterized in that the isotropic. Nachätzung performed by polysilicon etcher we do 14 »method for producing an alignment mark according to item 12, characterized in that the isotropic etching is carried out in conjunction with the anisotropic etching. For this 2 pages drawings