DD158078A1 - METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT OF A UNSYMMETRIC DMOS TRANSISTOR - Google Patents

Abstract

The invention relates to a method for producing a semiconductor device of a single-ended DMOS transistor with self-aligned gate structures. It is an object of the invention to produce semiconductor devices based on the known DMOS principle with better use value properties, such as high steepness, high cutoff frequency and reduced technological complexity, such as number of process steps, high yield. The object is achieved according to the invention in that a first photoresist mask A is used for structuring all gate webs and required polysilicon structures, and a second photoresist mask B is positioned on the not removed first photoresist mask A such that preferably only the drain-side halves 8 of the gate web of the DMOS Transistors is covered. In this case, only the DMOS source areas 11 are opened and all other areas of the pane with the aforementioned second resist mask B are protected against the channel pre-assignment for the DMOS transistor. The application of the invention is in semiconductor manufacturing, especially in p-channel and n-channel silicon gate technology.

Description

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Title of the invention

Process for the preparation of a semiconductor device of a single-ended DMOS trans tor

Field of use? the invention

The invention relates to special process steps in the production of MIS devices with selbstjustier'enden gate structures · It is considered as an application of the DMOS transistor produced on the basis of the double-diffusion principle, in particular its use as an integrated component. The DMOS transistor is in the pursuit of improved dynamic transistor parameters because of its relative to existing solutions, reduced effective Kanalallähge everywhere einotzbar where short switching times and thus high signal processing speeds are required _o

Characteristic of the known technical solutions

It is known that the integration of the DMOS principle in conjunction with the silicon gate technique proves to be very advantageous for circuit concepts. From the short effective channel with "" ^ eff ^ca * ^ / ^um , the essential advantages of the DMOS principle such as Space savings and high signal processing speed.

The following principal additional requirements arise for the application of the DMOS principle in the silicon gate technique for the asymmetrical DMOS transistor: 'M

Generation of a short out-diffused channel in the neighborhood of the source-side PN junction

- Application of an additional photochemical level.

To generate the short channel, it is necessary to introduce a corresponding pre-emptying amount into the source region of the DMCS trans istors. All other areas must be covered by a protective layer. This is followed by a diffusion step in order to design the desired doping profile in the space between source and drain in connection with the source / drain diffusion.

It has already been proposed to perform the selective pre-emption of the DMOS source regions by using a two-step structuring, wherein a first level of the opening of the source window of the DMOS transistors and the remaining polysilicon layer is protected by photoresist as implantation mask. A second level is used after the channel pre-emption of the generation of the drain edge of the DMOS transistors and the other structures in the polysilicon.

adversely, the reproducibility of the source / drain distance depends on the positioning accuracy of said planes from each other.

According to US-PS 3883372 a one-step structuring is known, wherein the polysilicon via a thicker CVD-SiO ₂ auxiliary layer or according to IEEE Journ. of SC 11 (1976) 4, 443-452 via an SiO ₂ ZSi ₃ N ₄ auxiliary layer combination is etched. In this case, the generation of the thicker auxiliary layers or auxiliary layer combinations represents additional technological expense for the DMOS process and mechanical stresses and the etching of said layers leads to an overall risky process, z. B ₀ Sub etching of the gates, especially in the removal of the auxiliary mask, development of a fir-tree structure, poor threshold voltage control and others

Object of the invention.

The aim of the invention is a more economical method over existing solutions by utilizing standard materials. The disadvantages of expensive and time-consuming CVD processes as well as the uncertainties of the adjustment of two levels to each other are avoided.

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Explanation of the essence of the invention

The invention has for its object to provide a method for producing a semiconductor device of a single-ended DMOS transistor with a minimum number of process steps using known process technologies.

According to the invention, the object is achieved in that the structuring of the poly-silicon gates in one step takes place via a first photoresist mask. For this purpose, there is a thin oxide layer of 10 to 100 nm, preferably 30 nm, due to the better adhesion of the photoresist to the polysilicon. The said oxide layer furthermore prevents undesirable erosion phenomena of the polysilicon in the channel deep diffusion.

During the use of the polysilicon, all necessary structures are produced with the aforementioned first resist mask. In contrast to existing solutions in the silicon gate techniques, said first photoresist mask is not removed, but remains on the etched structures. The lacquer thickness is to be selected such that sufficient implantation protection during channel pre-assignment is provided by the lacquer mask remaining on the gates.

On the cured first photoresist mask, a second photoresist layer is applied and treated according to the usual photochemical methods.

The second photoresist mask is preferably positioned at the center of the gate stems of the DMOS transistors, the center marking the distance between the source and drain so that the source regions of the DMOS transistors are opened: all remaining disc regions with the first photoresist mask, the second Photoresist mask and the first and second photoresist mask are covered. '. ,

The gate oxide remaining in the source window need not be removed. The conditions of the pre-assignment are to be determined by selecting appropriate energies, wherein the range of the dopants must be greater than the thickness of the SiOg layer remaining in the source window. The adhesion of the second Fofeolackmaske on the first photoresist mask is ensured by an unavoidable easy resolution of the first photoresist mask through the second photoresist mask. The stability of the first photo

varnish mask .isti can be adjusted by appropriate annealing times and temperatures during the usual curing process. "The use of undiluted photoresists is expedient.

After the preallocation for the potassium diffusion takes place according to known methods, the removal of the first and second photoresist mask and other known processes of the silicon gate technology.

embodiment

The invention will be explained below using an exemplary embodiment. The accompanying drawings show:

Fig. 1j DMOS transistor representation with first photoresist mask

Fig. 2j DMOS Tr ans is tor dar s tion with first and second Fotplackmaske

Fig. 3: Arrangement of the second photoresist mask on the gate

The generation of the field areas 1 and active regions 2, see Fig. 1, as a measure to prevent undesired current paths, the preparation of the transistor structures on ₀ close usually this case, the load transistors made before or 'after setting the threshold voltage to generate the gate oxide 3 and Depending on the state of development of the silicon gate technique measures to secure the gate-source connection of the depletion Lastelementeo The deposition of poly-silicon 4 as a gate material can be doped or * undoped in the further process, the thickness of the polysilicon layer between 3OO nm and 600 nm, typically 400 nm. "

The further treatment is followed by the oxidation of the polysilicon with oxide thicknesses 5 of 10-100 nm, but typically 30 nmj is not absolutely necessary. The thin oxide layer serves the better paint adhesion, but can also be ensured by the use of so-called adhesion promoter. The oxide layer should not be thicker than the gate oxide.

After the oxidation, the photoresist mask A is applied and the Gafeestege the DMOS transistors and load transistors and all other required polysilicon structures produced. The photoresist mask A is expediently at somewhat higher temperatures or "longer" temper pages than in the standard processes

I 'b 4 I

is common, hardened, but is not mandatory. The hardening temperature and time can be adapted to the respective photoresist and technological process. The photoresist mask A is not removed in contrast to the silicon gate process. A further photoresist mask B is applied to the photoresist mask A, see FIG. 2, which is positioned twice on the center of the DMOS transistor bridges, the center being the distance between the source and Drain indicates so that the source regions of the DMQS transistors remain open.

In this case, the photoresist mask A is loosened slightly from the photoresist mask B or softened on the surface and affords the adhesion of the photoresist mask B to the photoresist mask A.

The required positioning accuracy is G 1/2 gate length for each state of the design rule.

The stability of the photoresist mask A can be increased by using undiluted photoresists.

The protection against implant 6 is given by the resulting photoresist thickness A, source side of DMOS gate 7, photoresist thicknesses A and B, drain side of DMOS gate 8 and remaining polysilicon structures, and photoresist thickness B, drain area of the DMOS Transistor 9 »Source and drain region of all other transistor structures, given. The implantation conditions are selected according to the thickness of the photoresist mask A, weakest point, and the oxide thickness in the source window »

Bs is not favorable to remove the oxide in the source window before the channel pre-occupation, since the photoresist mask A is charged and. Furthermore, erosion phenomena of the silicon in the source window can occur during the channel deep diffusion. However, the "fate of the oxide is not absolutely necessary if sufficient adhesion of the photoresist mask A on the polysilicon 4 is given.

The preparation of the DMOS transistors is continued by the processes, paint removal and channel depth diffusion. In the case of simultaneous diffusion for channel and source / drain regions, the intermediate channel depth diffusion is omitted. Further steps to complete the structures are closing. on.

Claims (1)

··. , 223 7 54 7 ₆ invention claim Method for producing a semiconductor arrangement of an asymmetrical DMOS transistor in a silicon-gate technique using known method steps up to polysilicon deposition and anodization, characterized in that - The polysilicon Ebenö (4) is etched in only one structuring step using a first resist mask (A), the lacquer mask (A) remains on all structures after the structuring of the polysilicon plane (4), - A second resist mask (B) is preferably positioned along the center (10) of the gate webs of the DMOS transistors and that while only the DMOS source region (11) remains open. For this 1 page drawings