DD150135A1 - STARTLOGIC FOR PSEUDO ACCIDENT GENERATORS - Google Patents

Abstract

The invention relates to a starting logic for pseudo-random generators and relates to the field of pulse technology. Methods in which the application of the invention is possible and expedient are all coding, metric, and computational methods in which pseudo-random generators are employed. The object of the invention is to provide a starting logic for all types of pseudo-random generators, which is simple in construction and handling and is also suitable for use in pseudo-random generators of variable length. The object is achieved according to the invention in that a clock cycle and the sequence generated by the pseudo-random generator are routed via gates to the signal inputs of a counter. The counter are control inputs and the like. a comparison device. assigned, d. on reaching a zero-run bigger N-1 over another log. Gates a logical one into the pseudo-random generator.

Description

Dipl.-Ing. Heinz-Georg Nacke Dresden, 08.04.1980

Title of the invention

Start logic for pseudo-random generators

Field of application of the invention

The invention relates to the field of pulse technology. Objects in which the application of the invention is possible and expedient are computing devices, measuring devices and encoding devices in which pseudo-random number generators (PsZG) are used.

Characteristic of the known technical solutions in a wide range. 3 rd of the measure,. Transmission, control and computing technique pseudo-random generators are used, which consist of feedback N-stage shift registers whose input information is formed by modulo-2-Additlon the contents of the last stage N and other stages. Such an autonomous shift register automaton can go through two independent cycles: the actual pseudo-random cycle with the period L *, where the vector X s (χ,, .., X ₁ ,... · X _n ), X.-binary symbol, all possible ones Combinations except for one, X = O, and the cycle X = O, which the automaton can not leave. Therefore, it is necessary to provide in practical pseudo-random generators a start logic, which enters a 1 in the shift register at the state X = 0. In a known start logic for pseudo-random generators that generate m-sequences, all outputs of the memory elements X ^ are connected to an N-times NOR (see, eg, in: Massen, R .: Stochastic computer technology, Munich, Vienna 1977, p 278, 279 ). The exit

of the N-times NOR is assumed to be state 1 in case the N memory elements of the SR have the state O. This signal is given to the SR input with the previous input signal of the SR via an antivalence element. This known starting logic has the disadvantage that at large N complex NOR elements must be formed and a large number of additional connections are necessary. Furthermore, the known start logic requires access to all memory elements of the SR, which excludes their use for pseudo-random number generators constructed with integrated circuits in which not all outputs of the memory elements can be tapped off.

Object of the invention

The object of the invention is to provide a start logic for pseudo-random generators, which is simple in construction and in which no access to all memory elements of the pseudo-random generator is necessary,

Explanation of the essence of the invention

The invention has for its object to make a start logic for pseudo-random generators consisting of a sequence generator in the form of an N-stepped shift register with at least one outer or inner anti-coincidence circuit which generates an m-sequence, so that the shift register always the actual pseudorandom cycle works even in the case when the machine was in the state X = O, which may be caused by an external or internal action (when switching on the power supply, due to interference), was, for this start logic no further access to the memory elements of Pseudo-random generator is required as the one used for its actual construction ·

This object is achieved according to the invention in that a clock signal and the m-sequence, which can be removed at the output of any memory element of the SR or at the input of the shift register, are given to a gate and selection circuit with a downstream counter, the clock pulses be given to the count input of the up or down counter, as long as the m-sequence has the level Low, In the case

that the m-sequence has the level High, the counter is set in a state determined by the control inputs, the signal at the carry output of the counter then appears when at least N times the level low in succession in the m-sequence that at the Tor and selection circuit is present, has appeared »

The carry output and the signal of the antivalence element are given to the input of the SR via a wide antivalence element, such that the starting logic has no influence on the work of the pseudo-random generator in the actual pseudorandom cycle, and in the case that the automaton in the cycle Ύ = 0 which is identified by the appearance of at least N zeroes at the gate and select circuit, by which a logical 1 is input to the pseudo-random generator, thereby passing the automaton into its pseudorandom cycle. Sequence exploited: The number of blocks with m consecutive same sequence elements of an m-sequence, which are framed by inverse elements, are called "runs". There is one zero run of length N-1 per period, and no zero run of length N or greater N.

embodiment

The invention will be explained below with reference to the drawing in detail. Show it:

1 shows the block diagram of a possible pseudo-random generator with a start logic in accordance with the invention;

FIG. 2 is a timing diagram to FIG. 1 which shows the signal curves occurring in operation of the start logic during undisturbed operation of the pseudo-random generator;

FIG. 3 is a timing diagram for FIG. 1 showing the waveforms occurring during operation of the start logic in the state X = 0 of the pseudo-random generator;

Fig. 4 shows a shift register for the construction of simple pseudo-random variable length generator with a start logic according to the invention, which are externally connected

can and simultaneously generate a sync pulse for the pseudo-random generator.

The pseudo-random generator shown in FIG. 1 consists of the seven memory elements 11, 12, 13, 14, 15, 16, 17 and the antivalence gate 1. Er is driven by a clock clock 2. According to the task of the starting logic, the cycle X = O of the pseudo-random generator is not allowed to be solved so that the clock signal 2 and the ra-sequence, which is taken at the output of the antivalence gate 1, are given to an OR gate 22 whose output is given to the counting input 36 of a counting and charging circuit 30. In this case, a counting function is triggered only if at the moment the clock clock edge has the m-sequence low level.

In Fig. 2 is the clock clock 2, the m-sequence at the output of the antivalence gate 1 and 21, the output of the OR gate 22, and the resulting counting functions of the memory member 31, 32, 33 of the counting and charging circuit 30, which in this form exists as an integrated circuit, shown. It should be noted that each high level of the m-sequence, which is applied to the charging logic 37 of the counting and charging circuit 30, the preset value 41, 42 and 43 in the corresponding memory members 31, 32, 33 of the counting and charging circuit The load and load circuit shown in the concrete example reduces its value at each clock pulse coming from the OR gate 22. In the case of the work of the pseudo-random generator with K s 7 in the pseudorandom cycle shown in FIG. 2, the maximum zero-run K is -1, ie 6. The counter 30 thus does not reach the state in which all of its memory elements have the level Low. Since this state identified by the output 38 of the counting and charging circuit 30 does not occur, the output 38 always keeps the low level as long as the pseudo-random generator is in the pseudorandom cycle, and the antivalence gate 21 remains in this regime without affecting the logical function of the pseudo-random ·

In Fig. 3, the timing for the pseudo-random generator shown in Fig. 1 is shown, ¹ when it has been at a moment T in the cycle X = O · In this case, the counter 30 reaches the state in which all its memory elements reach the Level Low, and at the output 30, the high level is caused, which is stored on the antivalence gate 21 at the moment of the edge of the clock clock 2 in the first memory element 11 of the pseudo-random generator · From this moment on, the pseudo-random generator is in the pseudorandom regime, and it from here on, the statements made above for FIG. 2 apply ·

4 shows a start logic according to the invention, as it can be used as an additional block for variable length pseudo-random number generators. (Same elements as in FIG. 1 are given the same reference numerals). It is a shift register with M memory elements 11, 12, ···, 18, ··· 19, ··· from which two memory elements 18, 19 are selected and connecting their outputs to the inputs 3, 4 of the antivalence gate 21, a pseudo-random generator can be formed, which operates with a clock cycle 2. In order to use a start logic according to the invention for the variable length pseudo-random generator, the outputs of the variable memory element 18, 19 are connected to the inputs 23, 24 of the antivalence gate 1. The output 25 of the antivalence gate 1 is connected to the input 4 of the antivalence gate 21 and to the input of the Ol-gate 22. At the second input of the OR gate clock clock 2 is switched. The further structure is analogous to that shown in Fig. 1, and thus also the output 36 of the counting and charging circuit 30 is connected to the input 3 of the antivalence gate 21. The memory elements 31, 32, 33 of the counter and Ladesohaltung 30 pre-adjusting control signals 41, 42, 43 are set in the presetting 40, in such a way that only at a done after loading zero run the length N at the output 38 a High level is generated. In the circuit shown in Fig. 4, it would be the binary coded value

N-1. Further shown in Fig. 4 is a simple way of obtaining a sync pulse of the pseudostoohast signal. To the outputs of the memory members 31, 32, 33, a cycle 50 is switched. The cycle identifies the state of the counting and charging device 30 at the moment when N-1 clocks in a row at the output 25 were low. In the example shown in FIG. 4, this state corresponds to a binary one. Since this zero-run of length N-1 is in the pseudo-random pseudo-randomistic regime of the pseudo-random

# N nerators occurs only once in the period L = 2 - 1, the output signal 51 of the Konjununktors 50 can be used as a synchronization pulse.

Claims (3)

invention claim 1. start logic for pseudo-random number generators, the former consisting of at least one logic gate, a counter with control inputs, a comparator and another logic gate, characterized in that the sequence supplied by the pseudo-random generator and a clock clock are applied to a logic gate, wherein at the output of the Gatters at a low state of the sequence count pulses are generated, which are given to the downstream counter, which is set in the event that the sequence is high, to a value given by the control inputs, and in the presence of the counts its state »such changes in that only when the sequence N or more cycles one after the other has the state Low, does such a state be reached in which the comparator emits a pulse which is given via a further logic gate which causes, in the case of emitted pulse of the pseudo-random generator the state λ = 0 leaves, but in any other case the work of the pseudo-random generator is not affected · 2 »starting logic for pseudo-random number generators according to item 1, characterized in that the start logic in addition to the elements mentioned in item 1 has a further comparison means which identifies the state of the counter, which he holds after N-1 clocks in a row the sequence Had low, and then gives a pulse that can be used to synchronize the pseudo-random generator « For this 3 sheets of drawings