DD143991A1 - CIRCUIT ARRANGEMENT FOR AN INPUT INVERTER IN INTEGRATED MIS TECHNOLOGY - Google Patents

Abstract

The invention relates to a circuit arrangement for a TTL-compatible input inverter in integrated MiS technology It serves to couple digital integrated circuits outside of this TTL circuits. The aim of the invention is to improve the properties of a Improve MIS input inverter for TTL-compatible use. The object of the invention is in it, a good signal to noise ratio, a low power consumption and a high input resistance create. According to the invention the object is achieved in that the switching threshold of the inverter by a biasing transistor disposed between a switching transistor and reference potential is raised. The circuit consists of one input! nverterstufe with a Load and a switching transistor, from a power feed stage with series-connected load and Switching transistor and from a voltage applied to the reference potential bias transistor. The Power is supplied via the power feed stage. The operating voltage can be simple as well be present twice, wherein the one operating voltage can be clocked. The cleaning arrangement is applicable to integrated MLS circuits that are to be TTL compatible. - Fig.1 -

Description

with the invention

Circuit arrangement for an input inverter in integrated MIS technology

Field of application of the invention

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Pie invention relates to a circuit arrangement of an input inverter with Peldeffekttransistoren (J ¹ ET) in integrated MIS technology · ·

Inverters perform the punctuation of converting a logical 1 to a logical 0 and vice versa and represent essential puncturing units of digital integrated circuit arrangements. As a specific variant, MIS input inverters can be used as TTL-compatible input stages Digital circuitry of other logic located outside the integrated circuit, for example, STI ^ Circuitry _#

It is known one inverter basic circuit _? (D _{e s} Hsnkel the application of MOSTs in integrated digital circuits! Radio, Pernsehen _s elektronikj 18, 1969., Heft 3

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Page 74 -? 6) j constructed with Verarmuags-PETs as a switching transistor and load element »he beeteht from the series connection of the drain-source bridge of two'PETs which are arranged between Bezugspo.tential _f, for example, mass _s and operating voltage _e lter input of Inverter is at the gate of the switching EET ₉ whose source is at reference potential «. The drain is connected to the source of the load PET whose drain is connected to the operating voltage. The gate terminal of the load PET is also connected to the operating voltage, but may also be applied to the source to operate on the load transistor. The exterior of the Xnvertera is based on the drain-source connection of the two PESs «

The disadvantage of this circuit arrangement with regard to use as a TTL-compliant input stage is that a threshold voltage must be selected for the switching PETs of the integrated UCS circuit which must be less than the TTL level lift. * This has an effect the switching speed at low operating voltages is negative. Furthermore, the topology of both PETs is different, since the Sehalt-PET has to be dimensioned much larger in length and width than the load-PET. The achievable signal-to-noise ratio is In addition, because of the threshold voltage of the load FES very low

A © more Stfhaltungsanordnung (DE-AS 2 053 E 03 K / 19/08) shows an inverter having an aue a EET data input transistor formed and connected with this in series circuit of a IiSSt trans is tors and © ines Synchronisationstraneistors., Consisting of PETs with isolated control electrode * The rate of the load transistor is connected to a DC voltage and that of the synchronization transistor, a

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The disadvantage of this circuit arrangement is similar to that of the basic inverter circuit, that is, the threshold voltage of the data input transistor must be smaller than the TTL level and a relatively high technological or topological effort is required.

It is also a circuit arrangement of an inverter known (DE-OS 2,524,001? H 03 K / 5/00), the © © makes a level Tifandlung between the usual in !!! circuits and signal levels produced in MOS technology Schaltkreßen * Die Schaltungsanordnung shows an input stage consisting of a load transistor and two input stages downstream of this input stage, each realized with two transistors, the first inverter stage driving the second inverter stage. The input stage, consisting of a PET, is connected to a positive potential of + 5VoIt The following inverter stages Bind are connected to another supply line carrying a negative potential of typically -24 volts or -15 volts commonly used for MOS circuits. The second inverter stage is used for decoupling and for representing a negation. The switching threshold of the driver transistor of the first inverter stage is set so that the inverter switches with TTL leveling. At the output of the first inverter »stage then the full MOS level is available, which controls the second'Invertererstufe« Here is the Source AnscliluB the Singangsstufea-FET with. its input and the gate of the first FET of the first inverter stage and the drain terminal connected to the first supply line (-1-5 volts) "drain" connections of the first PETs of both inverter stages

lie on reference potential '(! Hasse), while the source connections are connected to the negative potential »The gate of the first PET of the second inverter stage is connected to the drain« = source «connection of the first inverter stage ® At the drain« = Source «> The output of the second inverter stage is connected. The second PETs of both inverter stages work as load transistors. The substrate connections of all FETs are connected to the first supply line. ^f (+5 volts) connected »

The disadvantages of this circuit arrangement are _s that the output of the circuit arrangement of the MOS-level swing but not besogen to the auxiliary voltage 0 toit ₉ to] substrate voltage +5 YoIt supplies * This resultierjfcj that the use of this circuit as a "speed stage ^ integrated MIS Schaltkreiseη In addition, an increased technological effort in the integration of this arrangement can be achieved by a threshold voltage to be set especially for the transistor transistor of the first inverter stage by means of an additional exposure and etching process. The dependence on the resulting substrate bias has a negative effect on the Tolerance behavior of the circuit arrangement ©

Object of the invention

The aim of the invention is to improve the properties of an MIS input inverter for TTL-compatible use.

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It is an object of the invention to provide a circuit arrangement for a TTL-compatible input inverter in integrated MIS technology, which has a good signal to noise ratio, a low power consumption and a high input resistance. To increase the stability, the switching point must be set between the maximum and minimum levels applied to the input «

According to the invention, the object is achieved by a circuit arrangement for an inverter in integrated MIS technology, which allows use as TTL-compatible input * stage, achievedj that the switching threshold of an inverter is raised by a transistor arranged between a first switching transistor and a reference potential «

The inventive solution is based on an inverter stage, consisting of a first switching transistor and a first load transistor, which is connected to a current injection stage consisting of a second Sehalttransistor and a second load transistor _s and a bias transistor, wherein the power supply via this Stromeinspeisungsstufe « In this case, the input of the circuit arrangement at the gate of the first switching transistor ₈ whose drain is connected to the source of the first load transistor _$ and to the gate of the second switching transistor and forms the outside of the circuit arrangement. The gate terminals of the first and second load transistors are connected to one of the two operating voltages, while the drain terminals of the two load transistors and the gate terminal of the drain transistor are at the other operating voltage. The source terminal of the second load transistor is connected to the drain of the second transistor Switching transistor connected »whose source

Closure at the source "° Drsi &" = connection of the Yprspan = nuagstransistors and the first switching transistor connected, _{f is connected} while the source of the Yorspannungs «transistor to the Bszugspotential (+5 YoIt bzw. * positive operating voltage TTIi) is«

Is located at the input of the inverter stage a K "" P © gel level) sn ₉ so is the first Sehalttransistor locked "The time required for the Yorspannungstransistor G ₃ te" voltage is secure in ale Stroaeinspeisungsstufe, as is the gate terminal of the second switching transistor to the output inverter stage connected eats and has an L level *

If at the input of the inverter stage there is an L P gel (TTL = P egei), then the ground switching transistor is conducting. Since the second switching transistor is simultaneously blocked, the current is applied via the inverter stage and the drain-source path of the transistor. Flube M output is liull level "" the connection of the output of the inverter stage to the gate of sweiten switching transistor, via whose source terminal of the current in the drain ~ source "path of Yorspannungstransistora arrives _s causes the space required for the raising of the switching threshold © voltage drops

It is aweckmäßigj all PET ¹ S of the same conductivity type herzuetellea _? where the switching transients in each enrichment-type pail and the load transistors and the bias transistor in a given enhancement-type circuit variant are _e . *.

Furthermore, it is expedient to connect the terminal connections of the load transistors to the source terminals of the load transistors, these and the Yorspan

mingstransistor made of the veranaungetyp «

It is furthermore expedient that, in addition to the variant with 2WGi different operating voltages, the circuit arrangement is operated with an operating voltage. Then, the gate and drain terminals of the load transistor and the gate terminal of the preamplification transistor are set to this operating voltage.

It is also expedient to apply the gate terminals of the load transistors and of the biasing transistor to a first operating voltage TL and the drain terminals of the load transistor to a second operating voltage Up.

Finally, it is expedient that the operating voltage I) U is clocked in order to reduce the power consumption. The advantages of this circuit arrangement of an input inverter are an increased stability of the switching threshold j and the controllability of the power supply in a reduced power consumption and in an improved SNR "

An embodiment of the invention will be explained in more detail with reference to the attached drawing

1 i the circuit order of an input inverter,

2: the transient curve of the circuit arrangement,

The Bingangsinverter after Pig _e 1 consists of an Inverterstufθ with eiiaem first load transistor 2 uad a first switching transistor 3 "a current"

Infeedungsstufe 11 with a second load transistor 4 and a second Sohalttransistor 5 and a bias transistor 6, an input 1 and an output 7 «

The input 1 of the circuit arrangement is connected to the gate of the first switching transistor 3 whose drain is connected to the source of the first load transistor 2, to the gate of the second Sehalt transistor 5 and to the output 7 of the circuit arrangement Sotirceanschlüsse of the first switching transistor 3 and the second Sehalttransietors 5 are common to the drain of the Yorspannungstransistors 6, whose source terminal is connected to a reference potential 9j, for example ground. The drain of the second switching transistor 5 is connected to the source of the second load transistor 4. The drain terminals of the first transistor 2 and of the second transistor 4 and the gate of the transistor 6 are connected to an operating voltage Ug ₉ Gate terminals of the load transistors 2, 4 connected to a further operating voltage IL · «

The current is supplied through the connected in Heihe transistors 4 and 5 of Stromeinspei "sungsstufe 11", the control of the second switching transistor 5 via its Gatenneohluß _e Dar first switching transistor 3 is gesperrtg if at A = · gear 1 H-Fegel '- (STL Level) and thus am.Ausgang 7 L »Level ₀ This L» level causes an open z z <eiten the switching transistor 5 and allows a power supply via the Drsin «source ~ distance of the biasing transistor 6 _β This occurs via the biasing transistor 6 a voltage drop, the one. Raising the switching threshold & © s input in · »vertsrs causes«

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Changes at input 1 the potential of TTL level. TTL-L level, so the first switching transistor 3 is turned on and the power supply is interrupted © Dar voltage drop across the bias transistor 6 is thereby kept constant even at the switching moment by the load transistors 2, 4 and the switching transistors 3 »5 a suitable Bimensionlerung on« wsisen »·

The connection of the gate terminal of the biasing transistor 6 with the operating voltage Up has. a regulating effect on the shifting of the switching threshold due to the resulting threshold voltage drift »The current consumption is considerably lower in relation to other solutions of the same dynamic behavior«

The shift of the switching threshold by addition of the generated bias voltage to the center of critical H and I level of the TTL drive enables a partial pear formation of the switching curve of the input inverter and thus results in an improvement of the stability conditions of the arrangement.

Claims (1)

10 - £ IJ \ l & 1β Circuit arrangement for a TTL-compatible integrated-circuit MIS transistor with field-effect transistors (FSTs) ₅ consisting of an inverter stage, a bias transistor and a current injection stage, characterized in that the current is supplied via the current feed stage (11), whose load transistor is the second load transistor (4) the circuit arrangement and its switching transistor, the second switching transistor (5) of the circuit arrangement are connected in series, that the input (1) at the gate «ArjischluB a first switching transistor (3), whose drain is connected to the source of a first load transistor (2) , further connected to the gate the second switching transistor (5) and to the output (7) of the circuit _s that the sources of the first switching transistor (3) and the second Sehaltträn «Bistors (5) together at the drain of Torspan« » Aungstransistors (6) abut, whose source at Bszugspotential (9) and the gate a n a second operating voltage (U ₀ ) is connected, that "at the sweiten'Betriebsspannung (U2) also -Brainaaschlüsse the first load transistor (2) and the second load transistor (4) and that at a first operating voltage (U ^) di © Gate connections of the two load transis gates η (2, 4) arig © locks are closed » Z ₉ circuit arrangement according to item 1, characterized in that all 'transistors (I ¹ ETs) are made of the same conductivity, wherein the switching transistors (3 _S 5) in the case of the enrichment type and the load transistors (2, 4) and the Yorspannungstransistor (6) are at a certain circuit variant of the enrichment * = type «, · 3e circuit arrangement according to item 1 and 2 »characterized in that the circuit arrangement with only one operating voltage (8) is operated5 with the gate and the drain terminals of the load transistors (2 _? 4) and the Qatean« conclusion of Vorspanmmgstransistors (6) on this operating voltage (8) are laid «, 4-e _t circuitry according to item 1 and 2, characterized in ₅ that the Gateaaschlüsse the L-asttranoistoron (2, 4 X) nit are connected to their own source terminals " Circuit arrangement according to items 2 and 4, characterized in that the load transistors (2 ₉ 4) and the voltage transistor (6) are of the depletion type « Circuit arrangement according to items 1 and 2, characterized in that the gate terminals of the Laittrarisistoren (2 ,. 4) and the Vorspannungstraneistors (6) to eiae operating voltage (IL ·) and the Drainanschlüseie aar load transistors (2, 4) the second operating voltage (^ are ·. Circuit arrangement according to point 1, 3 »4 and 6 characterized in that the first © operating voltage (U ^) is clocked«, 1 page drawings