DD143186A1 - CIRCUIT ARRANGEMENT FOR DIGITAL KEYBOARD INQUIRY - Google Patents

Abstract

The invention relates to electronic keyboards, as used for example in devices of data technology. The aim of the invention is to provide a circuit arrangement for digital keyboard interrogation, which can recognize a Mehrfachbetaetigung and uses the key elements with two active outputs. The object of the invention is to provide a circuit arrangement for digital keypad in which the Tastenbetaetigung a recognizing signal does not immediately cause the release of the information signal, no 90 degrees out of phase clock is generated and are not connected to the column or on the row lines multiplexer and / or encoded information. The invention is characterized in that on each row and column lines in each case a NAND gate is connected, each of which is connected to an output line of the decoder controlled by the clock and decoder, wherein the output signals of the counter are used simultaneously as output signals of the circuit and that the output signals of the NAND gates are combined and the validity of a key operation is determined via a control device. Preferred field of application of the invention are devices of data technology.

Description

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Title of the invention

Circuit arrangement for digital keyboard query

Field of application of the invention

The invention relates to electronic keyboards, such as those used in data technology devices «

Characteristic of the known technical solutions

Circuit arrangements for keyboard scanning are known in various variants.

For example, US Pat. No. 3,662,378 describes circuitry with a continuously generated code generated by a continuously counting binary coded decimal counter, providing a desired code and having a plurality of outputs consisting of the following details:

a) a multivibrator with a clock frequency of 25ΟΟ Hz .... 3j5 IviHz, which is divided by an inverter and a plurality of flip-flops to provide a 2-phase clock whose phases are shifted by 90 ° and adapted so that found a code and a change in the above Binary counter can be blocked

b) decoding means for continuously sampling some of a plurality of outputs of said binary counter to produce a change in each one

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its output leads for any combination of binary inputs,

c) multiplexing means continuously sampling certain other of said plurality of outputs of the binary counter,

d) code switch in the circuit for establishing a conduction path between said multiplexing means and said decoder means and

e) a gate in said circuit through which clock pulses from said multivibrator pass until one of said code switches is closed, establishing a conductive path between said decoder means and said multiplexing means to provide input to said gate which receives the clock pulses thereto prevents further activation of the named binary counter.

The disadvantage of this solution is that a multiple operation can not be detected and that no key elements with 2 active outputs can be used.

In DE-PS 24 09 170, an information input device is described, in which the row and column lines of a matrix can be selectively connected to one another by actuating pushbuttons; with a first counter driven by clock pulses for its cyclic further counting, which gives its counter output corresponding output signals to the associated row line of the matrix, and with a second counter 5 connected in series with the first counter for its cyclic further counting, characterized by a first one circuit coupled to the column lines for forming a synchronization signal upon receipt of a first output signal from the first counter via row and column lines connected by actuated input keys and a second output signal from the second counter and a second circuit for forming a coded information signal

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upon receipt of the synchronization signal and the counts indicating the counts of the first and second counters. Eei this solution is disadvantageous that no key elements with two active outputs can be used and that the switching ungstechnishe effort is high.

Object of the invention

The aim of the invention is to provide a digital keypad sensing circuit which can recognize a multiple operation and uses the key elements with two active outputs.

Explanation of the essence of the invention

The object of the invention is to provide a circuit arrangement for digital keyboard query, in the

the signal recognizing a key operation does not immediately cause the release of the information signal,

no 90-phase clock is generated and

- Are not connected to the column or on the row lines multiplexer and / or encoded information is supplied.

According to the invention the object is achieved in that a Schalt.anOrdnung consists of a clock generator, a counter, decoding means and a control device that are arranged in the intersections of the matrix key elements with two active outputs that all line and column lines in each case a NAND Member is connected,

these NAND gates are each connected to an output line of the counter and the clock-controlled decoding device, the output signals of the counter being simultaneously used as output signals of the circuit arrangement, *

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the output signals of the NAND gates are combined and a sum line signal bzv /. form a negated sum line signal,

that these sum line signals or the negated sum line signal are applied to the control device such that a first output signal of the control device and the clock are connected to inputs of an AND gate whose output is connected to a control input of the counter,

in that a second output signal of the control device is connected to an input of the decoder device and that a release signal is provided.

AusfuhrungsbeispieI

The invention will be explained in more detail with reference to an embodiment

 It shows the

Figure 1: The schematic diagram of the circuit according to the invention for digital keyboard query.

The keypad itself consists of active key elements 1 arranged in a matrix, which when actuated output a "V signal in one column and one row." A valid key actuation is present when exactly one key element 1 is actuated and the state of the counter This is achieved by the circuit arrangement described below All column and row lines are connected to one NAND gate 6 each.

A counter 3, which is controlled by the output signal of a first MD element 7, is connected by 2 lines each with a first demultiplexer D1 and a second demultiplexer D2 of a decoding device 4-. In this case, the control input Cg ^ of the first demultiplexer D1 connected to the clock generator 2 The 3 output lines of the first De codier D1 are each with a row lines associated NAND gate 6 and the 3 output lines of the

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second decoder D2 are each connected to a NAND gate 6 associated with the column lines. The outputs of the NAND gates 6 are combined to form a sum line signal S 'or a negated sum line signal H ¹ and fed as input signals to a control device 3 .

The core of the control device 5 are a first and a second flip-flop EP1 and FF2. The second flip-flop FF2 receives the clock directly from the clock generator 2, while the first flip-flop FF1 receives the clock negated by a first inverter 8. The sum line signal S ¹ is supplied to the first input D of the first flip-flop FF1 whose first output (JT ⁾ is supplied with a second one AND gate 11, which in turn receives another input from the first output Q2 "of the second flip-flop FF2 and outputs the enable signal STROBE, the second output Q1 of the first flip-flop FF1 and the first output Q2 of the second flip-flop FF2 a NAND gate 9 is supplied, whose output 12 is connected to the second input S of the first flip-flop FF1 and the second inverter 10. At the output of the second inverter 10, the second Ausgangssi.gnal A2 of the control device 5 is formed and the control input C ^ from the second output Q2 of the second flip-flop FF2, the first output signal A1 is the control unit tion 3 and given together with the clock on the first UID-element 7.

The negated Summenle itungsungs signal S "'is supplied to both inputs D' and R of the second flip-flop FF2" The outputs of the counter 3 are connected except to the decoder 4 with outputs ao ,, ₀ on the circuit to provide the valid key code there ,

For the operation of the circuit arrangement according to the invention 2 phases are characteristic:

1st phase:

The outputs of the counter 3 give their signals to the decoder 4 ₃ here from two Demu.ltiplexern

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Di and D2 exist. In this case D1 is assigned to the row lines of the keyboard query matrix and D2 to the column lines.

Due to the function of each has an output of the demultiplexer D1 and D2 a line the state "0". Thus, one row and one column are respectively masked via a respectively assigned NAND element in accordance with the counter reading. ,

If only one key element 1 is actuated, the sum line signal S ^f , which is formed by the sum of the outputs of the NAND gates 6, becomes S ¹ = "0 '* if and only if the associated row and the associated column are masked.

In this case, the state of the counter 3 corresponds to the code assigned to the key element i.

If more than 1 key element 1 is actuated, at least two columns and two lines are simultaneously "1". Thus, the sum line signal S ¹ can not assume the value "0" and a multiple operation is detected.

2nd phase:

The masking of the row and column lines is canceled. Thus, the negated sum line signal S ¹ to "1" when at least 1 key element 1 is actuated. Here, therefore, it is only recognized whether a key element 1 is actuated at all, irrespective of the number of actuated key elements 1. For the static formation of the release signal "STROBE", which indicates a valid key element actuation, the values of the sum line signals S ^! S * 'are stored in both the first and in the second phase, serve two D-flip-flops, the clock-controlled at the end of each phase take over the information. Prerequisite for the operation of the circuit arrangement according to the invention is in the illustrated embodiment that the counter 3 and the flip-flops 1 and 2 respond to the "o" - "L ^u edge of the clock input.

Specifically, the following signaling processes occur during these 2 phases:

1st phase:

With the clock provided by the clock generator 2 to logic "0", including the ^u O "- ^u L ^t 'edge, both demultiplexers D1 and D2 of the decoder 4 are switched on.

The sum line signal is ^f assumes the logic state for a correctly recognized key element actuation (S '= "0") or for an unrecognized or multiple key actuation (S' = "1").

With the ⁿ 0 "-" L "edge, a" 1 "information is taken over into the flip-flop FF 2, and a counting step is carried out at A1 =" 1. "When S ⁷ =" 0 ", this information immediately becomes the R-Bingang on the flip-flop FF2 v / effectively, to prevent that with correct counter position and the first output signal A1 = "1" of the control device 5 »a count can occur by the switching time of the flip-flop FF2.

2 «Phase:

With the clock provided by the clock generator 2 at logic "L", including the "L" - "O ⁿ -flank, the signal S '= ^M 0" is established at the signal line S' at least one actuated key element. With the edge ^L * L "- ' ^f 0 ^f » of the clock, the information is written into a first flip-flop FF1.

In order to prevent a faulty enable signal STROBE, when a key element 1 is pressed during the phase 2, which has not yet been detected, but the first output signal A1 is still logic "0", since the first phase is not yet passed, can in the first Flip-flop FF1 only at Al = "1" a ⁿ 0 ^u are written. Thus, it is necessary that when a key element 1 is actuated from the Gi 'and ζ us t and that means no key

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element 1. actuated, in any case, a signal at the second output Q2 of the second Plipflops ΈΈ2 arises, even if the correct count was reached by chance. This is achieved by switching off the demultiplexer D2 by means of the second output signal A2 of the control device 5

Claims (1)

1300 3 invention claim 1. Circuit arrangement for digital keyboard query for arbitrarily large matrix-like arranged key elements (1) consisting of a clock generator (2), a counter (3)> decoding (4) and a control device (5), characterized in that key elements in the intersections of the matrix (1) are arranged with two active outputs, that in each row and column lines in each case a first NAND gate (6) is connected, that this first NAND gate (6) each with an output line from the counter (3) and the Clock controlled decoding device (4) is linked, wherein the output signals of the counter (3) are also connected to an output (ao ... to) of the circuit arrangement that the output signals from the NAND gates (6) are combined and a sum line signal (S ') or a negated sum line signal (S ⁷ ") form, that this sum line signal (S ¹ ) or the negated sum line signal (ß ¹ ") to the control device (5) be placed, in that a first output signal (A1) of the control device (5) and the clock signal are connected to inputs of an AND element (7) whose output is connected to a control input of the counter (3), -10- 2130-03 in that a second output signal (A2) of the control device (5) is connected to an input of the decoding device (4) and in that a release signal (STROBE) is provided. Circuit arrangement for digital keypad inquiry according to item 1, characterized the clock in the control device (5) is applied once via a first inverter (8) to a first flip-flop (5 ¹ FI) and once directly to a second flip-flop (PF 2), in that the sum line signal (S ') is applied to a first input (D) of the first flip-flop (5 ¹ F1), in that the first flip-flop (FF1) has a first output (QT) and a second output (Q1) first output (QI) of the first flip-flop (FF1) is connected to a second AND gate (11) and the second output (Q1) of the first flip-flop (FF1) is connected to a NAND (9), that the second flip-flop ( FF2) receives the negated sum line signal '(S ¹ ') at a first input D * and a second input R, and has a first output (Q2) and a second output (Q2) that is connected to the second output (Q2) of the second flip-flop (Q2). FF2) the first output signal (A1) is formed and the first output (Q2 ~) of the second flip-flop (FE2) is connected to the second AND gate (11) and the NAND (9), that an output (12) of the NAND (9) is applied to a second input (S) of the first flip-flop (FF1) and to a second inverter (10), that this second inverter (10) supplies the second output signal (A2) and that the second UlTD member (11) provides the enable signal (STROBE). For this 1 page drawings