CZ307283B6 - Connection of a time delay generator - Google Patents

Abstract

Connection of a time delay generator in the field of pulse generators, which initiates the running of the first synchronous high speed binary counter (10) MC100E016 of the lower 8 bits and the second synchronous high speed binary counter (15) MC100E016 of the upper 8 bits by means of the R-S flip-flop circuit (29) and which uses a microstrip line (2, 4, 19, 22, 24, 27, 31, 33, 35, 37 and 39) with a known impedance of, for example, 100 Q on all critical joints of logic circuits and which are provided by adjusting (3, 5, 20, 23, 25, 28, 32, 34, 36, 38 and 40) having the same impedance as the microstrip lines (in this case 100 Ω again).

Description

Technical field

The invention relates to the connection of a time delay generator triggering a counter run by means of a flip-flop RS circuit.

BACKGROUND OF THE INVENTION

OTDR (Optical Time Domain Reflectometer) is an instrument for testing and measuring the attenuation of optical paths. The reflectometer uses a backscatter method, which is an indirect and non-destructive method based on the measurement of Rayleigh scattering, which contributes to the overall attenuation of the optical fiber. The method is based on the detection of backscattered optical pulses transmitted by the measuring instrument to the optical path. A pulse mode OTDR reflector emits a sequence of short optical pulses of approximately several hundred nanoseconds to several tens of microseconds. Due to Rayleigh scattering in the inhomogeneities in the core and due to back reflections on the connectors, part of the optical power is reflected back to the beginning of the connected path. Evaluation of backscattered radiation enables accurate estimation of attenuation properties of the measured path. The measured effect is thus the power level of the backscattered radiation as a function of the time of propagation of the pulses to the point of reflection and back.

The determination of the time position of the transmitted optical pulse and the reflected optical signal is performed by the OTDR time delay generator. The time delay generator operates such that when the optical signal source is activated, the countdown of the set time interval is triggered and the counter is waited to reset the reflected optical signal size.

However, the counting in the reflectometer circuits, whether metallic or optical lines, is excluded by the clock rate of the reading and the length of the time step to be distinguished. Usually, this is a clock speed in hundreds of MHz and a time step in nanoseconds.

U.S. Pat. No. 8,508,747 A discloses a system and method for executing trigger signals in optical reflectometers wherein, according to one embodiment, the OTDR system uses a laser beam to produce a reference signal. This signal is passed through a 4 x 4 optical coupler that splits the signal into a first signal and a second signal by phase shift. These signals are converted into electrical signals and the trigger unit generates trigger pulses at those times in which the electrical signals pass through zero.

It also uses integrated circuits, specifically logic circuits in ECL technology. Among other things, the ON Semiconductor MC100E016 integrated counter of 8 bit width is available. The typical clock speed of the circuit is 900 MHz, which is convenient for most applications. However, the problem arises if it is necessary to increase the number of bits to 16, or. even more. Then there is nothing else to do but concatenate the counters. However, the clock speed suffers. The information in the datasheet shows that when the output bits are increased to 16, the maximum clock speed is 625 MHz, at a further increase it drops to only 500 MHz.

An optical testing device for detecting and monitoring losses and / or failures in optical fibers is described in the international application WO 9112509. The optical testing device comprises an optical meter of the optical time domain of light pulses into the test fiber. The apparatus further includes an optical amplifier that is arranged in the light path between the optical optical time field meter and the test fiber for amplifying light pulses. The optical switch is located in the light path between the amplifier and the test fiber to prevent unwanted illumination of the test fiber. The time resources are arranged for synchronization

The optical switch so that the switch opens when the light pulse enters the switch and closes the switch as soon as the light exits the optical switch.

An optical time-dependent reflection system (OTDR) that incorporates a new pulse source is disclosed in U.S. Patent Application No. 5,033,826 A. The system comprises an oscillator, phase converter, amplifier, optical pulse generator, integrated electro-optical circuit, detector, timer, converter and output. equipment. The OTDR system can be used to determine which surface of a photo lens impairs light transmittance the most. When the amplifier is activated, the oscillator signal triggers the timer and pulse generator. The timer is designed as a time digital circuit with analog interpolation. The resulting pulse is transmitted via an integrated electro-optical circuit to the evaluation lens. When reflection from the lens with the highest intensity occurs, the resulting detection signal stops the timer. The result is displayed and / or stored on the output device. The optical pulse transmitted along the optical path of the integrated electro-optical circuit is phase shifted. The phase slider is programmed so that this phase distortion is approximately quadratic for the duration of the pulse, so that the pulse frequency is linearly attenuated. The integrated electro-optical circuit includes a dispersion grid which introduces a time delay as a function of frequency. The combination of dimming and scattering the light pulse results in the resulting pulse being compressed compared to its original form. Compressed pulse allows more accurate surface identification.

An OTDR system that is used in an optical fiber network to control optical fiber damage is described in European patent application EP 0 605 301. The control circuit generates a pulse current based on an electrical pulse from the timer. The light source emits a light pulse that passes into the optical fiber through the optical waveguide directional coupler and then passes to the measuring optical fiber. The delay circuit slows the digital control portions to gain the time needed for the light pulse to go back and forth in the optical fiber.

In Japanese Patent Application JP H03282344 A, a simple construction OTDR system is described. The system modifies the optical pulse to reduce the pulse width. The OTDR design includes a control unit, oscillator, phase converter, amplifier, optical pulse generator, integrated electro-optical circuit (IEOC), detector, timer, converter, and output unit, ie, display or memory. The IEOC includes a substrate, an input optical path, a dispersion grid, an output optical path, a first electrode, and a second electrode. The electrodes have parallel longitudinal segments and the current passing through these segments generates a field passing through the optical path. The field induces phase distortion in the optical pulse and its shorter width allows the weight and size of the OTDR structure to be reduced as well as its accuracy.

The disadvantage of the prior art lies in the following:

The first device uses an optical fiber to achieve short time intervals. The time constant of this device is given by the length of the optical fiber and cannot be changed operatively. In addition, optical fiber of a given length is not suitable for miniaturization and integration.

The disadvantage of the devices using the produced integrated circuits and their connection according to the datasheets lies mainly in the fact that these devices use in their circuits transmission paths of unknown impedance without the necessary adjustment, which ultimately leads to distortion of the signal shape and decrease of maximum transmission and clock speed.

It is an object of the present invention to design a time delay generator of an optical reflectometer that allows the shortest time step to be achieved, which results from the highest clock speed.

SUMMARY OF THE INVENTION

The above object is achieved by engaging a time delay generator, which consists of an integrated circuit comprising a clock signal input coupled via a first

-2GB 307283 B6 Microstrip line to CLK input of first synchronous high-speed binary counter 8 bits and second microstrip line to CLK input of second synchronous high-speed binary counter 8 bits and further comprising data input for lower 8 bit reading connected by first standard line to first TTL converter / ECL which is connected via a second standard line to the input of the first synchronous high-speed binary counter of 8 bits and further comprising an input for reading the upper 8 bits connected by a third standard line to the second TTL / ECL converter connected by the fourth standard line to the second synchronous input a high-speed binary counter of the upper 8 bits, wherein the first synchronous high-speed binary counter of the lower 8 bits is connected via the output TC via the ninth microstrip line to the CE input of the second synchronous a high-speed binary upper 8-bit counter and via a tenth microstrip to logic-sum gate D1 and a second synchronous high-speed binary counter 8-bit is connected via TC output via an 11th microstrip line to logic-sum gate D2 input a microstrip line to the counter termination output and a trigger signal input is connected by a fifth standard line to a third TTL / ECL converter, which is further connected by a third microstrip line to the trigger signal output, which has the third TTL / ECL converter connected by a fourth through the microstrip line to the flip-flop input S and the logic sum gate is connected via output Q via a sixth microstrip line to the R flip-flop input RS, which is connected via the output Q through the seventh microstrip to the PE input of the first synchronous high-speed binary counter of the lower 8 bits and via the eighth microstrip line to the PE input of the second synchronous high-speed binary counter of the upper 8 bits.

SUMMARY OF THE INVENTION The invention is based on a time delay generator which triggers a counter flip-flop RS circuit and uses a known impedance microstrip line (eg 100 Ω) on all critical logic circuit connections with the same impedance matching as the microstrip line in this case again 100 Ω). Preferably, the adaptation is in the form of a Thevenin divider.

To achieve the rising and falling edges of the signal in the order of hundreds of picoseconds of the OTDR timing circuit, microstrip lines and appropriate adjustments must be used. Not standard 50 Ω microstrip lines are used, but 100 Ω microstrip lines are used. Signal integrity is maintained at much smaller path widths of the microstrip lines. For a 100Ω microstrip line, a FR4 substrate, and a substrate thickness of 1.5 mm, the path width of the microstrip line is 0.6 mm. If a 1 mm thick FR4 substrate is used, only 0.4 mm of line width can be achieved, which fully meets the lead widths of modern integrated circuits.

The basic difference from the state of the art is the addition of an R-S flip-flop circuit that starts and stops counting, functional microstrip lines of known impedance, and appropriate adaptations of these lines.

Clarification of the drawing

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be explained in more detail with reference to the drawing, in which Fig. 1 shows a circuit diagram of a time delay generator triggering a counter run by a flip-flop R-S circuit.

DETAILED DESCRIPTION OF THE INVENTION

The principle of the connection of the time delay generator will be illustrated by the exemplary embodiment described below.

-3 CZ 307283 B6

The wiring of the counter time-delay generator by the flip-flop RS circuit is shown in Fig. 1. The wiring in this embodiment comprises a clock signal input 1 connected through the first microstrip line 2 to the CLK input of the first synchronous high speed binary counter 10 lower 8 bits MC100E016 and the second microstrip line 4 to the CLK input of the second synchronous high speed binary counter 15 of the upper 8 bits of the MC100E016 type. And further comprises a data input 6 for reading the lower 8 bits that is connected by the first standard line 7 to the first TTL / ECL converter 8, which is further connected via the second standard line 9 to the input of the first synchronous high-speed binary counter 10 lower 8 bits type MC100E016. It further comprises an input 11 for reading the upper 8 bits which is connected by a third standard line 12 to the second TTL / ECL converter 13 which is connected by the fourth standard line 14 to the input of the second synchronous high-speed binary counter 15 of the upper 8 bits type MC100E016. The high-speed binary counter of the lower 8 bits of the MC100E016 type is connected via the TC output via a ninth microstrip line 35 provided with a ninth adaptation 36 to the CE input of the second synchronous high-speed binary counter 15 upper 8 bits of the MC100E016 type and through the tenth microstrip the line 37 provided with the tenth adaptation 38 to the input D1 of the logic sum of the gate 30 is realized by the MC100EL01 circuit, the second synchronous high-speed binary counter 15 of the upper 8 bits of MC100E016 is connected via the TC output via an eleventh microstrip line 39 to the input D2 of the logic sum of the MC100EL01 type circuit 30, which is connected via the output Q to the fifth microstrip line 24 provided with the fifth adaptation 25, to the output 26 of the counter run termination. The circuit further comprises a trigger signal input 16 which is connected by a fifth standard line 17 to a third TTL / ECL converter 18, which is further connected by a microstrip third line 19, provided with a third adaptation 20 to the trigger signal output 21, the third TTL converter 18. The ECL is connected by a microstrip fourth line 22 provided with a fourth adaptation 23 to the input S of the flip-flop 29 RS, realized by the MC10H131 circuit, the logic summing gate 30 via an output Q connected via a microstrip sixth line 27 which is provided with the sixth adaptation 28. to the input R of the flip-flop 29 RS connected via the output Q, on the one hand through the seventh microstrip line 31 provided with the seventh adaptation 32, on the PE input of the first synchronous high-speed binary counter 10 lower 8 bits MC100E016; 33, which is provided with an eighth adaptation 34, to the PE input of the second synchronous high-speed binary counter 15 of the upper 8 bits of the MC100E016 type.

The function of the time delay generator triggering the counter run by the flip-flop R-S circuit is as follows. Lower 8 bits are input through block 6, and upper 8 bits are input through block 11. Data for reading the lower 8 bits is routed from block 6 via standard line 7 to the input of the first TTL / ECL level converter 8. Further, the data continues through standard lines 9 to input the first synchronous high-speed binary counter 10 of the lower 8 bits (MC100E016 circuit). While data for reading the upper 8 bits is routed from block 11 via standard line 12 to the input of the second TTL / ECL level converter 13. Further, the data continues through a standard line 14 to input a second synchronous high-speed binary counter 15 of the upper 8 bits (MC100E016 circuits). Input J6 is used to trigger the first and second synchronous high-speed binary counters 10 and 15. This is a TTL level signal that continues through standard line 17 to third TTL / ECL level converter 18. The TTL level signal further equips both the trigger signal output 21 through the third microstrip line 19 and the third adaptation 20, and the flip-flop circuit 29 RS input through the microstrip line 22 and the fourth adaptation 23. This results in a logical level change at the output Q of the flip-flop 29 RS. which equips the Parallel Load Enable (PE) input of the first synchronous high-speed binary counter 10 via the seventh microstrip line 31 and the seventh matching 32, as well as the Parallel Load Enable (PE) input of the second synchronous high-speed binary counter 15 via the eighth microstrip line 33 and the eighth matching 34 Changing the logical level at said PE inputs ensures that the memory cells of the first and second synchronous high-speed binary counters 10 and 15 are transcribed to the values entered by blocks 6 and 11 of the data inputs for reading. From now on, the first synchronous high-speed binary counter 10 and the second synchronous counter

The high-speed binary counter 15 increases its state by a unit according to the clock signal supplied by input 1. The clock signal is distributed by the first microstrip line 2 and the first matching 3 to the first synchronous high-speed binary counter 10 as well as by the second microstrip line. 4 and the second matching 5 to the second synchronous high-speed binary counter 15. The TC (Terminal Count) output signal of the first synchronous high-speed binary counter 10 equips the Count (Enable) input of the second counter 15 via the ninth microstrip 35 and ninth matching 36 as well as the gate input. The logic sum 30 through the tenth microstrip line 37 and the tenth adaptation 38. The output signal TC (Terminal Count) of the second synchronous high-speed binary counter 15 only equips the logic sum gate input 30 via j The 11th microstrip line 39 and the 11th adaptation 40. Overflow of the first and second synchronous high-speed binary counters 10 and 15 produces a common level at the logic sum gate inputs 30. This results in a change in the logic level at the output Q of the logic sum gate 30. This change is distributed to the counter run termination output 26 by means of the fifth microstrip line 24 and the fifth matching 25, as well as the input R of the flip-flop 29 RS by the sixth microstrip line 27 and the sixth matching 28. This completes the count and waits for a new command. trigger signal input 16.

The critical signal paths are implemented as microstrip lines with a precisely defined impedance value. In this case, 100 100 is used. Of course, any other value in the range of 10 Ω to 1 kΩ can be used. The microstrip lines are formed on the FR4 substrate. There are other substrates such as FR2, FR3, FR4, FR6, Teflon and the like. The substrates are provided with a copper strip of defined width on one side and a continuous copper surface on the other. The width of the microstrip line is based on the specific permittivity of the substrate, which may be in the range of 1 to 100, and the thickness of the substrate, which may be in the range of 0.1 to 10 mm, and the selected impedance of the microstrip line. Examples of microstrip line width values are given above. The matching impedance (Thevenin divider) must have the same value as the impedance of the microstrip line.

Industrial applicability

The Time Delay Generator Triggering the Counter with a Flip R-S Circuit finds industrial applicability within the pulse generators, when generating short adjustable time intervals, when generating adjustable time stamps for calibrating devices, etc.

Claims (3)

A time delay generator connection comprising a clock signal input (1) connected via a first microstrip line (2) to a CLK input of a first synchronous high-speed binary counter (10) of the lower 8 bits and a second microstrip line (4) to a CLK input of a second synchronous high-speed binary counter (15) upper 8 bits and further comprising a data input (6) for reading the lower 8 bits connected by a first standard line (7) to a first TTL / ECL converter (8) connected via a second standard line (9) to an input of a first synchronous a high speed binary counter (10) of the lower 8 bits and further comprising an input (11) for reading the upper 8 bits connected by a third standard line (12) to a second TTL / ECL converter (13) connected by a fourth standard line (14) to a synchronous high-speed binary counter (15) of the upper 8 bits, wherein the first sync a high-speed binary counter (10) of the lower 8 bits is connected via a TC output via a ninth microstrip line (35) to the CE input of the second synchronous high-speed binary counter (15) of the upper 8 bits and via a tenth microstrip line (37) to the gate D1 input (30) The second high 8-bit synchronous high-speed binary counter (15) is connected via the TC output via an eleventh microstrip line (39) to the logic summation gate input (D2) (30) which is connected via output Q via a fifth microstrip line. (24) to the counter (26) of the counter run termination and the trigger signal input (16) is connected by a fifth standard line (17) to a third TTL / ECL converter (18) which is further connected by a third microstrip line (19) to output (21). A trigger signal, characterized in that the third TTL / ECL converter (18) is connected by a fourth microstrip line (22) to the input of the RS-latch circuit (29) and the logic sum gate (30) is connected via the output Q via the sixth microstrip line. 27) to the input R of the flip-flop RS, which is connected via the output Q via a seventh microstrip line (31) to the PE input of the first sync a low 8 bits high speed binary counter (10) and through an eight microstrip line (33) to the PE input of a second high 8 binary high speed binary counter (15). The time delay generator circuit according to claim 1, wherein the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh microstrip lines (2, 4, 19, 22, 24, 27). , 31, 33, 35, 37 and 39) are provided with first, second, third, fourth, fifth, sixth seventh, eighth, ninth, tenth and eleventh adjustments (3, 5, 20, 23, 25, 28, 32, 34 , 36, 38 and 40). The time delay generator circuit according to claim 2, characterized in that the microstrip lines (2, 4, 19, 22, 24, 27, 31, 33, 35, 37 and 39) consist of a substrate of known thickness of 0.1 mm to 10 mm. and a specific permittivity in the range of 1 to 100, which is provided on one side with a copper strip of defined width and on the other side with a continuous copper surface.