CZ18271U1 - Modular programmable platform for high-speed hardware processing of packets - Google Patents

Description

The technical solution relates to a modular programmable platform for high-speed hardware packet processing. It belongs to the field of telecommunications technology and services.

BACKGROUND OF THE INVENTION

Today, commercially available hardware packet processing devices for monitoring high-speed computer network lines, generating packets for test purposes, or streaming are represented primarily in two basic forms: either as laboratory devices or as computer cards.

Laboratory instruments are designed for individual, usually short-term experiments primarily with human operation. The devices tend to be bulky, expensive and with limited remote access, for example, using a specialized client application. They are therefore unsuitable for permanent deployment in a computer network, for example to monitor it.

PC Cards consist of hardware and firmware that usually performs a simple function that the user cannot change. If the manufacturer provides more firmware variants, their number is very limited, cannot be extended by user-specified functions, and changing the firmware requires interrupting the device for the time it takes to change the configuration. The processing of packets by means of a card into a computer is almost always only at the monitoring level, that is to say statistics on incoming packets, without the possibility of modification. The interface between hardware and firmware is almost always proprietary and not available to the user. Some systems allow you to upload your own firmware, but it is very complex to create, because it must be created either from scratch or using components with complex and diverse interfaces and demanding time synchronization requirements.

It follows from the above that user-defined hardware packet processing with the possibility of changing the functionality during operation of the device and the possibility of modifying packets is very difficult to implement and deploy to computer networks as part of the infrastructure with the existing technology.

The essence of the technical solution

The above-mentioned shortcomings are overcome by the modular programmable platform for hardware high-speed packet processing according to the present solution. In essence, it consists of at least one universal programmable gate array (FPGA) board interconnected with at least one multiplexer and demultiplexer board for an optical transceiver, the gate array comprising modular firmware for packet stream processing. Packets are processed by at least one sequence of packet streaming modules having all the same input interfaces for receiving packets and control commands and output interfaces for sending packets and control commands. The output interfaces of all but the last packet stream modules are connected to the input interfaces of the next packet stream module. The input interface of the first packet stream processing module is connected via the first module for communication with the high-speed transmission channels to the demultiplexer and subsequently to the receiver part of the optical transceiver. The output interface of the last packet stream processing module is connected via the second module for communication with the high-speed transmission channels to the multiplexer and subsequently to the transmitting portion of the optical transceiver. The programmable gate array board further comprises a control module for configuring packet stream processing modules, the first and second modules for communicating with high speed channels. The device further comprises a module for communicating with peripherals, in particular a serial interface, a flash memory and an Ethernet network interface for remote access. This module is preferably implemented using a Linux universal operating system running on a processor embedded within a programmable gate array, without the need for an external computer. The apparatus further comprises a power supply. The device is built into a standard rack cabinet with the possibility of low height.

The unified interface of the packet processing modules makes it easier to develop new modules, add them and replace them in the sequence of modules through which packets pass. Any module can analyze, modify, remove, or add packets to the network. The modularity of the proposed solution allows for great scalability and high variability. It is possible to create a variety of module types, of which only the modules needed for a particular application can be deployed in a certain number and order inside the device, thus also saving space in the programmable gate array.

The unique configuration of the modules and the choice of their interfaces, with only streaming packet processing, make it possible to realize very complicated high-speed packet processing as well as expansion by other modules regardless of the time characteristics of previous modules, only at the cost of device passage. is fully compliant for monitoring, generating or processing packets. Typical packet pass rates are 1 Gbps, 2.5 Gbps, 10 Gbps, 40 Gbps, or 100 Gbps.

The second and other parallel sequence of packet stream modules can be used either for alternative packet processing that can be changed and switched while the device is running without interrupting its operation and / or for concurrent packet processing to achieve higher throughput by distributing packets between module sequences.

The second and further universal programmable gate array (FPGA) boards can be used to achieve higher throughput by distributing packets between individual boards. The second and subsequent multiplexer and demultiplexer boards for the optical transceiver may be used to increase the number of device ports where each port may act as input, output, or input / output. Packets can be modified as they pass through the device from one port to another.

For devices intended to be deployed in the operating mode to the computer network, the emphasis is on the possibility of remote management. The proposed device enables remote management via serial or Ethernet network interface, which can be used for a number of communication technologies for remote management, especially: telnet, SSH, SNMP, RMON, HTTP or HTTPS.

Implementing a Peripheral Interface Module using a Linux-based universal operating system running on a processor embedded inside a programmable gate array, without the need for an external computer, simplifies device installation and management, reduces costs, and provides great scalability with new remote device communication capabilities.

In one possible preferred embodiment, an optical switch is connected to the optical transceiver of the device, which allows the input and / or output of the transceiver to be switched to multiple optical fibers or optical channels in the fibers.

In another possible embodiment, a packet timing module is attached to the peripheral communication module, allowing each incoming packet to be assigned time information at the time of its arrival, which may be real time or system time.

The power supply may be redundant. In any case, an AC power supply can be used

2 3 0 V or 48 VDC

Overview of the drawings

The essence of the invention is further illustrated in the attached drawing. This is a block diagram of a real device that is currently being tested.

Example of technical solution

The modular programmable platform for hardware high-speed packet processing, whose block diagram is shown in Figure I, can be described by the following functional blocks: universal board I s

Programmable Gate Array (FPGA), multiplexer and demultiplexer board for optical transceiver, packet stream processing modules 3, first module 4 and second module 6 for communication with high speed transmission channels, demultiplexer 5, multiplexer 7, optical transceiver 8, a control module 9 for configuring packet stream modules 3, a first module 4 and a second module 6 for communicating with high-speed channels, a module JO for communicating with peripherals represented here by the RS 232 ϋ serial interface, flash memory 12 and Ethernet 13 , a power supply module 14, an optical switch 15, and a timestamp allocation module 16.

The universal board with programmable gate array (FPGA) is connected to the 2 io multiplexer and demultiplexer board for the optical transceiver. The universal board gate array 1 comprises packet stream processing modules 3, a first module 4 and a second module 6 for communicating with high speed transmission channels, a control module 9 for configuring packet stream modules 3, a first module 4 and a second module 6 for communicating with high speed channels, a module 10 for communicating with peripherals, and a module 16 for assigning time stamps to packets. The output interfaces of all but the last packet streaming modules 3 are connected to the input interface of the next packet streaming module 3. The data portion of the input interface of the first packet streaming module 3 is connected to the first module 4 for communication with high-speed transmission channels, which is further connected to the demultiplexer 5, which is further connected to the receiving part of the optical transceiver 8. the packet stream processing module 3 is connected to a second high-speed transmission channel communication module 6, which is further connected to a multiplexer 7, which in turn is connected to the transmitting portion of the optical transceiver 8. The input interface portion of the first packet streaming module 3 it is connected to a module 10 for communicating with the peripherals. The control portion of the output interface of the last packet stream processing module 3 is connected to the module configuration control module 9. The control module for configuring the packet streaming modules 3, the first module 4 and the second module 6 for communicating with the high-speed channels and the module 10 for communicating with the peripherals are interconnected. Module 10 for communication with peripherals is connected to serial interface RS 232 ϋ, flash memory 12 and network interface Ethernet type 13. Power supply

14 is coupled to both a universal board and a programmable gate array (FPGA) and a multiplexer and demultiplexer board for an optical transceiver. The optical transceiver 8 is coupled to the optical switch 15. The packet timing assignment module 16 is connected to a peripheral communication module. The device is built into a standard rack cabinet with the possibility of low height.

The sequence of modules 3 for packet stream processing is the basis of the whole device. An essential feature of these modules is that they all have the same input interfaces for receiving packets and control commands and an output interfaces for sending packets and control commands, and also arranging the modules 3 for packet stream processing into a clean sequence. This allows for great extensibility and high variability. The proposed solution provides scalability allowing even complex packet processing at high speeds. In addition to the first sequence of packet stream processing modules 3, the device may also include one or more additional parallel sequences of alternative packet processing modules. An essential feature of this arrangement is the possibility of configuring packet streaming modules 3 and switching packet processing between sequences of the packet streaming modules 3 at runtime without interrupting its operation, and the possibility of concurrent packet processing to achieve higher throughput by distributing packets between sequences modules 3 for packet stream processing.

The first module 4 for communication with high speed transmission channels and the second module 6 for communication with high speed transmission channels serve to convert data structure and time characteristics between the packet stream processing modules 3 on the one hand and the demulti50 plexer 5 or multiplexer 7 on the other. The demultiplexer 5 and multiplexer 7 are connected via parallel high-speed channels.

CZ 18271 Ul

The optical transceiver 8 provides a conversion between electrical and optical form of packet transmission in both directions.

In particular, the control module 9 serves to switch on, off, change parameters and to replace the modules 3 for packet stream processing and to change the parameters of the first module 4 and the second module 6 for communication with high-speed channels.

The peripheral communication module 10 allows remote reading of packet processing results, remote control of the entire device and its automatic start when the power is turned on via the RS 232 11 serial interface, the flash memory module 12 and the Ethernet network interface module 13 that can be used. for a variety of remote communication technologies, in particular: telnet, SSH, SNMP, RMON, HTTP or HTTPS. The peripheral communication module 10 is preferably implemented using a Linux universal operating system running on a processor embedded within a programmable gate array on a universal board and with a programmable gate array, without the need for an external computer. This arrangement saves space in the rack cabinet, simplifies installation and management, reduces costs, and allows great scalability with new remote communication capabilities.

The power supply 14 serves to power the entire device. Both simple and redundant versions have been developed for both 230 V AC and 48 V DC, which is the power supply used in telecommunications environments.

The optical switch 15 allows the input and / or output of the optical transceiver 8 to be switched to multiple optical fibers or optical channels in the fibers. This makes it possible to use a single device to alternately monitor multiple transmission channels or to generate packets to multiple receivers as needed.

The timestamp assignment module 16 allows to assign to each incoming packet time information valid at the time of its arrival, which is useful for some applications, which may be real time or system time. The input of this module can be connected to a time source such as a Global Positioning System (GPS) receiver.

Industrial applicability

This technical solution can be used industrially in local, national and international computer networks as well as in the laboratory environment, especially for network testing and monitoring, packet generation, data processing and modification, for example by encryption, compression, coding or changing quality characteristics.

Claims (16)

A modular programmable platform for hardware high-speed packet processing, characterized in that it comprises at least one universal board (1) with a programmable gate array (FPGA) connected to at least one multiplexer and demultiplexer board (2) for an optical transceiver, comprising modular firmware with at least one sequence of packet streaming modules (3) having the same input interface for receiving packets and control commands, and output interfaces for sending packets and control commands, where the output interfaces of all modules (3) are always in the sequence stream packet processing except the last one connected to the input interface of the following packet stream module (3), the data portion of the input interface of the first packet stream module (3) is connected through the first high-communication module (4) through the transmission channels to the demultiplexer (5) and then to the receiving part of the optical transceiver (8), the data part of the output interface of the last module is connected via the second module (6) to communicate with the high speed transmission channels to the multiplexer (7) (8), a control portion of the input interface of the first packet processing module (3) is connected to the peripheral communication module (10), the control portion of the output interface of the last packet stream processing module (3) is connected a control module (9) for configuring packet stream modules (3), a first module (4) and a second module (6) for communication with high-speed channels, the output of which is coupled to 5 through an input of a module (10) which is interconnected by its outputs for communication with peripherals with a serial interface (11) and / or a flash memory (12) and / or an Ethernet network interface (13), the individual modules of a modular programmable platform they are connected to a power supply (14). Modular platform according to claim 1, characterized in that the peripheral communication module (10) comprises a universal Linux operating system and is located on a processor embedded within a programmable gate array. Modular platform according to claim 1 or 2, characterized in that in case two or more sequences of modules (3) for alternative or simultaneous stream packet processing are included, these sequences of modules (3) for packet stream processing are connected in parallel and configurable and interconnectable. Modular platform according to claim 1 or 2 or 3, characterized in that the optical transceiver module (8) is connected to the optical switch (15). Modular platform according to any one of claims 1 to 4, characterized in that a time allocation module (16) is connected to the peripheral communication module (10). 20 brands of packets. A modular platform according to any one of claims 1 to 5, characterized in that it is built into a standard 1U rack rack. Modular platform according to any one of claims 1 to 6, characterized in that the power supply (14) is redundant. Modular platform according to any one of claims 1 to 7, characterized in that the power supply (14) is at an AC voltage of 230 V. Modular platform according to any one of claims 1 to 7, characterized in that the power supply (14) is at a DC voltage of 48 V. 1 drawing List of reference marks: 1. Programmable Gate Array Board (FPGA) 2. Muitiplexer and demultiplexer board for optical transceiver 3. Modules for packet stream processing 4. Module for communication with high-speed transmission channels 5. Demultiplexer 6. Module for communication with high-speed transmission channels 7. Multiplexer 8. Optical transceiver 9. Control module for module configuration 10. Module for communication with peripherals 11. Serial interface 12. Flash memory 13. Ethernet interface 14. Power supply 15. Optical switch 16. A module for assigning time stamps to packets.