CS227440B1 - Arithmetic and logic processor unit circuitry,especially for intelligent terminals - Google Patents

Description

The invention relates to the connection of an arithmetic and logic unit of a processor, in particular for an intelligent terminal.

Known connections of arithmetic and logic units of the processor allow, in addition to logical operations, to perform arithmetic operations, such as addition, only in binary form. The impossibility of performing binary-decadic operations represents a significant disadvantage, since conversions to the decimal form and back to the binary form must be ensured by the program, which means a great slowdown in operations. Connections are also known which allow, in addition to logical operations, an arithmetic operation, such as addition, to be binary-decadic only using a known code, such as code 8421. In these connections, the disadvantage is the inability to perform binary operations. Known connections, which represent a combination of the above mentioned connections, are either extensive and complex or do not suit their speed.

These disadvantages are eliminated by the connection of the arithmetic and logic unit of the processor, in particular for the intelligent terminal according to the invention, in which the first output for accelerating the transmission of the first central processor circuit is connected to the first input of the first pair of inputs to accelerate the transmission of the first central processor circuit, it is connected to the second input of the first pair of inputs to accelerate the transmission of the circuit to accelerate the transmission, the right shift output of the first central processor circuit is connected to the input to set for non-logic zero-setting of the second JK flip-flop, to the axial output of the transmission circuit to accelerate transmission, and simultaneously form the thirty-third circuit output, the first data output of the first central processor circuit tv oří simultaneously seventeenth ex2

227 440 degree of connection, the second data output of the first central processor circuit is connected to the third input of the twelfth three-input circuit of negation of the logical product and simultaneously forms the eighteenth output of output, the first memory address output of the first central processor the second processor circuit is connected to the first input of the second pair of inputs to accelerate transmission of the circuit to accelerate the transmission, the second output to accelerate transmission of the second central processor circuit is connected to the second input of the second pair inputs to accelerate the transmission of the circuit to accelerate the transmission, the right shift output of the second central processor circuit is connected to the right shift input of the first central processor the second data output of the second central processor circuit is connected to the second input of the twelfth three-input logic product negation circuit and forms the nineteenth wiring output, the second data output of the second central processor circuit is connected to the third input of the tenth three-input logic product negation circuit and simultaneously twentieth output circuit, the first output memory addresses the second central processor circuit simultaneously forms the third output circuit, the second output of the address memory, the second central processor circuit simultaneously forms the fourth output circuit, a first output for accelerating the transfer of the third central processor circuit is coupled to the first input ^w third pair inputs to accelerate the transmission of the circuit to accelerate the transmission, the second output to accelerate the transmission of the third central processor circuit is connected to the second input a third pair of inputs to accelerate transmission of the circuit to accelerate transmission, the right shift output of the third central processor circuit is connected to the right shift input of the second central processor circuit, the first data output of the third central processor circuit simultaneously forms the twenty first output; is connected to the third input of the ninth three-input circuit of the negation of the logical product type and simultaneously forms the twenty-second connection output, the first memory address output of the third central processor circuit simultaneously forms the fifth connection output; to accelerate

227 440 transmission of the fourth central processor circuit is connected to the first input of the fourth pair of inputs to accelerate transmission of the transmission circuit to accelerate transmission, the second output to accelerate transmission of the fourth central processor circuit is connected to the second input of the fourth pair of inputs to accelerate transmission the fourth central processor circuit is connected to the shift input to the right of the third central processor circuit, the first data output of the fourth central processor circuit is connected to the second input of the ninth three-input logic product negation circuit and forms the twenty-third wiring output, the second data output of the fourth central processor circuit is connected to the third input of the seventh three-input circuit of the negation of the logical product and it also forms the twenty-fourth output of the wiring, the first output of the memory address the fourth central processor circuit is simultaneously the seventh circuit output, the second memory address of the fourth central processor circuit is simultaneously the eighth circuit output, the first output to accelerate the transmission of the fifth central processor circuit is connected to the first input of the fifth pair output for accelerating transmission of the fifth central processor circuit is connected to the second input of the fifth pair of inputs for accelerating transmission of the circuit for accelerating transmission, the output of the right shift of the fifth central processor circuit is connected to the shift input of the right of the fourth central processor circuit is simultaneously the twenty-fifth output of the wiring, the second data output of the fifth central processor circuit is connected to the third input of the sixth of the type of negation of the logical product and at the same time the twenty-sixth wiring output, the first memory address of the fifth central processor circuit simultaneously forms the ninth wiring output, the second memory address of the fifth central processor circuit simultaneously forms the tenth wiring output is connected to the first input of the sixth pair of accelerator transmission inputs to accelerate the transmission, the second output to accelerate the transmission of the sixth central processor circuit is connected to the second input of the sixth pair of accelerator transmission inputs to the transmission accelerator to the right feed of the fifth central processor circuit,

227 440 the first data output of the sixth central processor circuit is connected to the second input of the sixth three-input logic product negation circuit and simultaneously forms the 27th wiring output, the second data output of the sixth central processor circuit is connected to the third input of the fourth three-input logic product negation circuit at the same time the twenty-eighth wiring output, the first memory address of the sixth central processor circuit simultaneously constitutes the eleventh wiring output, the second memory address of the sixth central processor memory simultaneously forms the twelfth wiring output, the first output for accelerating transmission of the seventh central processor circuit is connected to the first input of the seventh pair inputs to accelerate the transmission of the circuit to accelerate the transmission, the second output to accelerate the transmission of the seventh central processor circuit is connected to the second the input of the seventh pair of inputs to accelerate the transmission of the circuit to accelerate the transmission, the right shift output of the seventh central processor circuit is connected to the right shift input of the sixth central processor circuit, the first data output of the seventh central processor circuit circuit is connected to the third input of the third logic product negation type and at the same time forms the thirtieth output of output, the first memory address output of the seventh central processor simultaneously forms the thirteenth output of output, the second memory address output of the seventh central processor the output for accelerating the transmission of the eighth central processor circuit is connected to the first input of the eight pair of inputs for accelerating the transmission of the circuit for transmission, the second output to accelerate the transmission of the eighth central processor circuit is connected to the second input of the eighth pair of inputs to accelerate the transmission. the acceleration circuit, the right shift output of the eighth central processor circuit is connected to the right shift input of the seventh central processor circuit. the eighth central processor circuit is connected to the second input of the third three-input logic product negation circuit and forms the thirty-first wiring output, the second data output of the eighth central processor circuit is connected to the third input of the first three input logic product negation circuit , the first memory address output of the eighth central processor circuit forms simultaneously

227 440 the fifteenth wiring output, the second memory address of the eighth central processor circuit simultaneously constitutes the sixteenth wiring output, the zero output of the first JK flip-flop simultaneously forms the thirty-fourth wiring output, the second constants and masking bits of the first central processor circuit simultaneously form the first wiring input. the first input of the constants and masking bits of the second central processor circuit simultaneously form the fourth wiring input, the first input of the first multiplexer of the first quadruple two-input multiplexer simultaneously form the second wiring input, the first input of the second multiplexer of the first quadruple two-input multiplexer the two-input multiplexer forms the sixth input wiring, the first input of the fourth multiplexer of the first quadruple two-input the upstream multiplexer simultaneously forms the seventh input, the second input of the constants and masking bits of the third central processor circuit simultaneously form the fifth connection input, the first constants and masking bits of the fourth central processor circuit simultaneously form the eighth connection input, the second constants and masking bits of the fifth central processor circuit simultaneously form the ninth wiring input, the first input of the constants and masking bits of the sixth central processor circuit simultaneously form the twelfth wiring input, the first input of the first multiplexer of the second quadruple two-input multiplexer simultaneously forms the tenth vetup; the first input of the third multiplexer of the second quadruple two-input multiplexer simultaneously constitutes the fourteenth input connection, the first input of the fourth multiplexer of the second quadruple two-input multiplexer is simultaneously the fifteenth input of the connection, the second input of the constants and masking bits of the seventh central processor circuit is simultaneously the thirteenth connection input; the first and second quadruple two-input multiplexers are connected to the first input of the second two-input logic product negation circuit, and second through the second inverter to the first input of the first two-input logic product negation circuit and form the seventeenth input circuit. the processor circuit forms at the same time6

227 440 are the 18th input, the second inputs to determine the microinstructions of the first to eighth central processor circuits are connected to the first input of the eight-input logic product negation circuit and form the nineteenth wiring input, the third inputs to determine the microinstructions of the first to eighth central processor circuit to the second input of the eight-input logic product negation circuit and form the twentieth wiring input, the fourth inputs to determine the microinstructions of the first to eighth central processor circuit are connected to the third input of the eight-input logical product negation circuit and form the twenty first wiring input, the fifth input by the microinstruction of the first to eighth central processor circuits are connected via the eighth inverter to the fourth input of the eight-input logic product negation circuit and form simultaneously twenty The second wiring input, the sixth microinstruction inputs of the first to eighth central processor circuits are connected via the ninth inverter to the fifth and sixth inputs of the eight-input logic product negation circuit, and simultaneously form the twenty-third wiring input, the seventh inputs to the microinstruction of the first to eighth central processor circuits are connected via the tenth inverter to the seventh and eighth inputs of the eight-input logic product negation circuit, and simultaneously form the twenty-fourth wiring input, the transmission acceleration circuit input is connected to the right shift input of the eighth central processor circuit, simultaneously form the twenty-fifth wiring input, the clock input of the first flip-flop type JK simultaneously forms the twenty-sixth, 100th wiring input, the clock inputs of the second to fifth flip-flop type JK j are connected via the third inverter to the second input of the first and second circuits of the type of negation of the logical product, and to the clock inputs of the first to eighth central processor circuit and form the 27th wiring input, the second data input from the memory of the first central processor wiring, the first data input from the memory of the first central processor circuit simultaneously constitutes the twenty-ninth wiring input, the second data input from the memory of the second central processor circuit simultaneously constitutes the thirtieth wiring input, the first data input from the memory of the second central processor circuit simultaneously constitutes the thirty first wiring input the data from the memory of the third central processor circuit simultaneously forms the thirty-second

227 440 wiring input, the first data input from the memory of the third central processor circuit simultaneously forms the thirty-third wiring input, the second data input from the memory of the fourth central processor circuit simultaneously constitutes the thirty-fourth connection input, the first data input from the memory of the fourth central processor circuit simultaneously constitutes the thirty-fifth wiring input, the second data input from the memory of the fifth central processor circuit simultaneously constitutes the thirty-sixth wiring input, the first data input from the memory of the fifth processor processor simultaneously constitutes the thirty-seventh wiring input, the second data input from the memory of the sixth central processor circuit simultaneously constitutes the thirty-eighth wiring input , the first data input from the memory of the sixth central processor circuit is simultaneously the thirty-ninth connection input, the second data input from the memory of the seventh central processor at the same time the 40th wiring input, the first data input from the memories of the seventh central processor circuit simultaneously constitutes the forty-first wiring input, the second data input from the memory of the eighth central processor circuit simultaneously constitutes the forty-second wiring input wiring input, second input of external devices of the first central processor circuit at the same time Forty-fourth wiring input, first input of external devices of first central processor circuit at the same time the forty-fifth wiring input, second input of external devices of second central processor circuit simultaneously constitutes forty-sixth wiring input, first input the external devices of the second central processor circuit simultaneously form the forty-seventh input of the wiring, the second input at The third input of external devices of the third central processor circuit simultaneously constitutes the ninety-eight connection input, the second input of external devices of the fourth central processor circuit simultaneously constitutes the 50th connection, the first input of external devices of the fourth central processor circuit simultaneously form the fifty ... first input wiring, second input of external devices of the fifth central processor circuit simultaneously form fifty second wiring input, first input of external devices of the fifth central processor circuit simultaneously form fifty third wiring input, second input of external devices of the sixth central processor circuit simultaneously 54th Canopy Entry8

227 440, the first input of the sixth central processor circuit simultaneously constitutes the fifty-fifth wiring input, the second input of the external devices of the seventh central processor circuit simultaneously constitutes the fifty-sixth wiring input, the first input of the external devices of the seventh central processor circuit simultaneously constitutes the fifty-seventh wiring input external devices of the eighth central processor circuit simultaneously form the fifty-eight wiring input, the first input of the external devices of the eighth central processor circuit simultaneously form the fifty-ninth wiring input, the inputs for equipping the data outputs of the first to eighth central processor circuit simultaneously form the sixtieth wiring input The first to eighth central processor circuits are connected to the ground potential input terminal the first to eighth central processor circuitry is connected to the zero potential input terminal, the power inputs of the first to eighth central processor circuitry are connected to the positive voltage input terminal, the first transmission acceleration output is connected to the second central processor circuit transmission input, the second output the transmission circuit for accelerating transmission is connected to the transmission input of the third central processor circuit, longer to the input for setting the logical one of the fifth flip-flop type JK and through the seventh inverter to the input for setting the logical zero of the fifth flip-flop type JK the transmission acceleration is connected to the transmission input of the fourth central processor circuit, the fourth transmission output of the transmission circuit for accelerating transmission is connected to the transmission input of the fifth central processor circuit, and to the setting input to the fourth JK flip-flop and through the sixth inverter to the JK fourth flip-flop input, the fifth accelerator transmission output is connected to the transmission input of the sixth central processor circuit, the sixth transmission accelerator output is connected to the transmission input of the seventh central processor circuit, to the input for setting the logical one of the third flip-flop type JK and through the fifth inverter to the input for setting the logical zero of the third flip-flop type JK; transmission of the eighth central processor circuit, the output of the eight-input logic product negation circuit is connected to the equipment input

227 440 output of the transmission accelerator circuit, the ground input of the accelerator circuit is connected to the input terminal, zero potential and its power input is connected to the positive voltage input terminal, the first multiplexer output of the first quadruple dual input multiplexer is connected to the first input of constants and masking bits of the first central processor circuit, the output of the second multiplexer of the first quadruple two-input multiplexer is connected to the second constant input and masking bits of the second central processor circuit, the output of the third multiplexer of the first quadruple two-input multiplexer is connected to the first input of constants and masking bits of the third central processor circuit the multiplexer of the first quadruple dual-input multiplexer is connected to the second input of the constants and masking bits of the fourth central processor circuit u, the output of the first multiplexer of the second quadruple two-input multiplexer is connected to the first input of constants and masking bits of the fifth central processor circuit, the output of the second multiplexer of the second quadruple two-input multiplexer is connected to the second input of constants and masking bits of the sixth central processor circuit. the multiplexer is connected to the first input of constants and masking bits of the seventh central processor circuit, the output of the fourth multiplexer of the second quadruple two-input multiplexer is connected to the second input of constants and masking bits of the eighth central processor circuit, zero potential input terminal, grounding inputs of the first and second quadruple 2Vs of the multiplexer are connected to the input terminal of zero potential and their power inputs are connected to the input terminal of positive voltage, the output of the first two-input circuit of the negation of the logical product type is connected to the reset input of the first flip-flop type JK. zero potential input terminal, the output of the second 2-input logic product negation circuit is connected to the adjusting inputs of the second to the 5th JK flip-flop, the output of the second JK type flip-flop is connected to the first and second inputs input of the third three-input circuit ty10

227 440 pu logic product negation whose output is connected to the third input of the second three-input logic product negation circuit, the output of the first two input logic product negation circuit is connected to the first and second inputs of the second two-input logic product negation circuit whose output is connected to the second input of the third multiplexer of the second quadruple two-input multiplexer, to the second input of the fourth multiplexer of the second quadruple two-input multiplexer and through the first inverter to the logic 1 input of the first JK flip-flop; of the three-input circuit of the negation of the logical product and the first input of the sixth three-input circuit of the negation of the logical product, the output of which is connected to the third input of the fifth three-input circuit of the negation of the logical product The output of the fourth three-input logic product negation circuit is connected to the first and second inputs of the fifth three-input logic product negation circuit, the output of which is connected to the second input of the first multiplexer of the second quadruple dual input multiplexer and to the second input of the second multiplexer of the second quadruple double input multiplexer. the output of the fourth flip-flop type JK is connected to the first and second inputs of the seventh three-input logic product negation circuit and to the first input of the ninth three-input logical product of the logic product negation type whose output is connected to the third input the logic product negation circuit is connected to the first and second inputs of the eighth three-input logic product negation circuit whose output is connected to the second input of the third multip lexor of the first quadruple two-input multiplexer and to the second input of the fourth multiplexer of the first quadruple two-input multiplexer, the one output of the fifth flip-flop type JK is connected to the first and second inputs of the tenth three-input logic product negation circuit; the output is connected to the third input of the eleventh three-input logical product negation circuit, the output of the tenth three-input logic product negation circuit is connected to the first and second inputs of the eleventh three-input logical product negation circuit, whose output is connected to the second input of the first quadruple multiplexer

227,440 of the two-input multiplexer and the second input of the second multiplexer in the first four-fold two-input multiplexer.

The connection of the arithmetic and logic unit of the processor, in particular for the intelligent terminal, according to the invention has the advantage of allowing all basic logical operations to be performed and, in addition to binary addition, addition in binary decimal code 8421, all operations being performed in parallel. The whole connection is very simple and has the further great advantage that it uses a conventional arithmetic and logic unit of great integration with central processor circuits, even though it does not itself allow binary decimal operations. Said properties are achieved in that the decimal addition operation is implemented in several steps in which the elementary operation of the binary addition of the generated constant is repeatedly performed. In this way, all parts of the wiring are used multiple times and wiring is my minimum number of logical elements, although all operations are performed in a fast parallel manner.

An example of an arithmetic and logic unit of a processor, in particular for an intelligent terminal, according to the invention is shown in the accompanying drawings, in which Fig. 1 represents the arithmetic and logic unit of the processor and its connection with the processor controller, main memory and input / output controller. Figures 2a to 2d show a circuit diagram of the arithmetic and logic unit of the processor, Figure 3 a timing diagram of a microinstruction in programmable ROM type memory, and Figure 4 a timing diagram of a time source.

The first output 132 to accelerate the transmission of the first central processor circuit CPO1 for the XO signal is connected to the first input 715 of the first pair of inputs to accelerate the transmission of the PUP circuit to accelerate the transmission. The second output 131 to accelerate the transmission of the first central processor circuit CP01 for the YP signal is connected to the second input 716 of the first pair of inputs to accelerate the transmission of the PUP circuit to accelerate the transmission. The right shift output 133 of the first central processing unit CPP1 for the signal is connected to the input 76 to set the logical one of the second flip-flop KJK2 type JK, via the fourth inverter IN4 to the input 78 to adjust the logic zero of the second flip-flop KJK2 type JK 738 PUP circuit transmission for

227 440, and simultaneously forms the thirty-third wiring output 033 for connection to the CPU controller. The first data output 134 of the first central processor circuit CP01 for the 15C signal simultaneously forms the seventeenth output 017 of the wiring for main memory connection HP. The second data output 135 of the first central processor circuit CP01 for signal 151 is connected to the third input of the twelfth three-input logic product negation type NT12, and simultaneously forms the eighteenth output 018 of the main memory connection HP. The first memory address output 136 of the first central processor circuit CP01 for the SU signal simultaneously forms the first circuit output 01 for connection to the main memory $ HP. The second memory address 137 of the first central processor circuit CP01 for the signal A1 simultaneously forms the second circuit output 02 for connection to the main memory $ HP. The first output 182 to accelerate the transmission of the second central processing circuit CP02 for signal XI is connected to the first input 713 of the second pair of inputs to accelerate the transmission of the PUP circuit to accelerate the transmission. The second output 181 to accelerate the transmission of the second central processor circuit CP02 for the Y1 signal is connected to the second input 714 of the second pair of inputs to accelerate the transmission of the PUP circuit to accelerate the transmission. The right shift output 183 of the second central processor circuit CP02 is connected to the right shift input 109 of the first central processor circuit CP01. The first data output 184 of the second central processing circuit CP02 for the 15Σ signal is connected to the second input of the twelfth three-input logic product negation type NT12 and simultaneously forms the nineteenth wiring output 019 for connection to the main steam t HP. The second data output 185 of the second central processing circuit CP02 for the T5J signal is connected to the third input of the tenth three-input logic product negation type NT10 and simultaneously forms the twenty output 020 of the circuit for connection to the main memory HP. The first memory address output 186 of the second central processing circuit CP02 for the signal ΣΣ simultaneously forms the third output 03 of the circuitry for connection to the main memory HP. The second memory address output 187 of the second central processing circuit CP02 for the AT signal simultaneously forms the fourth circuit output 04 for connection to the main memory HP. The first output 232 to accelerate the transmission of the third central processor circuit CP03 for the X2 signal is connected to the first input 711 of the third pair of inputs to accelerate the transmission of the PUP circuit to accelerate the transmission. A second output 231 to accelerate transmission of the third central pro13

227 440 of the CP03 for circuit Y2 is connected to low input 712 of the third pair of inputs to accelerate transmission of the PUP to accelerate transmission. The right shift output 233 of the third central processor circuit CPO3 is connected to the right shift input 199 of the second central processor circuit CPO2. The first data output 234 of the third central processor circuit CPO3 for the signal D4 simultaneously forms the twenty-first circuit output 021 for connection to the HP main memory. The second data output 239 of the third central processing unit CPO3 for the I5 * signal is connected to the third input of the ninth three-input logic product negation type NT9 and simultaneously forms the twenty-second output 022 of the main memory connection. The first memory address output 236 of the third central processor circuit CP03 for the signal tý4 coincided the fifth wiring output 09 at the same time to the main memory HP. The second memory address output 237 of the third central processing circuit CP03 for the signal A9 simultaneously forms the sixth output 06 of the circuitry for connection to the main memory HP. The first transmission acceleration output 282 of the fourth central processor circuit CP04 for the X3 signal is coupled to the first input 709 of the fourth pair of inputs to accelerate the transmission of the PUP circuit to accelerate the transmission. The second transmission acceleration output 281 of the fourth central processor circuit CP04 for the signal Ϊ3 is connected to the second input 710 of the fourth pair of inputs to accelerate the transmission of the PUP circuit to accelerate the transmission. The right shift output 283 of the fourth central processor circuit CP04 is coupled to the right shift input 209 of the third central processor circuit CP03. The first data output 284 of the fourth central processor circuit CP04 for the I5 signal is coupled to the second input of the ninth three-input logical product negation type NT9 and simultaneously forms the twenty-third output 023 of the main memory connection HP. The second data output 289 of the fourth central processor circuit CP04 for signal 137 is connected to the third input of the seventh three-input logic product negation type NT7 and simultaneously forms the twenty-fourth output 024 of the circuit for connection to the main memory HP. The first memory address output 286 of the fourth central processor circuit CP04 for the A 'signal simultaneously forms the seventh output 07 of the circuitry for connection to the main memory HP. The second memory address output 287 of the fourth central processor circuit CP04 for signal 17 simultaneously forms the eighth output 08 for connection to the main memory HP. First output 332 to accelerate transmission of the fifth central processor circuit CP09 for

227 440, the X4 signal is coupled to the first input 707 of the fifth pair of inputs to accelerate the transmission of the PUP circuit to accelerate the transmission. The second output 331 for accelerating the transmission of the fifth central processor circuit CPO5 for the Y4 signal is connected to the second input 708 of the fifth pair of inputs to accelerate the transmission of the PUP circuit to accelerate the transmission. The right shift output 333 of the fifth central processor circuit CF05 is connected to the right shift input 259 of the fourth central processor circuit CP04. The first data output 334 of the fifth central processor circuit CP05 for the signal 55 simultaneously constitutes the twenty-fifth circuit output 025 for connection to the main steam! HP. The second data output 335 of the fifth central processor circuit CP05 for signal 55 is connected to the third input of the sixth three-input circuit of the logical product negation type NT6 and simultaneously forms the twenty-sixth output 026 of the circuit for connection to the main steam! HP. The first memory address 336 of the fifth central processor circuit CP05 for the Á5 signal simultaneously forms the ninth output 09 of the wiring for connection to the main steam! HP. The second memory address output 337 of the fifth central processor circuit CP05 for the signal A9 simultaneously forms the tenth output 010 of the circuit for connection to the main steam! HP. The first transmission acceleration output 382 of the sixth central processor circuit CP06 for the X5 signal is coupled to the first input 705 of the sixth transmission accelerator input pair QUP. The second transmission acceleration output 381 of the sixth central processor circuit CP06 for the Y5 signal is coupled to the second input 706 of the sixth transmission accelerator input pair QUP. The right shift output 383 of the sixth central processor circuit CP06 is connected to the right shift input 309 of the fifth central processor circuit CP05 * The first data output 384 of the sixth central processor circuit

CP06 for signal 510 is connected to the second input of the sixth three-input circuit NT6 of the logic product negation type and simultaneously forms the twenty-seventh output 027 of the circuit for connection to the main steam! HP. The second data output 38 ' of the sixth central processor circuit CP06 for the D1 signal is coupled to the third input of the fourth three-input logical product negation type NT4 and simultaneously forms the 28th output 028 of the circuit for connection to the main steam! HP. The first memory address output 386 of the sixth central processor circuit CPO6 for the A1O signal simultaneously forms the eleventh circuit output 011 for connection to the main steam! HP. The second memory address output 387 of the sixth central processor15

The 227,414 GP06 circuit for the All signal simultaneously forms the twelfth output 012 of the circuit for connection to the HP main steam. The first transmission acceleration output 432 of the seventh central processor circuit CP07 for the X6 signal is coupled to the first input 703 of the seventh pair of inputs to accelerate the transmission of the PUP to accelerate the transmission. The second transmission acceleration output 431 of the seventh central processor circuit CP07 for the Y6 signal is coupled to the second input 704 of the seventh pair of inputs to accelerate the transmission of the PUP to accelerate the transmission. The right shift output 433 of the seventh central processor circuit CP07 is connected to the right shift input 359 of the sixth central processor circuit CP06. The first data output 434 of the seventh central processor circuit CP07 for the D12 signal simultaneously forms the twenty-ninth output 029 of the circuit for connection to the HP main steam. The second data output 435 of the seventh central processor circuit CP07 for the D13 signal is connected to the third input of the third three-input logic product negation type NT3 and simultaneously forms the thirtieth output 030 of the circuit for connection to the HP main steam. The first memory address output 436 of the seventh central processor circuit GP07 for the A12 signal simultaneously forms the thirteenth output 013 of the circuit for connection to the main memory HP. The second memory address output 437 of the seventh central processor circuit CPQ7 for the signal Ϊ signál3 simultaneously forms the fourteenth output 014 of the connection for connection to the main memory HP. The first transmission acceleration output 482 of the eighth central processor circuit CP08 for the X7 signal is coupled to the first input 701 of the eighth transmission accelerator input pair PUP. The second transmission acceleration output 481 of the eighth central processor circuit CP08 for the Y7 signal is coupled to the second input 702 of the eighth transmission accelerator input pair. The right shift output 483 of the eighth central processor circuit CP08 is connected to the right shift input 409 of the seventh central processor circuit CP07 «The first data output 484 of the eighth central processor circuit CP08 for the l4 signal is connected to the second input of the third three input thirty-first wiring output 031 for connection to HP main memory. The second data output 485 of the eighth central processor circuit CP08 for the ΰΪ5 signal is connected to the third input of the first three-input logic product negation type NT1 and simultaneously forms the thirty-second output 032 of the main memory connection. The first memory address output 486 of the eighth memory

The CPC 227 440 central processor circuit for the ΪΪ4 signal also forms the fifteenth output 015 of the circuit for connection to the HP main memory. The second memory address output 487 of the eighth central processor circuit 0P08 for the signal A 1 forms simultaneously the 16th circuit output 016 for connection to the main memory HP. The output 072 of the first flip-flop KJK1 of the J-K type for the signal ϊ) ύΡ simultaneously forms the thirty-fourth output 034 of the wiring for connection to the controller of the CPU of the processor. The second input 117 of the constants and masking bits of the first central processor circuit CP01 for the KS signal simultaneously forms the first wiring input 1 for connection to the processor controller 60 of the processor. The first constant input and masking bits 166 of the second central processor circuit CPQ2 for the signal KJ simultaneously form the fourth wiring input 4 for connection to the processor controller 60 of the processor. The first input 508 of the first multiplexer of the first quadruple two-input multiplexer CMP1 for the KT signal simultaneously constitutes the second circuit input £ for connection to the processor controller 60 of the processor. The first second multiplexer input 506 of the first quadruple two-input multiplexer CMP1 for the signal ΚΣ simultaneously forms the third wiring input 6 for connection to the processor controller 60 of the processor. The first third multiplexer input 504 of the first quadruple two-input multiplexer CMP1 for the signal K1 simultaneously forms the sixth wiring input 6 for connection to the controller CPU of the processor. The first input 502 of the fourth multiplexer of the first quadruple two-input multiplexer ČMP1 for the KS signal simultaneously constitutes the seventh input 7 of the connection for connection to the controller of the CPU of the processor. Second input

The 217 constants and masking bits of the third central processor circuit CP03 for the K4 signal simultaneously form the fifth wiring input 2 for connection to the controller CPU of the processor. The first constant input and masking bits 266 of the fourth central processor circuit CP0 for the signal K7 simultaneously form the eighth wiring input 8 for connection to the processor controller 60 of the processor. The second input 317 of the constants and masking bits of the fifth central processor circuit CP05 for the KS signal simultaneously constitutes the ninth input circuit 9 for connection to the controller CPU of the processor. The first input 66 of the constants and masking bits of the sixth central processor circuit CP06 for the signal ΚΓΓ simultaneously forms the twelfth wiring input 12 for connection to the processor controller 60 of the processor. The first input 608 of the first multiplexer of the second quadruple two-input multiplexer ČMP2 for the K9 signal simultaneously forms the tenth input 10 for connection to the processor controller of the CPU. Prv17

227 440, the second multiplexer input 606 of the second quadruple two-input multiplexer ČMP2 for the K1 signal simultaneously forms the eleventh wiring input 11 for connection to the controller CPU of the processor. The first third multiplexer input 604 of the second quadruple two-input multiplexer ČMP2 for the signal ΚΪ3 simultaneously constitutes the fourteenth wiring input 14 for connection to the controller CPU of the processor. The first fourth multiplexer input 602 of the second quadruple two-input multiplexer ČMP2 for the ΚΪ4 signal simultaneously forms the fifteenth wiring input 15 for connection to the processor controller of the CPU. The second constant input and masking input 417 of the seventh central processor circuit CPQ7 for the IR12 signal simultaneously forms the thirteenth wiring input 13 for connection to the processor controller 60 of the processor. The first constant input and masking bits 466 of the eighth central processor circuit CP08 for the K1 signal simultaneously form the sixteenth wiring input 16 for connection to the processor controller 60 of the processor. Selection inputs 501,601 of the first and second quadruple two-input multiplexer ČMP1, ČMP2 for the DEC signal are connected both to the first input of the second two-input circuit of the negation of the logical product type and through the second inverter IN2 wiring input 1-7 for connection to the CPU control unit. The first inputs 102, 152, 202, 252, 302, 352, 4Q2 ₁₄₅₂ for determining mikroinstukcí first to eighth central processor CP01 to CP08 circuit for signal FO eighteenth simultaneously forms the inlet 18 for wiring connection to the control unit of the SPS processor. The second inputs 103, 153, 203, 253, 303, 353, 403, 453 for determining the microinstructions of the first to eighth central processing circuitry CP01 to CP08 for the F1 signal are connected to the first input of the eight-input logic product NO circuit. wiring for connection to CPU control unit. The third inputs 104, 154, 204, 254. 304, 354, 404, 454 for determining the microinstructions of the first to eighth central processing circuitry CP01 to CP08 for the F2 signal are connected to the second input of the eight-input logic product negation circuit NO. wiring for connection to CPU control unit. The fourth inputs 105, A55, 205, 255. 305, 155, 405, 455 to determine the microinstructions of the first to eighth central processor circuitry CP01 to CP08 for the F3 signal are connected to the third input of the eight-input logic product type NO circuit.

227 440 wiring input 21 for connection to the CPU control unit. The fifth inputs 106, 156, 206, 256. 306, 356. 406. 456 to determine the microinstructions of the first to eighth central processing circuitry 0P01 to CP08 for the F4 signal are coupled via the eighth IN8 inverter to the fourth input of the eighth input of the logic 3-type negation type. at the same time, the twenty-second wiring input 22 for connection to the CPU control unit. The sixth inputs 102, 122, 202 »257, 307, 357, 121, 457 to determine the microinstructions of the first to eighth central processor circuitry CP01 to CP08 for the F5 signal are connected via the ninth inverter IN9 to the fifth and sixth input of the eight input and forms at the same time the twenty-third wiring input 23 for connection to the CPU control unit. The seventh inputs X08, 158. 208. 258, 308, 358, 408, 458 to determine the microinstructions of the first to eighth central processor circuitry CP01 to CP08 for the F6 signal are connected via the tenth inverter IN10 to the seventh and eighth input of the eight input and form at the same time the twenty-fourth wiring input 24 for connection to the CPU controller. The PUP transmission transmission input 717 for the signálΠ signal is connected to the right shift input 459 of the eighth central processing unit CP08, to the transmission input 118 of the first central processing unit CP01, and simultaneously forms the twenty-fifth wiring input 25 for connection to the CPU control unit. The clock input 72 of the first flip-flop KJK1 of the J-K type for the TB signal simultaneously constitutes the twenty-sixth wiring input 26 for connection to the processor control unit RPU. Clock inputs 21 »82, 82, 92 of second to fifth flip-flop KJK2 to KJK5 of J-K type for UEK signal? are connected via the third inverter IN3 to the second input of the first and second circuits of the logic product negation type ND1, ND2 and to the clock inputs 101, 151, 201, 251, 301, 351.

* 401. 451 of the first to eighth central processor circuitry CP01 to CP08, and simultaneously form the 27th wiring input 27 for connection to the CPU controller. The second data input 113 from the memory of the first central processor circuit CP01 for the signal SK5 simultaneously forms the twenty-eight wiring input 28 for connection to the main memory HP. The first data input 112 from the memory of the first central processing circuit CP01 for the HT signal. it also forms the 29th input 29 for connection to the HP main memory. The second data input 163 from the memory of the second central processing circuit CP02 for the signal ΗΣ simultaneously forms the 30th input 30

The first input 16 of data from the memory of the second central processing circuit CP02 for the signal M1 simultaneously forms the thirty-first input 31 of the connection for connection to the main memory HP. The second data input 213 from the memory of the third central processing circuit CP03 for the signal M4 simultaneously forms the thirty-second wiring input 32 for connection to the main memory HP. The first data input 212 from the memory of the third central processing circuit CP03 for the signal M5 simultaneously forms the thirty-third wiring input 33 for connection to the main memory HP. The second data access 263 from the memory of the fourth central processing unit CPO4 for the KS signal simultaneously forms the thirty-fourth wiring input 34 for connection to the main memory HP. The first data access 262 from the memory of the fourth central processor circuit CPQ4 for the signal M? it also forms the 35th wiring input 35 for connection to HP main memory. The second data input 313 from the memory of the fifth CPO5 central processor circuit for the M8 signal simultaneously forms the 36th wiring input 36 for connection to the main memory HP. The first data input 312 from the memory of the fifth central processor circuit CP05 for the signal Ϊ25 is simultaneously the thirty-seventh input 37 for connection to the main memory HP. The second data input 363 from the memory of the sixth central processor circuit CP06 for the signal ΜΪ0 simultaneously forms the 38th input 38 of the circuit for connection to the main memory HP. The first data input 362 from the memory of the sixth central processor circuit CP06 for the signal Mil is simultaneously the thirty-ninth input 39 of the circuitry for connection to the main memory HP. The second data input 413 from the memory of the seventh central processor circuit CP07 for the signal M12 simultaneously constitutes the 40th wiring input 40 for connection to the main memory HP. The first data input 412 from the memory of the seventh CPO7 central processor circuit for the ΜΪ3 signal simultaneously constitutes the forty-first wiring input 41 for connection to the main memory HP. The second data input 463 from the memory of the eighth central processor circuit CP08 for the signal ΚΪ4 simultaneously forms the forty-second second input circuit 42 for connection to the main memory HP. The first data input 462 from the memory of the eighth central processor circuit CP08 for the Ml5 signal simultaneously forms the forty-third wiring input 43 for connection to the main memory HP. The second external device input 113 of the first central processor circuit CPO1 for the TU signal simultaneously forms the forty-fourth wiring input 44 for connection to the I / O controller of the I / O. The first input 114 of the external devices of the first central processor circuit CP01 for the 3 signal ΪΤ constitutes sou20

227 440 early Forty-fifth input 45 wiring for connection to the I / O controller. Second external device input 165 of second central processor circuit CP02 for signal T? at the same time, the forty-six input 46 of the wiring for connection to the RVV input and output controller. The first external device input 164 of the second central processor circuit CP02 for the TJ signal simultaneously forms the 37th wiring input 47 for connection to the RVV I / O controller. The second external device input 215 of the third central processor circuit CP03 for the T4 signal simultaneously forms the 48th wiring input 48 for connection to the input / output controller RW. The first external device input 214 of the third central processor circuit CPQ3 for the T5 signal simultaneously forms the 49th wiring input 49 for connection to the RVV I / O controller. The second external device input 265 of the fourth central processor circuit CPO4 for the T5 signal simultaneously forms the 50th wiring input 50 for connection to the RVV I / O controller. The first external device input 264 of the fourth central processor circuit CP04 for the rr signal simultaneously forms the fifty first wiring input 51 for connection to the RVV I / O controller. The second external device input 315 of the fifth central processor circuit CP05 for sqgn 15 simultaneously forms the fifty-second wiring input 52 for connection to the input / output controller RW. The first external device input 314 of the fifth central processor circuit CP05 for the Π signal simultaneously forms the fifty-third wiring input 53 for connection to the input / output controller RW. The second external device input 365 of the sixth central processor circuit CP06 for the signal 1010 simultaneously forms the fifty-fourth wiring input 54 for connection to the input / output controller RW. The first external device input 364 of the sixth central processor circuit CP06 for the signal ΤΓΓ simultaneously forms the fifty-fifth wiring input 55 for connection to the input / output controller RW. The second input 415 of the external devices of the seventh central processor circuit CP07 for the Τ1Σ signal simultaneously constitutes the fifty-sixth wiring input 56 for connection to the input and output controller ŘW. The first input 414 of the external devices of the seventh central processor circuit CP07 for the signal 113 simultaneously constitutes the 57th wiring input 57 for connection to the input-output controller. The second external device input 465 of the eighth central processor circuit CP08 for the signal Ϊ14 simultaneously forms the fifty-eighth wiring input 58 for connection to the input / output controller ŘW. First input 464 outside21

The 227,440 devices of the eighth central processing unit ”0P08 for the 1Ϊ5 signal simultaneously form the 59th input 59 of the wiring for connection to the I / Os of the I / O controller. Inputs 119 _f 169, 219, 269, 319, 3691 419, 469 for equipment outputs data first to eighth CPOl central processor circuit to signal CP08 for the EU are currently sixty input wiring 60 for connection to the controller RDC input and output. The memory addressing inputs 120, 170, 220, 270, 320, 370, 420, 470 of the first to eighth central processor circuits CP01 to GPQ8 are connected to the zero potential input terminal 61. The ground inputs 110, 160, 210, 260, 310, 360, 410, 460 of the first to eighth central processor circuits CP01 to CP08 are connected to the zero potential input terminal 61. Power inputs 111, 161, 211, 261, 311,

361, 411. 461 of the first to eighth central processor circuitry CPO1 to CP08 are connected to the positive voltage input terminal 62. The first transmission output 731 of the PUP to accelerate transmission for the signal C11 is connected to the transmission input 168 of the second central processing circuit CP02. The second PUP accelerator transmission output 732 for the C1 signal is connected to the transmission input 218 of the third central processor circuit CP03, to the input 91 to set the logical one of the fifth flip-flop KJK5 type JK, and via the seventh inverter IN7 to the set input 93 to the logical zero of the fifth-flip-flop KJK5 type JK. The third PUP accelerator transmission output 733 for signal C13 is connected to the transmission input 268 of the fourth central processor circuit CPQ4. The fourth PUP accelerator transmission output 734 for the signal C14 is connected to the transmission input 318 of the fifth central processor circuit CP05, input 86 to set the logical one of the fourth flip-flop KJK4 type JK and through the sixth inverter IN6 to input 88 to set the logical zero of the fourth flip-flop KJK4 type JK The fifth transmission output 735 of the PUP to accelerate transmission for signal Cl5 is connected to transmission input 368 Sixth central processor circuit CP06. The sixth QUP transmission acceleration output 716 for the C1 signal is connected to the transmission input 418 of the seventh central processing unit CP07, to the input 81 for setting the logical one of the third flip-flop KJK3 type JK and via the fifth inverter IN5 to the logic zeros of the third flip-flop KJK3 type JK. The seventh QUP transmission acceleration output 737 for the 0Ϊ7 signal is connected to the transmission input 468 of the eighth central

227 440 CPOQ processor circuit. The output of the 8-input logic product negation NO circuit is connected to input 720 to equip the transmission output of the PUP circuit to accelerate transmission. The grounding input 719 of the PUP to accelerate transmission is connected to the zero potential input terminal 61 and its power input 718 is connected to the positive voltage input terminal 62. The first multiplexer output 531 of the first quadruple two-input multiplexer ČMP1 is connected to the first input 116 of the constants and masking bits of the first central processor circuit CP01. The output 532 of the second multiplexer of the first quadruple two-input multiplexer δ připojen is connected to the second input 167 of the constants and masking bits of the second central processor circuit CP02. The third multiplexer output 533 of the first quadruple two-input multiplexer of the CMP1 is coupled to the first constant input and masking bits 216 of the third central processor circuit CP03. The first multiplexer output 631 of the second quadruple two input multiplexer ČMP2 is coupled to the first input of constants and masking bits of the fifth central processor circuit CP05. The second multiplexer output 632 of the second quadruple two-input multiplexer ČMP2 is connected to the second input 367 of the constants and masking bits of the sixth central processor circuit CP06. The third multiplexer output 633 of the second quadruple two-input multiplexer ČMP2 is coupled to the first input 416 of constants and masking bits of the seventh central processor circuit CP07. Inputs 512, 612 for controlling the outputs of the multiplexers of the first and second quadruple dual-input SmPI multiplexers. The terminals are connected to the input terminal 61 of the zero potential. The ground inputs 511 _t 611 of the first and second quadruple two-input multiplexers ČMP1, ČMP2 are connected to the zero potential input terminal 61 and their power inputs 510, 610 are connected to the positive voltage input terminal 62. The output of the first two-input logic product negation circuit ND1 is connected to the reset input 74 of the first flip-flop KJK1 of the JK type, whose logic zero input 73 is connected to the zero potential input terminal 61. Exit

227 440 of the second dual input NP2 logic product negation circuit is connected to the input inputs 79, 84, 89, 94 of the second to fifth flip-flop circuits KJK2 to KJK4 of the J-K type. One output 076 of the second flip-flop KJK2 of the JK type for the C4 signal is connected to the first and second inputs of the first three-input logic product negation type NT1 and to the first input of the third three-input logic product negation type NT3. NT2 logical product negation. The output of the first two-input logic product negation type NT1 is connected to the first and second inputs of the second two-input logic product negation type NT2 whose output is connected to the second input 605 of the third quadruple two-input multiplexer ČMP2. multiplexer ČMP2 and through the first inverter INI on the input 71 to set the logical one of the first flip-flop KJK1 type JK. One output 081 of the third flip-flop KJK3 of the JK type for CT7 signal is connected to the first and second inputs of the fourth three-input circuit of the logical product negation type NT4 and to the first input of the sixth three input circuit NT6 logical product negation. The output of the fourth three-input logical product negation type NT4 is connected to the first and second inputs of the fifth three-input logical product negation type NT5, the output of which is connected to the second input 609 of the second quadruple two-input multiplexer. multiplexer ČMP2. A single output 086 of the fourth flip-flop KJK4 of the JK type for a signal <22 is connected to the first and second inputs of the seventh three-input logic product negation circuit NT7 and to the first input of the ninth three-input logic product negation circuit NT9. The eighth NT8 logic product negation type. The output of the seventh three-input NT7 logic product negation circuit is connected to the first and second inputs of the eighth three-input logic product negation type NT8, whose output is connected to the second input 505 of the third multiplexer of the first quadruple two-input multiplexer ČMP1 and to the second V3tup 503 of the fourth multiplexer of the first quadruple two-input multiplexor ČMP1. One output 091 of the fifth

227 440 of the JK5 flip-flop type JK for U1 signal is connected to the first and second inputs of the tenth three-input NT10 negation of the logical product and to the first input of the twelfth three-input circuit NT12 of the negation of the logical product. negation of a logical product. The output of the tenth three-input logical product negation type NT10 is connected to the first and second inputs of the eleven three-input negation logical product type NT11, the output of which is connected to the first multiplexer input 509 of the first quadruple two-input multiplexer CMP1 and the second input 507 of the second multiplexer. of the first quadruple two-input multiplexer ČMP1.

The arithmetic and logic unit ALJ of the processor is connected to the main memory HP (Fig. 1) by means of the signals: 555 to M15 for input of data read from the main memory HP, AU to A14 for output address,

EU to D15 for HP main memory write data, Processor ALJ processor is coupled to processor control unit via signals: KU to ΚΪ5 for constant input, DEC for switching processor arithmetic and logic unit ALJ to direct decimal addition mode , F0 to F6 to input the operation code in the arithmetic and logic unit ALJ of the processor, KU for input of binary or decimal transmission, KlF for output of binary transmission, DIF for output of decimal transmission,

TB for the time signal input to control decimal operations and CLk2 for the clock signal for the arithmetic and logic unit ALJ of the processor. The ALJ processor arithmetic and logic unit is connected to the I / O controller using signals: T5U to 015 for data output, TU to ΪΪ5 for data input, e55 for input for controlling three-state data signal drivers UU to D5 ·

The arithmetic and logic unit ALJ of the processor consists of central processor circuitry comprising the first to eighth central processor circuitry CP01 to CP08, a constant multiplexer comprising the first and second quadruple two-input multiplexer of the MP1 and the MP2, a constant generator comprising the first to twelfth three-input circuit of NT1. to NT12 of the logical product negation type, second to fifth flip-flop KJK2 to KJK5 type JK, third to seventh inverter IN3 to IN7, and second two-input logic product negation ND2, from the decimal transmission circuit including first flip-flop KJK1 type JK and a second inverter IN1 and IN2 and a first two-input ND1 type circuit

227 440 logic product negation, from a transfer acceleration circuit comprising a transfer acceleration PUP circuit, an 8-input logic-product negation NO circuit, eighth to tenth inverters IN8 to IN10.

The processor control unit RPU generates in its ROM a microinstruction as shown in Fig. 3. From this microinstruction, the control signals F0 to F6 are input to the arithmetic and logic unit ALJ for the input of the operation code to be performed in the central processor circuitry CP01 to CP08. Central processor circuits alone cannot perform decimal operations, but only binary additions or a complete set of logical operations. The control signals F0 to F6 are set at the inputs of the processor arithmetic and logic unit ALJ at time T3 (Fig. 4)

At time T7, the controller 60 of the processor sends a signal CLK2 which causes the operation result to be transcribed, for example, to an internal AC register (not shown) in the central processor circuits and this result appears as signals signály) D to D15. Furthermore, signals K1 to K15 and the DEC signal are supplied from the processor control unit. The DEC signal decides whether to perform binary or decimal operations in the processor's arithmetic and logic unit ALJ. If at DEC T3 the DEC signal is in a logic zero state, a standard binary operation is performed. In this case, the DEC signal in the logic zero state causes the constant multiplexer to be set such that all sixteen bits of the constant K1 to K15 are routed directly to the inputs of the central processor circuits through the constant multiplexer. In a decimal addition operation, two decimal numbers are added, each with four digits in code 8421. Before the operation begins, the first decimal number is in the internal register R1 (not shown) and the second decimal number in the internal register AC of the central processor circuits. Both digits of the lowest order will be added using CPO1, CPO2, CP1, NT10, NT11, NZ12 and KJK5 circuits. two more higher digits using CPO3 circuits. CP04. ČMPl. NT7, NT8, NT9 and KJK4, two more digits using CP05 circuits. CP06, ČMP2. NT4. NT5, NT6 and KJK3 and last digits of the highest order using circuits CP07, CP08, ČMP2, NT1,

NT2, NT3 and KJK2. The decimal addition is performed in five steps.

In the first step, the operation R1 + AC · - «* AC is set at T3 by the signals F0 to F6, and the DEC is set to logic zero. The arrival of the CLK2 signal in this first step adds the two decimal numbers binary and the result will be in the AC

227,440 signals 15U to D15. Simultaneously with the CLK2 signal, it stores four transmissions generated between decimal orders in one-bit transmission and using its signals 0Ϊ2, CI4, cell £ '. In the second step, at time T3, the AC + K - * AC operation is set using signals F0 to F6 and the DEC signal is set to logic one. The arrival of the ClKŽ signal in this second step will be done by means of the constant generator +6 correction only in those decimal orders in which the transmission of CT, U2, UJ, U4 signals originated or in which the result of the previous step is greater than 9. circuits KJK5, KJK4. KJK3, KJK2. If, after the second step, any decimal order is greater than 9, the +6 correction is performed again in the third step using the constant generator. By analogy, the fourth and fifth steps are conducted. After completion of the fifth step with the CLKŽ signal, the decimal addition result on signals výsledek to Sl5 and the decimal transmission event on the CCr signal. By repeating the process, any number of decimal orders can be performed, and successive results can be stored and retrieved from the main memory of the processor using data signals SKJ to M1 $, Ι5Φ to 1515, and address signals Σ0 to AI4. For better understanding, a positive representation of some signals is used in the timing diagram of FIG.

The connection of the arithmetic and logic unit ALJ of the processor according to the invention can be used in desktop computers and in particular in intelligent terminals.

Claims (1)

SUBJECT OF THE INVENTION 227 440 Connection of an arithmetic and logic unit of a processor, in particular for an intelligent terminal, to the central processing circuitry and to the transmission acceleration circuit, characterized in that the first output (132) to accelerate transmission of the first central processor circuit (CP01) is connected to the first input (715) a pair of accelerate transmission circuit inputs (OUP) to accelerate the transmission, a second accelerate transmission output (131) of the first central processor circuit (CP01) is connected to the second input (716) of the first pair the right central output (GPO1) shift output (133) is connected to the input (76) to set to the second JK type flip-flop (KJK2), via the fourth inverter (IN4) to the logic zero input (78) a second flip-flop (KJK2) of the JK type, to the eighth circuit transfer output (738) at the same time the thirty-third wiring output (033), the first data output (134) of the first central processor circuit (CP01) is simultaneously the seventeenth wiring output (017), the second data output (135) of the first central processor circuit (CP01) is connected to the third input of the twelfth logic product of the 12th input (NT12) type and simultaneously form the eighteenth wiring output (018), the first memory address output (136) of the first central processor circuit (CP01) forming the first wiring output (01), the second memory address output (137) the first central processor circuit (CP01) simultaneously forms the second circuit output (02), the first transmission acceleration output (182) of the second central processor circuit (CP02) is connected to the first input (713) of the second pair of circuit acceleration inputs (OUP) for a second output (181) to accelerate the transmission of the second central the processor circuit (CP02) is coupled to the second input (714) of the second pair of accelerator transmission inputs (OUP) to accelerate the transmission, the right shift output (183) of the second central processor circuit (CP02) is coupled to the right shift input (109) of the first the central processor circuit (CP01), the first data output (184) of the second central processor circuit (CP02) is connected to the second input of the twelfth logic product of the 12th input (NT12) type and simultaneously forms the nineteenth wiring output (019); ) of the second central processor28 The 227 440 ho circuit (CP02) is connected to the third input of the tenth three-input circuit (NT10) of the logic product negation type and simultaneously forms the twenty output (020) wiring, the first memory address output (186) of the second central processor circuit (CP02) (03), the second memory address of the second central processor circuit (CP02) is simultaneously forming a fourth circuit output (04), the first output (232) for accelerating transmission of the third central processor circuit (CP03) is connected to the first input (711) ) a third pair of Accelerate Circuit Transfer Inputs (OUP) to accelerate the transfer, a second output (231) of Accelerate Transfer of the third central processor circuit (CP03) is coupled to the second input (712) of the third pair of Accelerate Circuit Transfer Inputs (OUP) to accelerate For the transmission, the right shift output (233) of the third central processor circuit (CP03) is coupled to the v a second central processor circuitry (CP02) shift (159), a first data output (234) of the third central processor circuit (CP03) at the same time being the twenty-first wiring output (021), a second data output (235) of the third central processor circuit (CP03) is connected to the third input of the ninth three-input circuit (NT9) of the negation of the logical product type and simultaneously forms the twenty-second wiring output (022), the first output (236) of memory address of the third central processor circuit (CP03) the memory address output (237) of the third central processor circuit (CP03) simultaneously forms the sixth wiring output (06), the first output (282) to accelerate transmission of the fourth central processor circuit (CP04) is connected to the first input (709) of the fourth pair of acceleration inputs OUP to accelerate transmission, second output (281) to accelerate the transmission The fourth central processing circuit (CP04) transmission is coupled to the second input (710) of the fourth transmission accelerating input (OUP) input, the right shift central output (CP04) output (283) is coupled to the input (209) ) to the right of the third central processor circuit (CP03), the first data output (284) of the fourth central processor circuit (CP04) is connected to the second input of the ninth three-input logical product type (NT9) and forms the twenty-third circuit output (023). the second data output (285) of the fourth central processor circuit (CP04) is coupled to the third input of the seventh three-input circuit (NT7) of the negation product type29 and simultaneously forms the twenty-fourth circuit (024) circuit, the first output (286) of the fourth central processor memory address The circuit (CP04) also forms the seventh output (07) behind coupling, the second memory address output (287) of the fourth central processor circuit (CP04) is simultaneously the eighth wiring output (08), the first output (332) to accelerate the transmission of the fifth central processor circuit (CP05) is connected to the first input (707) of the fifth a pair of accelerate transmission circuit inputs (OUP) to accelerate transmission, a second output (331) to accelerate the transmission of the fifth central processor circuit (CP05) is coupled to a second input (708) of the fifth accelerator transmission input pair (OUP), the fifth central processor circuitry (CP05) shift output (333) is coupled to the fourth central processor circuitry (CP04) shift right input (259), and the fifth central processor circuitry (CP05) first data output (334) simultaneously forms the twenty-fifth output (025) ), the second data output (335) of the fifth central processor circuit (CP05) is connected to t the third input of the sixth three-input circuit (NT6) of the type of negation of the logical product and simultaneously forms the twenty-sixth output (026) of the wiring, the first output (336) of memory address of the fifth central processor circuit (CP05) the memory addresses of the fifth central processor circuit (CP05) simultaneously form the tenth output circuit (010), the first output (382) to accelerate the transmission of the sixth central processor circuit (CP06) is connected to the first input (705) OUP) to accelerate transmission, the second transmission acceleration output (381) of the Sixth Central Processor Circuit (CP06) is coupled to the second input (706) of the sixth transmission acceleration input (OUP) port, to the right of the sixth right shift a central processor circuit (CPQ6) is coupled to the right shift input (309) of the fifth c entral processor circuit (CP05), the first data output (384) of the sixth central processor circuit (CP06) is connected to the second input of the sixth logical product negation type (NT6) and forms the 27th wiring output (027), the second data output ( 385) the sixth central processor circuit (CP06) is coupled to the third input of the fourth three-input logic product negation type (NT4) and simultaneously forms the twenty-eight wiring output (028), the first memory address (386) of the sixth central processor memory (CP06) forming simultaneously the eleventh circuit output (011), the second memory address output (387) of the sixth central processor circuit (CP06) simultaneously forming the twelfth circuit output (012), the first output (432) for accelerating transmission of the seventh central processor circuit (CP07) a first input (703) of a seventh pair of inputs to accelerate the pr the second accelerator transmission output (431) of the seventh central processor circuitry (CP07) is connected to the second input (704) of the seventh pair of transmission accelerator transmission inputs (OUP), output (433) The right feed of the seventh central processor circuit (CP07) is connected to the feed input (359) of the right feed of the sixth central processor circuit (CP06), the first data output (434) of the seventh central processor circuit (CP07) being the twenty-ninth output (029). the data output (435) of the seventh central processor circuit (CP07) is connected to the third input of the third three-input circuit (NT3) of the logical product negation type and simultaneously forms the thirtieth output (030) of wiring; ) simultaneously form the thirteenth wiring output (013), the second memory address output (437) the seventh central processor circuit (CP07) simultaneously forms the fourteenth circuit output (014), the first output (482) to accelerate the transmission of the eighth central processor circuit (CP08) is connected to the first input (701) of the eighth pair of inputs for the acceleration, circuit transmission (OUP) to accelerate transmission, the second transmission acceleration output (481) of the eighth central processor circuitry (CP08) is coupled to the second input (702) of the eighth transmission accelerator input (OUP) input, the right shift output (483) of the eighth central processor the circuit (CP08) is connected to the right shift input (409) of the seventh central processor circuit (CP07), the first data output (484) of the eighth central processor circuit (CP08) is connected to the second input of the third three-input circuit (NT3) it also forms the thirty-first wiring output (031), the second data output (485) of the eighth center The first processor input (NT1) of the logic product type (NT1) is connected to the third input of the first three-input circuit (NT1) and forms the thirty-second wiring output (032), the first memory address output (486) of the eighth central processor circuit (CP08). (015), the second output (487) of the address 31 of the eighth central processor circuit (CP08) simultaneously forms the 16th circuit output (016), the zero output (072) of the first JK type flip-flop (KJK1) forms the thirty-fourth output ( Wiring, the second constants and masking bits input (117) of the first central processor circuit (CP01) simultaneously form the first wiring input (1), the first constants and masking bits input (166) of the second central processor circuit (CP02) simultaneously form the fourth input ( 4) wiring, a first input (508) of a first multiplexer of a first quadruple two-input The multiplexer (CMP1) simultaneously constitutes the second wiring input (2), the two-input first input (506) of the second multiplexer first quadrupleV multiplexer (CMP1) simultaneously forms the third wiring input (3), the first input (504) of the third multiplexer first quadruple two-input multiplexer ) simultaneously form the sixth input (6), the first input (502) of the fourth multiplexer of the first quadruple two-input multiplexer (CMP1) simultaneously form the seventh input (7), the second constant input (217) and masking bits of the third central processor circuit (CP03) simultaneously, the fifth wiring input (5), the first constants and masking bits input (4) of the fourth central processor circuit (CP04) simultaneously form the eighth wiring input (8), the second constants input (317) and masking bits of the fifth central processor circuit (CP05) are simultaneously the ninth input (9) of the wiring, the first input (366) to onstant and masking bits of the sixth central processor circuit (CP06) simultaneously form the twelfth wiring input (12), the first input (608) of the first multiplexer of the second quadruple dual input multiplexer (CMP2) simultaneously form the tenth wiring input (10), the first input (606) of the second multiplexer the second quadruple two-input multiplexer (CMP2) simultaneously forms the eleventh wiring input (11), the first input (604) of the third multiplexer second quadruple two-input multiplexer (ČMP2) simultaneously forms the fourteenth wiring input (14), the first input (602) (CMP2) simultaneously form the fifteenth wiring input (15), the second input (417) of the constants and masking bits of the seventh central processor circuit (CP07) simultaneously form the thirteenth wiring input (13), the first constant input (466) and masking bits of the eighth central processor The first and second quadruple two-input multiplexer (ČMP1, ČMP2) are connected to the first input of the second two-input circuit (ND2) of the logic product type, on the one hand through the second inverter (IN2) to the first input of the first two-input circuit (ND1) of the type of negation of the logical product and simultaneously form the seventeenth input (17) of the wiring, the first inputs (102,152, 202.252.302.352.402.452) to determine the microinstructions of the first to eighth central processor circuitry (CP01 to CP08) simultaneously comprise the eighteenth wiring input (18), the second inputs (103,153, 203.253.303.353.403.453) to determine the microinstructions of the first to eighth central processor circuitry (CP01 to CP08) are coupled to the first input of the eight-input logic product negation circuit (NO) and simultaneously form the nineteenth wiring input (19), the third inputs (104,154,204,254,304,354,404, 4543 to determine the microinstructions of the first to eighth central processor circuitry (CP01 to CP08) are connected to the second input of the eight-input logic product negation circuit (NO) and form simultaneously the twentieth wiring input (20), the fourth inputs (105,155,205,255, 305,355,405,455) to eighth central processor circuitry (CP01 to CP08) are connected to the third input of the eight-input logic product negation type and simultaneously form the twenty-first wiring input (21), the fifth inputs (106,156,206,256,306,356,406,456) to determine the microinstructions of the first to eighth central processors The circuits (CP01 to CP08) are connected via the eighth inverter (IN8) to the fourth input of the eight-input logic product negation type (NO) and form the twenty-second wiring input (22), the sixth inputs (107,157,207,257,307,357,407,457). the processor circuitry (CP01 to CP08) are connected via the ninth inverter (IN9) to the fifth and sixth inputs of the eight-input, non-logical product type and form the twenty-third wiring input (23), the seventh inputs (108,158,208,258,308,358,408,458) up to the eightth central processor circuitry (CP01 to CP08) are connected via the tenth inverter (IN10) to the seventh and eighth inputs of the eight-input logic product negation type (NO) and form the twenty-fourth wiring input (24), the circuit input (717) (OUP) for accelerating transmission is connected to the right feed axis input (459) of my central processor circuit (CP08), to the transmission input (118) of the first central processor circuit (CP01) and simultaneously forms the twenty-fifth wiring input (25), the clock input (72) of the first JK type flip-flop (KJK1) simultaneously (26) connection, clock inputs (77,82,87,92) of second to fifth flip-flop (KJK2 to KJK5) of JK type are connected via third inverter (IN3) to second input of first and second circuit (ND1, ND2) type of logical product negation, firstly to the clock inputs (101,151,201,251,301,351,401,451) of the first to eighth central processor circuit (CPO1 to CP08) and simultaneously form the twenty-seventh input (27) wiring, the second data input (113) from the memory of the first central processor circuit (CPO1) at the same time the twenty-eighth wiring input (28), the first data input (112) from the memory of the first central processor circuit (CPO1) simultaneously forms the twenty-th wiring input (29), the second data input (163) from the memory of the second central processor circuit (CPO2) simultaneously forms the thirtieth wiring input (30), the first data input (162) from the memory of the second central processor circuit (CP02) simultaneously forms the thirty first the wiring input (31), the second data input (213) from the memory of the third central processor circuit (CP03) is simultaneously the thirty-second wiring input (32), the first data input (212) from the memories of the third central processor circuit (CP03) is the thirty-third the wiring input (33), the second data input (263) from the memory of the fourth central processor circuit (CP04) is simultaneously the thirty-fourth wiring input (34), the first data input (262) from the memory of the fourth central processor circuit (CP04) is the thirty-fifth the wiring input (35), the second data input (313) from the memory of the fifth central processor circuit (CP05) are simultaneously three the thirty-sixth wiring input (36), the first data input (312) from the memory of the fifth central processor circuit (CP05) is simultaneously the thirty-seventh wiring input (37), the second data input (363) from the memory of the sixth central processor circuit (CP06) the thirty-eight wiring input (38), the first data input (362) from the memory of the sixth central processor circuit (CP06) is simultaneously the thirty-ninth wiring input (39), the second data input (413) from the memory of the seventh central processor circuit (CP07) Forty wiring input (40), the first data input (412) from the memory of the seventh central processor circuit (CP07) simultaneously constitutes the forty-first wiring input (41), the second data input (463) from the memory of the eighth central processor circuit (CP08) simultaneously the second wiring input (42), the first data input (462) from the memory of the eighth central processor circuit (CP08) the first forty-third wiring input (43), the second external device input (115) of the first central processor circuit (CP01) simultaneously constitutes the forty-fourth wiring input (44), the first external device input (114) of the first central processor circuit (CPO1) simultaneously forty-fifth wiring input (45), second external device input (165) of the second central processor circuit (CPO2) simultaneously constitutes forty-six wiring input (46), first external device input (164) of second central processor circuit (CPO2) is simultaneously forty-seventh the wiring input (47), the second external processor (CPO3) external device input (215) simultaneously constitutes the 48th wiring input (48), the third third processor central unit (CPO3) external V3tup (214) simultaneously constitutes the ninety-eight ( 49) involved , the second input (265) of the external devices of the fourth central processor circuit (CPO4) simultaneously forms the fifty wiring input (50), the first V3tup (264) of the external devices of the fourth central processor circuit (CP04) simultaneously forms the fifty first wiring input (51), the second input (315) external devices of the fifth central processor circuit (CP05) simultaneously form fifty second wiring input (52), the first input (314) of external devices of the fifth central processor circuit (CP05) simultaneously form fifty third wiring input (53), second input (365) the external devices of the sixth central processor circuit (CP06) simultaneously form the fifty-fourth wiring input (54), the first input (364) of the external devices of the sixth central processor circuit (CP06) simultaneously form the fifty-fifth wiring input (55), the second input (415) equipment of the seventh central process of the seventh central processor circuit (CP07) is simultaneously the fifty-seventh wiring input (57), the second input (465) of the external devices of the eighth-central processor circuit (CP08) is also the fifty-eight wiring input (58), the first input (464) of the external devices of the eighth central processor circuit (CP08) is also the fifty-ninth wiring input (59), inputs (119,169,219,269, 319,369,419,469) the eighth central processor circuit (CP01 to GP08) is simultaneously a sixtieth wiring input (60), the memory addressing inputs (120,170,220,270,320,370, 420,470) of the first to eighth central processor circuits (CP01 to CP08) are connected to the zero potential input terminal (61), grounding inputs (110, 160,210,260,310,360,410,46 0) the first to eighth central processor circuits 35 (GPO1 to CP08) are connected to the zero potential input terminal (61), the power inputs (111,161,211, 261,311,361,411,461) of the first to eighth central processor circuits (GPO1 to CP08) are connected to the input terminal (62 positive voltage, the first transmission acceleration output (73D) (OUP) is connected to the transmission input (168) of the second central processor circuit (GPO2), the second transmission acceleration output (O32) (732) is connected to the input ( 218) transmission of the third central processor circuit (CPO3), further to the input (91) for setting the logical one of the 5th flip-flop (KJK5) of the JK type and via the seventh inverter (IN7) to the input (93) (KJK5) of the JK type, the third transmission transfer output (733) for accelerating transmission is connected to the transmission input (268) of the fourth central processor The fourth transmission circuit output (734) for accelerating transmission is connected to the transmission input (318) of the fifth central processor circuit (CPO5), and to the input (86) for setting the logical one of the fourth flip-flop ( KJK4) of the JK type and through the sixth inverter (IN6) to the input (88) to set the logic zero of the fourth flip-flop (KJK4) of the JK type, the fifth transmission transfer output (735) 368) transmission of the sixth central processor circuit (CPO6), the sixth transmission circuit output (736) for accelerating transmission is connected to the transmission input (418) of the seventh central processor circuit (CPO7), longer to the input (81) to set the JK type third flip-flop (KJK3) and via the fifth inverter (IN5) to the input (83) to set to the logical zero of the JK type third flip-flop (KJK3), the seventh circuit transfer output (737) the transmission is connected to the transmission input (468) of the eighth central processor circuit (CPO8), the eight-input circuit output (NO) of the logic product type is connected to the input (720) for the transmission transmission output (OUP) (719) the transmission acceleration circuit (OUP) is connected to the zero potential input terminal (61) and its power input (718) is connected to the positive voltage input terminal (62), the first multiplexer output (531) of the first four-fold dual-input multiplexer ( The MP1) is coupled to the first constant input and masking bits of the first central processor circuit (CP01), the second multiplexer output (532) of the first quadruple two-input multiplexer (MP1) is coupled to the second constant input and masking bits of the second a central processor circuit (GPO2), a third multiplexer output (533) of a first quadruple dual-input multiplexer ( Is connected to the first input (216) of the third central processor circuit (CPO3) constants and masking bits, the output (534) of the fourth multiplexer of the first quadruple two-input multiplexer (ČMP1) is connected to the second constant input (267) circuit (CPO4), first multiplexer output (631) of second quadruple two-input multiplexer (ČMP2) is coupled to first input (316) of constants and masking bits of fifth central processor circuit (CPO5), second multiplexer output (632) of second quadruple two-input multiplexer (ČMP2 is connected to the second input (367) of the sixth central processor circuit (CPO6), and the third nultiplexer output (633) of the second quadruple two-input multiplexer (CMP2) is connected to the first constant input (416) and masking bits of the seventh central processor circuit (CPO 7), the fourth multiplexer output (634) of the second quadruple dual-input multiplexer (CMP2) is coupled to the second constant input (467) and masking bits of the eighth central processor circuit (CP08), inputs (512,612) to control the multiplexer outputs of the first and second quadruple dual input multiplexers (ČMP1, ČMP2) are connected to the zero potential input terminal (61), the ground inputs (511,611) of the first and second quadruple two-input multiplexer (ČMP1, ČMP2) are connected to the zero potential input terminal (61) and their power inputs (510,610) are connected to the positive voltage input terminal (62), the output of the first two-input logic product (ND1) circuit is connected to the reset input (74) of the first JK type flip-flop (KJK1), whose logic zero input (73) is connected to the input terminal (61) of the zero potential, output of the second two - input circuit (ND 2) logic product negation type is connected to the JK type second to fifth flip-flop (KJK2 to KJK5) setting inputs (79, 84,89,94), the JK type one output (076) of the second flip-flop (KJK2) is connected to the first and a second input of a first three-input logic product (NT1) type and to a first input of a third three-input logic product (NT3) type, whose output is connected to a third input of a second three-input logic product type (NT2) the logic product negation circuit (NT1) is connected to the first and second inputs of the second 2-input logic product negation circuit (NT2), the output of which is connected to the second input (605) of the third multiplexer second quadruple two-input multiplexer (ČMP2) (603) a fourth multiplexer of a second quadruple two-input multiplexer (ČMP-2) and via a first inverter (INI) to the input (71) for setting to the first JK type 1 flip-flop (KJK1), the output of the JK type third flip-flop (081) (081) is connected to the first and second inputs of the Fourth Negative Type and to the first input of the sixth three-input circuit (NT6) of the type of negation of the logical product whose output is connected to the third input of the fifth three-input circuit (NT5) of the type of negation of the logic product. and a second input of the fifth three-input logic product negation circuit (NT5), the output of which is connected to the second input (609) of the first multiplexer of the second quadruple two-input multiplexer (CMP2) and the second input (607) of the second multiplexer the JK type fourth flip-flop (KJK4) output (086) is connected to the first and second inputs of the seventh three-input logic product (NT7) and to the first input of the ninth three-input logic product (NT9), the output of which is connected to the third input of the eighth three-input logic product (NT8) the output of the seventh three-input logical product negation circuit (NT7) is connected to the first and second inputs of the eighth three-input logical product negation circuit (NT8), the output of which is connected to the third multiplexer second input (505) of the first quadruple two-input multiplexer (ČMP1) second input (503) of the fourth multiplexer of the first quadruple two-input multiplexer (CMP1), the one output (091) of the fifth flip-flop (KJK5) type JK is connected to the first and second inputs of the tenth three-input circuit (NT10) three input circuit (NT12) ty pu negation of logic product whose output is connected to the third input of the eleventh three-input circuit (NT11) of the logic product negation type, the output of the tenth three-input circuit (ΝΤ1Ό) of the logic eouč negation type is connected to the first and second inputs of the eleventh three-input circuit (NT11) a product whose output is connected to the second input (509) of the first quadruple two-input multiplexer (CMP1) and to the second input (507) of the second quadruple two-input multiplexer (CMP1).