CS209751B1 - Circuit for quick jump to microprogram branches according to length and position of operand - Google Patents

Abstract

A circuit for fast branching into microprogram branches according to the length and position of the operand, intended for microprogram-controlled processors. The effect is to increase the speed of contact between the computer's operational processor and the computer's memory. The invention allows, in a single microinstruction, to modify the address of the next microinstruction by the length of the operand for which contact is to occur, and the evenness or oddness of the address of the start of that operand. This results in a microprogram branching into branches that contain a sequence of commands for contact, created exactly for the given length and position of the operand. The acceleration of contact consists in the fact that the said branching takes place at once, during a single microinstruction. The field of application is computer technology, microprogram-controlled operational processors. It is suitable only for simpler processors that do not allow multiple parallel operations in a single microinstruction.

Description

The invention relates to a circuit which, in connection with a suitable microprogram, enables a quick jump to the branches of the microprogram, depending on the length of the operand and the even or odd address of its beginning.

Most computers perform, among other simpler operations, a group of operations with a variable or different distance of operands, which are read from the operational memory, processed in the operational unit and the result is written back to the operational memory. Reading the operands and writing the result will take place in a general number of contacts with the memory, depending on the computer design and the length of the operands. The control microprogram must contain cycles for contacting the memory, in which records are kept of the not yet read or written parts of the operand, and the cycle is repeated until the length of the operand is exhausted. Before starting such a cycle, it is usually necessary to determine the position of the beginning of the operand in relation to the structure that can be read from the memory at once, or written to the memory. In most designs, the evenness or oddness of the address of the beginning of the operand is decisive. It is usually read or written in double bytes, i.e. 16 bits, but the address must be even. If the address is odd, it is necessary to first read or write one byte, i.e. 8 bits, and then continue the communication in two-byte cycles. Since the end of the communication with the memory can be two-byte, if the operand ends at an odd address, or one-byte, if the operand ends at an even address. A communication for one byte lasts the same time as a communication for two-byte cycles.

Syllable access is therefore disadvantageous in terms of speed. The cycle for accessing memory requires preparation and contains a secondary activity that slows down the access to memory. The time loss is especially significant if the operands are short.

For this reason, it seems advantageous to solve memory access for short operands by jumping to branches containing one or several consecutive memory access instructions that exactly match the length of the operand and the evenness or oddness of its start address. In such a solution to memory access, the only preparatory activity is the selection of a suitable microprogram branch. This selection can be made by successively testing the length of the operand and testing the start address of the operand for evenness. Such a decision is slow and invalidates an otherwise advantageous solution to memory access.

The current circuit for performing the microprogram branch selection consists of test circuits connected to the control memory address arithmetic circuits, which together ensure the final achievement of the address of the start of the appropriate microprogram branch, but this happens by successive address changes over multiple steps.

The described deficiency, that is, the gradual and therefore slow selection of the microprogram branch, is eliminated by a circuit for a quick jump to the microprogram branches according to the length and position of the operand, according to the invention, the essence of which is that the arithmetic unit is equipped with an input for the sum of the microinstruction address with the operand length code, to which the output of the operand length code register is connected, further the arithmetic unit is equipped with an input for modifying the microinstruction address of the evenness or oddness of the operand address, to which the output of the operand address register is connected and further the arithmetic unit is equipped with another input connected to the microinstruction address register and the output of the arithmetic unit is connected to the control memory input and to the microinstruction register input.

By connecting the parts of the circuit for fast jump as mentioned above, the formation of the microinstruction address is influenced by the contents of the operand length code register and the contents of the selected part of the operand address register, thus enabling the selection of a microprogram branch according to the length and position of the operand within a single microinstruction. This selection is significantly faster than the sequential selection imposed by the existing circuit.

The attached drawing schematically shows a circuit according to the invention.

The circuit according to the invention consists of an arithmetic unit J., a microinstruction address register 2, an operand length code register J, an operand address register £ and a control memory 2. At the input

102 arithmetic unit J_ is connected to the output of register 2 of the microinstruction address, to the input

The output of the register J of the operand length code is connected to the input 103 of the arithmetic unit and the output of the register 4 of the operand address is connected to the input 104 of the arithmetic unit J. The output of the arithmetic unit i is connected to the input of the register 2 of the microinstruction address and to the input of the control memory 5,.

The arithmetic unit, assuming that the current microinstruction is a fast jump, creates the address of the next microinstruction by adding the following four binary numbers:

ones, generated inside the arithmetic unit J.

the address of the current microinstruction, stored in the microinstruction address register 2, the operand length code, stored in the operand length code register J, a variable characterizing the evenness or oddness of the address of the start of the operand, this variable being created inside the arithmetic unit J based on the operand address, stored in the operand address register £.

The address of the new microinstruction thus created is both stored in the microinstruction address register 2 and used in the control memory £ to select a new microinstruction. The arithmetic unit _£ creates the address of the next microinstruction by adding the four numbers mentioned above only if the current microinstruction is a fast jump. If the current microinstruction is a sequential one, the arithmetic unit _1_ creates the address of the new microinstruction only by adding an internally generated one to the address stored in the microinstruction address register 2, which is a common function. For some other microinstructions, the address of the new microinstruction is created in a completely different way, which is not shown in the figure. When executing a microinstruction other than a fast jump, only known parts of the circuit are used.

The following table TAB. 2 is included, showing an example of a microprogram in which the fast jump enabled by the circuit according to the invention is used. For this example, the operand length is limited to 4 bytes. A longer operand would be read using a cycle, which is not shown in TAB. 2. The circuit according to the invention adds a binary increment to the microinstruction address stored in register 2 of the microinstruction address, which is defined as follows:

for even address of the start of the operand ... 1 + length code + 0000 for odd address of the start of the operand ..1 + length code + 0100

An overview of the binary increments of the microinstruction address for all situations of the above example is given in Table TAB. 1.

start address operand length length code binary increment decadal addition- operand (syllable) addresses address growth even 1 00 0001 1 even 2 01 0010 2 even 3 10 0011 3 even 4 11 0100 4 odd 1 00 0101 5 odd 2 01 0110 6 odd 3 10 0111 7 odd 4 11 1000 8

TABLE 1

TABLE 2.

The address increment in decimal form is shown only for better clarity. The circuit according to the invention works in binary. A single microinstruction 201 activates the circuit according to the figure, which adds to the address of the current microinstruction 201 the increment according to TAB. 1. Microinstruction 201 is followed in close succession in the microprogram by eight jumps 211 to 218. The address sequence of microinstructions 201. 211, 212. 213. 214. 215. 216. 217 and 218 is graphically emphasized by always being placed lower in TAB. 2. The beginnings of the sequences of microinstructions after the jumps can be located anywhere in the control memory and the height of their placement in TAB. 2 does not mean anything. Microinstruction 201 selects one of the eight jumps 211 to 218 and thus also selects the appropriate branch of the microprogram. For example, if the operand length is 4 bytes and its start address is even, the circuit according to the figure, activated by microinstruction 201, adds an increment of 4 to the address of this microinstruction, so that jump 214 is performed, followed by microinstructions 224 and 234. The operand is read twice in two-byte increments. Another example. The operand length is 4 bytes, the operand starts at an odd address. The circuit according to the invention, activated by microinstruction 201, adds an increment of 8 to the address of this microinstruction, so that jump 218 is performed, followed by microinstructions 228, 238 and 248. The operand is read three times.

The circuit for performing a fast jump to microprogram branches based on the length and position of the operand is designed for smaller computers whose technical equipment does not normally allow for performing multiple operations in parallel in a single microinstruction.

Claims (1)

SUBJECT OF THE INVENTION Circuit for quick program branching according to the length and position of the operand, characterized in that the arithmetic unit (1) is equipped with an input (103) for the sum of the microinstruction address with the operand length code to which the output of the operand length code (3) furthermore, the arithmetic unit (1) is provided with an input (104) to modify the microinstruction address by the evenness or oddity of the operand address to which the output of the register (4) is connected. the operand address and further, the arithmetic unit (1) is equipped with an additional input (102) connected to the microinstruction address register (2) and the output of the arithmetic unit (1) is connected to the control memory input (5) and microinstruction address register (2) .