CS196035B1 - Connected to highlight graphical information on the display screen - Google Patents

Abstract

The invention relates to a circuit for highlighting graphic information on the screen of a display unit

Description

The invention relates to a circuit for highlighting graphical information on a display screen.

In computing and the like, a display unit with a screen is used as an output device for information of the operator, on the screen of which the luminance modulation screen obtains the display of alphanumeric or other graphic characters, usually arranged in several text lines. In order to inform the operator to which location of the screen to write the desired characters of the information, this field of unrecorded characters is pre-marked by writing suitable marks, such as x marks, or by brightening the entire field. when the information is entered, this indication disappears and is replaced by the information characters.

When writing information, the operator is also forced to monitor alternately the source materials from which the information is drawn and the screen where the information is transmitted by the keyboard. To make it easier for the bperator to find the location where the next character of the information will be written, the address is indicated with an address mark, for example, as a horizontal line below the location, blinking the brightness of the location, blinking the entered character or displaying it negatively.

The disadvantage of marking an array of unregistered characters with tags is that the operator's orientation is impaired if the written character is information similar to that tag. In addition, this method does not allow marking of information already entered. Similarly, with the current method of displaying address marks, the disadvantage is the slow orientation of the operator when searching for an address mark in the form

196 0J5

188 838 underline of the marked place, possibly impaired readability of the text if the address mark is indicated by flashing or negative display.

These drawbacks are eliminated by the circuitry for highlighting graphical information on the screen of the display unit according to the invention, which is characterized in that the basic input of the first D-type flip-flop simultaneously constitutes the first input, wiring and clock input of the first D-type flip-flop. are connected and form the third wiring input, the setting input, and the reset input of the first D-type flip-flop are connected and connected to a logic 1 source, the one output of the first D-type flip-flop is connected to the second input of the first whereas its zero output is connected to the reset input of the second D-type flip-flop and the basic input of the second D-type flip-flop simultaneously forms the second wiring input, while its setting input is connected to the logic 1 source and its zero output is connected to the second input of the second dvo a logic product negation input circuit and a third input of a first three-input logic product negation circuit, wherein the first input of the first two input logic product negation circuit simultaneously forms the fourth input input, while its output is connected to the first input of the second two input logic product negation circuit; to the second input of the first three-input logic product negation circuit and the output of the second two-input logic product negation circuit is connected to the first input of the third two-input logic product negation circuit, whose output is simultaneously the first output connected and the second input connected to the first input of the first three-input logic product negation circuit and simultaneously form the sixth input circuit, while the output of the first three-input logic product negaée circuit is connected to the first input of the fourth two-input logic product negation circuit, the output of which is simultaneously the second wiring output and the second input of the fourth two-input logic product negation circuit forms the fifth wiring input at the same time.

The advantage of the wiring according to the invention is its simplicity and easy orientation of the operator. It also brings a uniform marking of the field of registered characters and unregistered places as well as a uniform marking of the address mark on already registered and unregistered places. The enhancement of the graphical information solved by the invention has also brought about a substantial improvement in reading working conditions, in that the operator's eyes are less stressed.

An example of a wiring diagram for highlighting graphical information on a display screen of the present invention is shown in the accompanying drawings, in which FIG. 2 is a graphical representation of an address mark; - a marking mark to highlight a written or unwritten place and information sign; and FIG. 3 a timing diagram of the engagement.

The basic input 11 of the first D-type flip-flop KOI (FIG. 1) for the P1 signal simultaneously forms the first wiring input 6, connectable to a controller (not shown). The clock input 12 of the first D-type flip-flop of the KOI circuit and the clock input 22 of the second flip-flop of the KO2 type-D signal for the H1 signal are coupled to form a third input 3 connected to a time source shown. The adjusting input 14 and the reset vs. input 13 of the first D-type flip-flop KOI are connected and connected to the positive pole * of the power source, such as

1 »· 03S logic 1. The one output 101 of the first D-type flip-flop KOI is connected to the second input of the first two-input logic product negation type NSD1, while its zero output 10g is connected to the reset input 23 of the second flip-flop. input 21 of second flip-flop K02 type D for signal P2 simultaneously constitutes second wiring input 2, connectable to a controller (not shown), while its setting input 24 is connected to the positive pole + power supply, as a logic 1 source.

a second D-type flip-flop K2 is connected to a second input of a second two-input logic product negation type NSD2 and to a third input of a first three-input logic product negation type NST1. The first input of the first two-input logic product negation type NSD1 for H2 signal simultaneously forms the fourth wiring input 4, connectable to a time source not shown, while its output is connected to the first input of the second two-input logic product negation type NSD2 and to the second input of NST1 rubber type of negation of logical product. The output of the second two-input logic product negation type NSD2 is connected to the first input of the third two-input logic product negation type NSD3, whose output for the JAS signal simultaneously constitutes the first output 01 connected, connectable to a display unit not shown. The second input of the third two-input logic product negation circuit NSD3 for the OS signal is coupled to the first input of the first three-input logic product negation circuit MSTI and simultaneously forms the sixth input 6, connectable to a video signal source (not shown). The output of the first three-input logic product negation NST1 is connected to the first input of the fourth two-input logic product negation NSD4, whose output for the UPS signal is simultaneously the second wiring output 02, connectable to a display unit not shown. The second input of the fourth two-input NSD4 logic product negation type for the H3 signal is simultaneously the fifth wiring input 5, connectable to a time source not shown.

The positive edge of the H1 signal sets both KOI flip-flops well in advance of the displayed character. K02 type D according to the condition inputs, i.e. according to the first input 1, where the logic level P1 signal is applied and which means displaying the address mark in the following character and according to the second input 2, where the logic level P2 signal is supplied * 1a showing the indication in the following feature, wherein the coupling between the zero output 102 of the first D-type flip-flop and the reset input 23 of the second D-type flip-flop ensures priority setting of the first D-type flip-flop prior to the second D-type flip-flop both the display of the address mark and the marking are required in the following character. Unlike indicated, the address mark flashes. The signal from the first output 101 of the first D-type flip-flop KOI on the first two-input logic product negation NSD1 is gated with the H2 signal at the desired address tag flashing rate. The output signal of this circuit in the second 2-input logic solo negation NSD2 is summed with the signal from the zero output 202 of the second 2-input K02 type D circuit. The signal coming from this circuit is gated on the third logic product negation NSD3. The OS signal has a logical O level when displaying the point of the information symbol, i.e., in this case, it is displayed at full brightness regardless of the address mark or underlay. The brightness signal controls the brightness level on the display of the display so that if its brightness level is logical 0, it is reduced. Signal

191 03 »coming from the output of the first two-input logic product negation type NSD1 to the first three-input logic product negation type NST1 is added together with the OS signal and the zero output 202 of the second D-type flip-flop K02. of the logical product negation type, the logical level 1 signal appears if the point of the character, address mark or marking is displayed at the moment. This signal is sampled by the H3 signal, i.e., clock pulses, in the fourth two-input logic product negation NSD4 circuit. Full UPS video signal on second output.

logic level 0 means that a bright point is displayed on the screen of the display.

If the operator locates the blinking address tag with reduced brightness - 11 in FIG.

field marked by permanent reduced brightness - III. in FIG. 2, where it records the feature information, then this feature will be recorded by continuous full brightness and supported by a reduced continuous brightness - VI. 2, wherein the address mark is moved to the next location. If the address marker is set by the operator to an already written character, it is displayed with continuous full brightness and is backed by a flashing reduced brightness - V in Fig. 2. If the character is not marked in any of the above ways, it is displayed with full permanent brightness without any underlay. For clarity, full brightness dots are shown in Figure 2. , points with reduced continuous brightness x and points with reduced flashing brightness /.

The wiring function is further evident from Fig. 3, where the signals in column a represent a point on the screen without luminance modulation - I. in Fig. 2, b underlay point - III. in Fig. 2, c point of address mark - II. in Fig. 2, d point of character IV. FIG.

The circuit according to the invention can also be used for display units with analogue display information with modified signals H1 and H3.

Claims (1)

SUBJECT VŤNÁLEZU A circuit for highlighting graphical information on a display screen, characterized in that the primary input (11) of the first D-type flip-flop (KOI) forms at the same time the first wiring input (1) and the clock input (12) of the first D-type flip-flop (KOI). the clock input (22) of the second D-type flip-flop (K02) is connected to form the third wiring input (3), the set-up input (14) and the reset input (13) of the first D-type flip-flop (KOI) are connected and connected logic 1 source, the first output (101) of the first D-type flip-flop (KOI) is connected to the second input of the first 2-input logic product negation (NSD1), while its zero output (102) is connected to the reset input (23) of the second flip-flop the D-type circuit (K02) and the basic input (21) of the second D-type flip-flop (K02) simultaneously form the second wiring input (2), while its setting input (24) is connected to a logic L source and its neutral output (202) is connected to the second input of the second two-input logic product negation (NSD2) and to the third input of the first three-input logic product negation (NST1), the first 188 038 the input of the first two-input circuit (NSD1) of the logic product type is simultaneously the fourth input (4), while its output is connected to the first input of the second two-input circuit (NSD2) of the logic product type and the logic product negation type and the output of the second two-input circuit (NSD2) of the logic product negation type is connected to the first input of the third two-input circuit (NSD3) of the logic product negation. ) of the logical product negation type is connected to the first input of the first three-input circuit (NST1) of the logical product type and simultaneously form the sixth input (6) circuit, while the output of the first three input (NSD4) type negation l the output of which is simultaneously the second circuit output (02) and the second input of the fourth two-input circuit (NSD4) of the logical product negation type simultaneously forms the fifth circuit input (5).