CO2018012657A1 - Method and apparatus for the protection of ram memories against computer attacks - Google Patents

Method and apparatus for the protection of ram memories against computer attacks

Info

Publication number
CO2018012657A1
CO2018012657A1 CO2018012657A CO2018012657A CO2018012657A1 CO 2018012657 A1 CO2018012657 A1 CO 2018012657A1 CO 2018012657 A CO2018012657 A CO 2018012657A CO 2018012657 A CO2018012657 A CO 2018012657A CO 2018012657 A1 CO2018012657 A1 CO 2018012657A1
Authority
CO
Colombia
Prior art keywords
cell
monitoring
random access
access memory
cells
Prior art date
Application number
CO2018012657A
Other languages
Spanish (es)
Inventor
Fuentes Élkim Felipe Roa
Beltrán Andrés Felipe Amaya
Héctor Gómez
Original Assignee
Univ Industrial De Santander
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Industrial De Santander filed Critical Univ Industrial De Santander
Priority to CO2018012657A priority Critical patent/CO2018012657A1/en
Priority to PCT/IB2019/059898 priority patent/WO2020104922A1/en
Publication of CO2018012657A1 publication Critical patent/CO2018012657A1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Storage Device Security (AREA)
  • Dram (AREA)

Abstract

La presente invención se refiere a un sistema de seguridad contra ataques por martilleo de filas que monitorea filas adyacentes para generar alertas que determinan acciones de mitigación aplicable a cualquier memoria dinámica de acceso aleatorio (100). Así mismo, la presente invención se refiere a una memoria dinámica de acceso aleatorio (100) que comprende un sistema de seguridad contra ataques por martilleo de filas según la invención. En una de las modalidades de la invención el tamaño de las celdas de monitoreo (5) es el mismo que de las celdas de almacenamiento (4), en donde las celdas de monitoreo (5) emulan un efecto del doble de la capacitancia, haciendo a la celda de monitoreo (5) menos susceptible a corrientes de fuga. En otra modalidad de la invención, el tamaño de la celda de monitoreo (5) es distinto al de la celda de almacenamiento (4), lo que hará a dicha celda más susceptible ante las corrientes de fuga y permitirá una detección temprana del ataque de martilleo por filas, para que el controlador de la memoria de acceso aleatorio (100) tome las acciones pertinentes, como el refresco de la memoria.The present invention relates to a security system against row hammering attacks that monitors adjacent rows to generate alerts that determine mitigation actions applicable to any dynamic random access memory (100). Likewise, the present invention refers to a dynamic random access memory (100) comprising a security system against row hammering attacks according to the invention. In one of the embodiments of the invention, the size of the monitoring cells (5) is the same as that of the storage cells (4), where the monitoring cells (5) emulate an effect of twice the capacitance, making to the monitoring cell (5) less susceptible to leakage currents. In another embodiment of the invention, the size of the monitoring cell (5) is different from that of the storage cell (4), which will make said cell more susceptible to leakage currents and will allow an early detection of the attack of row hammering, for the random access memory controller (100) to take appropriate actions, such as memory refresh.

CO2018012657A 2018-11-23 2018-11-23 Method and apparatus for the protection of ram memories against computer attacks CO2018012657A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CO2018012657A CO2018012657A1 (en) 2018-11-23 2018-11-23 Method and apparatus for the protection of ram memories against computer attacks
PCT/IB2019/059898 WO2020104922A1 (en) 2018-11-23 2019-11-18 Security system for protection against row hammering attacks, memory and methods

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CO2018012657A CO2018012657A1 (en) 2018-11-23 2018-11-23 Method and apparatus for the protection of ram memories against computer attacks

Publications (1)

Publication Number Publication Date
CO2018012657A1 true CO2018012657A1 (en) 2019-11-29

Family

ID=68652339

Family Applications (1)

Application Number Title Priority Date Filing Date
CO2018012657A CO2018012657A1 (en) 2018-11-23 2018-11-23 Method and apparatus for the protection of ram memories against computer attacks

Country Status (2)

Country Link
CO (1) CO2018012657A1 (en)
WO (1) WO2020104922A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114388049B (en) * 2020-10-16 2023-09-12 长鑫存储技术有限公司 Memory testing method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9190131B2 (en) * 2012-12-20 2015-11-17 SK Hynix Inc. Memory and memory system including the same
US9741421B1 (en) * 2016-04-05 2017-08-22 Micron Technology, Inc. Refresh circuitry
US9799391B1 (en) * 2016-11-21 2017-10-24 Nanya Technology Corporation Dram circuit, redundant refresh circuit and refresh method

Also Published As

Publication number Publication date
WO2020104922A1 (en) 2020-05-28

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