CN87104879A - High Density Tape Recording Technology of Ordinary Cassette Recorder - Google Patents

Abstract

Realize the recording and playback technology of high-density mathematical tapes with ordinary cassette recorders and ordinary cassette tapes, consisting of A/D converters, code modulators, ordinary cassette recorders and tapes, phase code/non-return to zero code converters, encoding Demodulator composition. Its characteristic lies in the encoding of information and the transformation method of phase code and non-return-to-zero code. The recording density of this technology on ordinary magnetic tape exceeds 10 ⁵ bpi, and has a very good performance/price ratio.

Description

High-density tape recording technology for ordinary cassette recorders

The present invention relates to a high-density digital tape recording and playback technology, in particular to a high-density digital tape recording and playback technology realized by using a common cassette recorder and intelligent technology.

Tape recording technology is an indispensable means in scientific research. Existing high-density digital tape recording technology devices (such as Japan TEAC's MT-2ST dedicated digital tape recorder, dedicated test tape, recording density of 8000 b.p.i.) require high-precision tape transport mechanisms and high-quality magnetic heads and tapes, which are expensive. Although ordinary tape recorders are cheap, their recording density is difficult to exceed 1200 b.p.i., and are not suitable for high-density digital tape recording.

Therefore, an object of the present invention is to realize the recording and playback of high-density digital tapes using an ordinary cassette recorder and an ordinary cassette tape.

Another object of the present invention is to use a conventional cassette recorder and a conventional cassette tape to play back a high-density digital tape having electrical crowding and nonlinear distortion of the tape loop.

A third object of the present invention is to provide a high-density digital tape recording and playback apparatus using a conventional cassette recorder and a conventional cassette tape having a high degree of anti-interference performance.

The present invention utilizes a domestically produced common two- or three-stage cassette recorder movement and uses common cassette tapes to achieve high-density digital tape recording under low-speed tape transport conditions, with a recording density exceeding 10 ⁵ bpi and a bit error rate lower than 10 ^-8 , and a ±20% variation in tape speed being allowed. The present invention has a high performance/price ratio, and has high reliability and flexibility.

FIG. 1 is a block diagram showing the composition of the present invention.

FIG. 2 is a circuit diagram of a specific embodiment of the present invention.

FIG. 3 is a software flow chart of the single chip microcomputer of the embodiment of FIG. 2 .

The essential features and excellent performance of the present invention are further described below in conjunction with the accompanying drawings.

Referring to FIG1 , the present invention is composed of an A/D converter 1, a multi-channel code modulator 2, an ordinary cassette recorder and an ordinary cassette tape 3, a phase code/non-return-to-zero code converter 4, a multi-channel code demodulator 5 and a recovery circuit 6. The A/D converter 1 converts analog continuous information into a parallel output digital signal, the code modulator 2 encodes and modulates the parallel digital signal output by the A/D converter into a serial phase code signal, and the ordinary recorder and the ordinary cassette tape 3 record and save the serial phase code signal output by the code modulator 2. When playback is required, the recorder plays the serial phase code signal recorded on the tape, the phase code/non-return-to-zero code converter 4 converts the distorted phase code signal played by the recorder 3 into a non-return-to-zero code signal NRZ and a corresponding clock CP, and the code demodulator 5 restores the serial non-return-to-zero code into a parallel output digital signal to the recovery circuit 6 under the synchronization of the clock pulse, thereby completing the high-density digital tape recording and playback of information.

Fig. 2 is a circuit diagram of a specific embodiment of the present invention. In this embodiment, the present invention is composed of an A/D converter 11, an encoding single chip microcomputer 12, a common cassette recorder and a cassette tape 13, a playback single chip microcomputer 14 and a demodulation single chip microcomputer 15.

For multi-channel information recording, the encoding microcontroller completes the following functions when recording on the tape:

1. Provide the A/D converter with a clock signal CP, a channel control signal CHANNEL and a conversion start signal START.

2. Encode the digital signal read by the A/D converter and output it from the interface in the form of phase code BIφ.

3. Encode the synchronization signal into the output serial phase code to form a serial phase code output with a frame synchronization signal.

An ordinary tape recorder and an ordinary cassette tape 13 are used to record the serial phase code signal BIφ output by the encoding microcontroller 12.

The program flow of the encoding microcontroller is shown in Figure 3 (a).

When the tape is played back, the played back BIφ signal is sent to the playback microcontroller 14 through the amplifier 18 and the zero-crossing comparator 19. The playback microcontroller 14 performs the following functions: recovering the non-return-to-zero code signal NRZ from the BIφ signal and detecting the corresponding clock pulse CP bit by bit.

The recovery method of non-return-to-zero code signal NRZ is:

1. Read the BIφ signal and determine the length of the positive 1 bit and negative 1 bit of the BIφ signal.

2. The 1-bit length of the BIφ signal in the positive direction indicates that the NRZ changes from "1" to "0", while the 1-bit length in the negative direction indicates that the NRZ changes from "0" to "1".

The bit-by-bit detection method corresponding to the clock pulse signal CP is:

1. Whenever a 1-bit serial phase code signal BIφ is encountered, a clock pulse CP is output.

2. When the serial non-return-to-zero code signal NRZ is positive or negative, a clock pulse CP is output corresponding to the 1-bit interval of the serial phase code signal BIφ.

The block diagram of FIG3(b) is a flowchart of a program for replaying the single-chip microcomputer 14 to recover the non-return-to-zero code signal NRZ from the serial phase code signal BIφ and detect the corresponding clock pulse CP bit by bit.

The serial non-return-to-zero code signal NRZ and the corresponding clock signal CP output by the playback microcontroller 14 are sent to the demodulation microcontroller 15 for branch coding and demodulation. When the tape is played back, the demodulation microcontroller 15 detects, identifies, and protects the frame synchronization signal in synchronization with the clock pulse CP, and then sends the decoded digital signal to the recovery circuit 16 in parallel, thereby completing the recovery of the magnetic recording information.

In this embodiment, the encoding single chip computer 12, the playback single chip computer 14, and the demodulation single chip computer 15 are all single chip computers with memory (such as ROM or EPROM).

Claims (6)

1, a kind of high-density digital tape recording and playback technology that is made up of A/D converter, coded modulator, common cassette recorder and common cassette tape, coded demodulator and recovery circuit, is characterized in that, The coded modulator is a multiplexed coded modulator, which is used to encode and modulate the parallel output digital signal generated by the A/D converter into a serial phase code output signal, The common cassette tape recorder and the common cassette tape are used to record the serial phase code signal output by the coded modulator, The coded demodulator is a multi-channel coded demodulator, which is used to recover the serial NRZ signal into a parallel output digital signal to the recovery circuit under clock pulse synchronization, A phase code/non-return-to-zero code converter is also connected between the ordinary cassette recorder and the ordinary cassette tape and the codec, for playing the ordinary cassette recorder and the ordinary cassette tape The serial phase code signal is transformed into a serial non-return-to-zero code signal and a corresponding clock pulse signal. 2. The technique according to claim 1, characterized in that, Wherein the NRZ generation method of phase code/NRZ converter output is, (1) According to the serial phase code signal read in, determine the positive 1bit and negative 1bit lengths of the serial phase code signal, (2) The positive 1-bit length of the serial phase code signal indicates that the serial non-return-to-zero code signal changes from "1" to "0", and the negative 1-bit length indicates that NRZ changes from "0" to "1". 3. The technology according to claim 2, characterized in that: The method of generating the clock signal output by the phase code/non-return-to-zero code converter is: (1) When encountering a serial phase code signal with a length of 1 bit, output a clock pulse, (2) When the serial non-return-to-zero code signal is positive or negative, a clock pulse CP is output corresponding to the 1-bit interval time of the serial phase code signal. 4. The technique according to claim 1, characterized in that, The phase code/non-return-to-zero code converter is composed of a single-chip computer with memory, and the hardware and software of the single-chip computer are used to simulate the generation of non-return-to-zero code and corresponding clock signal. 5. The technique according to claim 1, characterized in that, Among them, the multi-channel code modulator includes a single-chip microcomputer with memory, which is used to provide control signals to the A/D converter and generate serial phase code signal output. 6. The technique according to claim 1, characterized in that, The multi-channel codec includes a single-chip microcomputer with memory, which is used to detect and identify the protection frame synchronization signal under the synchronization of the clock signal, and output the decoded digital signal in parallel.

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