CN87101032A

CN87101032A - Automatical design of programmable array logic

Info

Publication number: CN87101032A
Application number: CN 87101032
Authority: CN
Inventors: 赵正校; 韩翔瞭; 徐智勇
Original assignee: Shanghai Jiaotong University
Current assignee: Shanghai Jiaotong University
Priority date: 1987-05-05
Filing date: 1987-05-05
Publication date: 1988-11-23

Abstract

A kind of design system of programmable array logic PAL chip, form by microcomputer, special interface circuit and software, special interface circuit is under software control, can be directly converted to corresponding level value to user's logical expression, be applied on each pin of PAL, to blow the node fuse that should blow PAL inside, form needed logical circuit, speed is fast, forms a logical circuit required time less than 10 seconds.

Description

The invention belongs to the electronic circuit technology field.Hereinafter to be referred as the PAL logic design automation.

U.S. Pat 45546460 is that a kind of PAL of utilization chip carries out the design of specific function, for example makes the logic function of PAL chip in advance, places it certain system to move as a kind of specific logical circuit.Deutsche Bundespatent 3332506 is to utilize the PAL chip to implement maintaining secrecy of software.The PAL chip is displayed logical design, and common way is by a special development system, carries out with FORTRAN IV program compiler, and the shortcoming of this method is an operating difficulties, and hardware is also very complicated, and general personnel are difficult to grasp.

The objective of the invention is to design a kind of interface circuit that the logical design of PAL chip display is used that simply is suitable for, use PALL logic description language description logic circuit, make the PAL logic design automation.

Interface circuit of the present invention as shown in Figure 1, the PC microcomputer bus is meant the bus of using PC/XT microcomputer or PC compatible among the figure.I/O address (non-memory address) is all adopted in all of the port address.Address 3EOH～3E4H port in the address decoder is data of depositing level, is used for blowing the fuse on the PAL chip internal node.Because during design PAL chip display logic, it is big to blow on the chip internal node the required level variation range of fuse, and therefore, only the level of sending by port shown in Fig. 1 can not meet the demands.So level generator is accepted 3E0H～3E4H and is sent data here among Fig. 1, be transformed into various level then, be sent on each pin of PAL chip, by designing requirement, blow the fuse that chip internal should blow.

Fig. 2 is the synoptic diagram of level generator.It accepts two kinds of signals that latch is sent here, exports a kind of level to the PAL pin of chip.

Two ports of 3E5～3E6 in the address decoder are control read datas, are used to verify whether certain node fuse of PAL chip internal blows.

Fig. 3 is the program flow diagram that control PAL chip internal node blows, and incoming source document is the source program of user with PAL logic description language PALL establishment, the i.e. logical circuit and the PAL device model of user's design; Behind the input data file, set arbitrarily by the user, be mainly used in the node coordinate figure of depositing in the PAL interior display, the course of work of whole process flow diagram is: first, search key before and after the follow procedure section, such as COMMENT, DEVICE DECLARATION, PIN ASSIGNMENT, LOGIC EQUATION and END etc., behind the key word that searches a certain program segment,, handle the statement in this program segment according to each program segment requirement.All comment statements are all ignored, and pin is composed name and the PAL model all will be sent table storage.Describe in the section at logical expression, at first all pin names are defined as the pin number, and then carry out grammatical analysis by the SLR analytic approach, and produce the limit coordinate figure, this coordinate figure one by one is admitted in the data file.When producing the node coordinate figure, contrast PAL model judges whether the logical expression that the user writes is consistent with its selected PAL chip internal structure, as inconsistent, then provides error message.

Second, after forming whole node coordinate figures and do not have an error message, then program is by one section program segment of writing with 8086/8088 assembly instruction, data are delivered to the interface circuit corresponding port, level generator becomes corresponding level to the data conversion of corresponding port, and this level is delivered to corresponding pin in the PAL chip jack again.

Whether check PAL chip internal node is blown by designing requirement, in the end carries out, and as inerrancy, then whole procedure finishes.

The present invention carries out Logic Circuit Design to programmable array logical device PAL, is methodically arranged, and writes conveniently, according to logical expression, can directly be applied to corresponding level changing value on each pin of PAL, thereby speed is fast, the time that forms a logical circuit was less than 10 seconds.

Claims

1, a kind of design system that displays logical circuit is made up of micro computer, interface circuit and software, it is characterized in that interface circuit and software can automatically display logical design to the PAL chip of different model.

2, by the described display Logic Circuit Design of claim 1 system, it is characterized in that interface circuit is applicable to the multiple level requirement of different model PAL chip.

3,, it is characterized in that with PALL logic description language description logic circuit by the described display Logic Circuit Design of claim 1 system.