CN86208875U

CN86208875U - Electronic millisecond watch

Info

Publication number: CN86208875U
Application number: CN 86208875
Authority: CN
Inventors: 李恭敢
Original assignee: HENGYANG SIFANG RELAY FACTORY
Current assignee: HENGYANG SIFANG RELAY FACTORY
Priority date: 1986-11-01
Filing date: 1986-11-01
Publication date: 1988-06-15

Abstract

The utility model provides a digital MS meter comprising a CMOS integrated circuit, taking the crystal oscillator as the standard time source. The digital MS inputs the addition counter through a first-stage variable divider and a first-stage fixed divider. The digital MS meter starts, times or stops the control of circuits with a D trigger and a plurality of gate circuits. The digital MS meter counts the clock pulse by controlling the addition counter, realizing the millisecond and time quantity measurements. The meter circuit is simple and small structure. The utility model has the advantages of low power consumption and low cost.

Description

Electronic millisecond watch

The utility model is the electronic millisecond meter (hereinafter to be referred as instrument) that a kind of 4-digit number of full-digital circuit shows.It is the time interval between being switched on or switched off of cycle, pulse width, all kinds of relay tip or other electric installation of measuring electric impulse signal, and the calibration of the delay time of the time relay provides reliable means.

Before this, for reaching the purpose of measuring these time quantums, mechanical type millisecond meter and electronic type millisecond meter have appearred.Mechanical type millisecond meter measuring accuracy is low, and the machining requirement is high, uses mechanical component easily frayed for a long time.Existing electronic type millisecond meter circuit complexity, volume is big, power consumption is big, cost is high.

The utility model instrument is intended to for the user provides a kind of small and exquisite, and it is convenient to measure, and circuit is simple, low-power consumption, cheap electronic millisecond meter.

The utility model instrument has a standard clock source that is produced by crystal oscillator, send into up counter through behind the suitable frequency division, starting timing and stopping under the control of two control circuits of timing, the number of the time clock that record passes through, promptly be the numerical value that needs the time quantum of measurement, instrument shows with 4-digit number.

The characteristics of the utility model instrument are: all adopt the Low-Power CMOS device, have a change frequency divider standard clock source is carried out suitable frequency division, starting timing and stopping respectively to have in two control circuits of timing a d type flip flop and the control core of some gate circuits conduct " startup " or " stopping ", circuit is simple.No matter start stop signal is positive negative pulse stuffing or positive negative potential, or ac signal all can, it is flat that datum both can be " 0 " platform, also can be high level.

Fig. 1 is the circuit diagram of the utility model instrument preferred embodiment.

The theory diagram of the utility model instrument as shown in Figure 2, each square frame is defined as follows:

11 is standard clock source, and 12 for becoming frequency divider, and 13 is fixed frquency divider, and 14 is up counter, and 15 is nixie display, and 16 are zero clearing, and 17 is start-up control, and 18 is " startup " signal, and 19 is "signal for " stop ", and 20 for stopping control.

Followingly according to Fig. 1 the principle of work of the preferred embodiment of the utility model instrument is described, this accompanying drawing is the electronic millisecond meter schematic diagram.

Present embodiment is provided with the crystal oscillator of a 200KHZ and makes standard clock source (6).(7) be to become frequency divider, its divide ratio is by the CN end level decision of (7), and when CN was level "0", divide ratio was 20, and during for level"1", divide ratio is 200.The output of standard clock source (6) links to each other with (7) input end of clock C.(7) output terminal C ₀Through rejection gate D ₆Anti-phasely link to each other with a clock end C who fixes 10 frequency dividers (8).(8) output terminal C ₀Link to each other with the counting control end C1N of up counter (9), the result of counting is shown by group of four figures display (10).

D type flip flop FF ₁And rejection gate D ₃Start-up control device, Schmidt's not gate D have been formed ₁, D ₂With two core socket J ₁, double-pole multithrow switch K ₄Resistance R ₁～R ₅Diode Z ₁And Z ₂Constitute " startup " signal input circuit.Look the polarity and the amplitude size of " startup " signal and select K ₄The switch gear." startup " signal is by resistance R ₁～R ₃Step-down, Z ₁～Z ₂Behind the amplitude limit by D ₁The anti-phase FF that is defeated by of D2 one-level or two-stage shaping ₁D end.Rejection gate D ₃Output terminal connect FF ₁Clock end C, FF ₁Q termination D ₃An input end, D ₃Another the input termination standard clock source (6), FF ₁Q end connect the counting control end C that becomes frequency divider (7) _1N, FF ₁Reset terminal R by reset switch K ₁Insert reset signal.Starting elder generation, FF ₁Be reset to " O " state, i.e. FF ₁Q be " O " level, Q end is level"1", at this moment rejection gate D ₃Opening d type flip flop FF ₁Clock end time clock is arranged, FF ₁D end be level "0".In case " startup " signal adds the D end when becoming level"1" and width greater than 10 μ S, FF ₁Upset is one state.Make the counting control end C1N that becomes frequency divider (7) become level "0".Electronic millisecond meter promptly is activated timing.This moment rejection gate D ₃Sealed.FF ₁C end time clock disappear, no matter how its D end level changes FF ₁One state all no longer change, can only force go back to " 0 " by the level of its reset terminal R.

If " startup " signal is pulse or current potential or alternating current, then " startup " signal is by two core socket J ₁Input.J ₁Skin be with reference to level "0", the internal layer heart yearn transmits signal.Send into Schmidt's not gate D after the signal step-down ₁Shaping if " startup " signal is a negative polarity, is then sent into FF by (4) point after the shaping ₁D end; If " startup " signal is a positive polarity, then multipath is crossed Schmidt's not gate D ₂Have anti-time phase and send into FF by (5) point ₁D end.

D type flip flop FF ₂And rejection gate D6 has formed and has stopped control circuit, D ₆Output terminal connect the counting that becomes frequency divider (7) simultaneously and preset control end PE, the clock end C of fixed frquency divider (8), the clock end C of up counter (9), d type flip flop FF ₂Clock end C, D one the input termination variation output terminal C of device (7) frequently ₀, another input end and FF ₂Q end link FF ₂D termination "signal for " stop ", FF ₂Reset terminal R by reset switch K ₁Insert reset signal.FF ₂Be " 0 " state before stopping timing, rejection gate D6 is opening, FF ₂C end time clock is arranged, its D end does not have and is input as level "0", in case the D end has the "signal for " stop " input to become level"1", FF ₂Upset is one state, D ₆Sealed FF ₂C end time clock disappear, no matter how its D end level changes FF ₂One state all no longer change, can only force go back to " 0 " by the level of its reset terminal R.Schmidt's not gate D ₄, D ₅With two core socket J ₂, double-pole multithrow switch K ₃, resistance R ₆～R ₁₀, diode Z ₃, Z ₄Constituted and stop the "signal for " stop " input circuit, it is similar with " startups " signal input circuit, has just repeated no more.

K ₁Be reset switch, during zero clearing, high level is added to the clear terminal CLEAR and the d type flip flop FF of fixed frquency divider (8) and up counter (9) ₁, FF ₂Reset terminal R, make counter O reset, and with FF ₁, FF ₂Be changed to initial " 0 " state.K switch ₂For the divide ratio that select to become frequency divider (7) and people are provided with into the radix point of adding display.K ₂The CN that puts (7) holds when being level"1", and divide ratio is 200, and the digital least unit that shows is 1ms, K ₂Divide ratio is 20 when putting CN and being level "0", and the digital least unit that shows is 10ms.

When the adhesive of test idle contact or release time, should be with J ₁And J ₂In plug transfer to K ₃, K ₄Should corresponding placing " often open " or " normally closed " position.

Claims

1, a kind of by standard clock source, frequency divider, up counter and start timing or stop time control circuit and electronic millisecond meter that other accessory circuit is formed, it is characterized in that: it has the frequency divider that is in series and is constituted by one-level change frequency divider (7) and one-level fixed frquency divider (8), has one by d type flip flop FF ₁Rejection gate D ₃The start-up control circuit that constitutes.Have one by d type flip flop FF and rejection gate D ₆What constitute stops control circuit.

2, by the described electronic millisecond meter of claim 1, it is characterized in that the rejection gate D of wherein said start-up control circuit ₃Output termination d type flip flop FF ₁Clock end C, FF ₁Q termination D ₃An output terminal, D ₃Another termination 200KHZ standard clock source, FF ₁The Q termination become the counting control end C1N of frequency divider (7), FF ₁D termination " startup " signal, FF ₁Reset terminal R by reset switch K ₁Insert reset signal.

3, by the described electronic millisecond meter of claim 1, it is characterized in that, the wherein said output terminal that stops the rejection gate D6 of control circuit connects the counting that becomes frequency divider (7) simultaneously and presets control end PE, the clock end C of fixed frquency divider (8), the clock end C of up counter (9) and d type flip flop FF ₂Clock end C; D ₆The input termination variation output terminal C of device (7) frequently ₀D ₆Another termination FF ₂Q end; FF ₂D termination "signal for " stop "; FF ₂Reset terminal R by reset switch K ₁Insert reset signal.