CN86101206B - Semiconductor memory - Google Patents

Abstract

Disclosed is a dynamic RAM wherein each time a refresh address counter performs a plurality of steps of increment operations, an address switching circuit is switched to specified refresh addresses held in an address storage circuit, by utilizing the most significant bit of a divided-by-(2<n> + 1) counter circuit whereby memory cells of inferior data retention times are refreshed.

Description

Semiconductor memory

The present invention relates to a semiconductor memory, particularly relate to be used to resemble dynamic ram (random access memory (RAM)) such have the memory of inherent refresh circuit the time be effective a kind of technology.

The memory cell of dynamic memor is by the storage capacitance and the MOSFETs(MOS (metal-oxide-semiconductor) memory that is used for address selection that are used for the form of electrical charges stored data) constitute.Among the memory cell that forms on the semiconductor chip, the electric charge that is stored in its capacitor is owing to the growth of causes such as leakage current along with the time will reduce.Therefore, be referred to as to call the operation that refreshes in order to keep being stored in the accuracy of the data in the memory cell, need to finish.Finish among this operation that refreshes, the data item that is stored in the memory cell was read before its disappears, and the data item of reading is amplified, going among then again it being write same memory cell.For example, at magazine " electronic technology (Denshi Gijutsu) " Vol.23, No.3, a kind of auto-refresh circuit of the last description of pp.30-33 promptly is considered to an automatic updating system that is used for the memory cell of 64K position (bits) dynamic random access memory RAM.It to the effect that such: an external terminal that is used for refresh control is installed on dynamic random access memory RAM, and this dynamic ram has automatic refresh function; Therefore, a refresh control signal REF who gives deciding level is added on this exterior terminal, so just the many memory cells among this dynamic random access memory RAM have all been refreshed automatically.And because himself refresh function, just this refresh signal REF is remained on this and give and having decided on the level, so the operation by an internal timing circuit is finished this refresh operation to each fixing cycle.

Because this auto-refresh circuit makes all memory cells all stand this refresh operation in the same cycle, therefore consider under its worst situation, must select about 2ms(millisecond) very short refresh cycle so.This dynamic ram continues to carry out refresh operation on so quite short time interval, therefore very most power consumption ascribes this refresh operation on this dynamic random access memory RAM.

The inventor has studied the data hold time of memory cell, and the data hold time of finding most of memory cells reaches about 400-1000ms(millisecond), deteriorate into several milliseconds at random and have only limited minority memory cell because of cause such as procedure fault.Find that according to this inventor expects making the refresh cycle of these memory cells unequal mutually, with corresponding with the data hold time of these memory cells.

Purpose of the present invention is exactly to provide a for example semiconductor memory resemble the dynamic ram that reduces its power consumption.

Above-mentioned purpose of the present invention and other purposes and some novel characteristics among the description of this instructions and accompanying drawing thereof, will be very clearly.

Principal feature of the present invention is summarized as follows simply.

A refresh address counter, among many operation steps, carry out one at every turn and add 1 operation, a traffic pilot is switched to some the specific refresh addresses that kept in the address storage circuit to get on, therefore for refreshing memory cell, it is less important that the data hold time of these memory cells just becomes.

Fig. 1 is the circuit diagram of explanation DRAM, and it is one embodiment of the invention;

Fig. 2 is the circuit diagram of an embodiment of refresh control circuit and a traffic pilot among the DRAM of key diagram 1;

Fig. 3 is the circuit diagram of the embodiment of an address storage circuit among the DRAM of key diagram 1;

Fig. 4 is the sequential chart of refresh operation that is used for the DRAM of key drawing 1.

Fig. 1 represents the circuit diagram according to dynamic ram embodiment of the present invention.With the various circuit components among the figure by known production CMOS(complementary MOS) process of integrated circuit is produced on the single semiconductor chip, for example on the such substrate of monocrystalline silicon.In the following description, if not dated especially, MOSFEF(isolated-gate field effect transistor (IGFET) then) just refer to the MOSFET of N-raceway groove.In the figure, each is added with the MOSFET of straight line at its source electrode and drain electrode two ends, refers to the MOSFET of P-raceway groove.

Though be not to limit especially, the integrated circuit of the present embodiment is to be produced on the semiconductor chip of being made by p type single crystal silicon.The N-channel mosfet is made of source area and drain region and grid.This source area and drain region all are to be produced among such surface of semiconductor chip, and for example the grid of polysilicon is to be produced on the part surface of the semiconductor chip between source area and the drain region by an insulation film.The P-channel mosfet is to be produced on the N type wellblock that forms in its surface of semiconductor chip.Therefore, this of semiconductor chip formation is many N-channel mosfet s gate common bodies that form on this semiconductor chip.This N type wellblock is formed in the grid body of the P-channel mosfet that forms on this semiconductor chip.Power end V among Fig. 1 is coupled in the grid body of P-channel mosfet that is N type wellblock _Cc

Below will summarize the more concrete structure of this integrated circuit.

What made by the monocrystalline silicon of P-type conduction, and be formed with in the surface of semiconductor chip part of N type wellblock, the part of those non-surface portions is used for active region; In other words, the part of those non-surface portions is used for the semiconductor wires zone; And source electrode, drain electrode and raceway groove (grid) the formation zone that those electric capacity is formed zone and N-raceway groove and P-channel mosfet uses the thicker field insulating membrane that forms by known selective oxidation method to cover.Form formation ground floor polysilicon on the zone by an insulation film (oxide film) at these electric capacity.This ground floor polysilicon is extended to field insulating membrane to get on.The oxide film that produces with the thermal oxide by this polysilicon layer itself forms this ground floor polysilicon surface.In form the surface of semiconductor chip part in zone corresponding to electric capacity, inject the formation raceway groove by ion; Perhaps these channel regions are gone to this ground floor polysilicon by applying like an elephant a so suitable voltage induced of supply voltage.Like this, form electric capacity, insulation film and the channel region of forming by its ground floor polysilicon.The ground floor polysilicon segment that is superimposed with field oxide film is regarded as a kind of wiring.

By a grid oxidation film, on the channel formation region territory, be formed for constituting the second layer polysilicon of grid.This second layer polysilicon is extended to field insulating membrane and the ground floor polysilicon gets on.Although do not limited especially, but word line in the storage array that will describe below and dummy word line all are to constitute with this second layer polysilicon.

On the active region surface that field insulating membrane of no use covers and in ground floor and the second layer polysilicon, by a known employing diaphragm and these polysilicon layers doping introducing technology, form its source region, drain region and semiconductor wires zone as the mask that is used to mix.

Including on the semiconductor surface part of ground floor and second layer polysilicon, form a thicker inner layer insulating film.On this inner layer insulating film, form a conductor layer that for example makes by aluminium.Some contact paths by providing in the dielectric film of underlay are coupled to these polysilicon layers to this conductor layer in the electrical couplings mode and semiconductor regions gets on.Although do not limited especially, but the data line in the storage array that will describe below is to be made of this conductor layer that extends on this inner layer insulating film.

The surface of semiconductor chip part of this inner layer insulating film and this conductor layer will be included, with a last passivation membrane covered that for example makes that forms by silicon nitride film and phosphinylidyne silication glass-film.

Substrate reverse bias voltage among Fig. 1 produces circuit VBG, according to being added in the power end V that constitutes this integrated circuit outer end contact _CcAnd a forward supply voltage between reference potential end or the earth terminal, for example+and 5V, produce a negative sense anti-bias voltage V who adds to this semiconductor chip _BbLike this.The grid body that this reverse bias is added to those N-channel mosfets s gets on.Therefore, the source electrode of these MOSFETs and the stray capacitance value between drain electrode and the substrate have been reduced, thereby improved the operating speed of circuit.

Although do not limited especially, but this storage array M-ARY is the storage array of folded bit line structure.Fig. 1 shows a pair of line of this storage array particularly.Each memory cell all is made up of an address selection MOSFET Qm and a data storage capacitance Cs.According to giving set pattern then distribute the input node and the output node of these memory cells shown in the figure, and they are coupled to complementary data line D and the D that pair of parallel arranges.

Constitute pre-charge circuit PC1 by the switch MOS FET that is plugged on the N-channel-type between complementary data line D and the D, as figure MOSFET Q ₅Shown in the typical case like that.

By P-channel mosfet s Q ₇And Q ₉With N-channel mosfet sQ ₆And Q ₈The CMOS latch circuit of forming constitutes sensor amplifier SA, and a pair of input of sensor amplifier and the node of output are coupled on complementary data line D and the D.Though do not limited especially, this latch circuit is the P-channel mosfet s Q that is in parallel by two ₁₂And Q ₁₃Add to supply voltage V _Cc, and by two N-channel mosfet s Q that are in parallel ₁₀And Q ₁₁Ground voltage V _SSPower switch MOSFETs Q ₁₀And Q ₁₁With MOSFETs Q ₁₂And Q ₁₃Be common to the latch circuit in other lines roughly the same in the same storage piece.In other words, the P-channel mosfet s in the latch circuit in the identical storage piece has the source electrode then that links to each other jointly respectively with N-channel mosfet s.

Respectively to MOSFETs Q ₁₀And Q ₁₂Grid add to complementary timing pip φ at an operating cycle internal trigger sensor amplifier SA _Pa1And φ _Pal, simultaneously respectively to MOSFETs Q ₁₁And Q ₁₃Grid add to and lag behind timing pip φ _Pa1And φ _Pa1Complementary timing pip φ _Pa2And φ _Pa2In this manner, the division of operations of this sensor amplifier is two stages.Producing timing pip φ _Pa1And φ _Pa1The time, that is, and on the phase one, when handle amplifies from faint read-out voltage memory cell, that obtain on the pair of data lines two ends, owing to have the MOSFETs Q of relative low electric conductivity ₁₀And Q ₁₂Metering function, thereby remove any undesirable level fluctuation from.Producing timing pip φ _Pa2And φ _Pa2The time, that is, the amplification by sensor amplifier SA through after amplifying, begins its subordinate phase to the potential difference (PD) on this complementary data line, and this is had the MOSFETs Q of relative high conductivity ₁₁And Q ₁₃Become " conducting " state.By MOSFETs Q ₁₁And Q ₁₃" conducting " state, quicken the amplification of sensor amplifier SA.Owing to finish the amplification of this sensor amplifier SA by this way in two stages of separating, therefore sense data has at high speed prevented also simultaneously that those the undesirable level on this complementary data line from changing.

Though limited especially, its line decoder R-DCR is made of the combination of two line decoder R-DCR1 and R-DCR2.The circuit arrangement (corresponding to four word lines) of its second line decoder R-DCR2 typically has been described in the drawings.According to described device, be circuit-formed for a word line selection signal of these four word lines by a cmos nand gate (NAND), this cmos nand gate is by receiver address signal a ₂-φ ₆N-channel mosfet s Q ₃₂-Q ₃₆And P-channel mosfet s Q ₃₇-Q ₄₁Constitute.By CMOS phase inverter IV ₁With this NAND(and non-) output signal of gate circuit is anti-phase, then, the MOSFETs Q that ends by the N-channel-type ₂₈-Q ₃₁, send them to transmission gate MOSFEsQ as the N-channel-type of on-off circuit ₂₄-Q ₂₇Grid.

Yet, this first line decoder R-DCR ₁Do not provide its concrete circuit, it selects timing signal φ through on-off circuit from a word line _XAmong form four word lines and select timing signal φ _X00-φ _X11This on-off circuit is to be made of roughly the same above those transmission gates MOSFETs and the MOSFETs that ends, and is by 2-position (bit) complementary address signal a ₀, a ₀And a ₁, a ₁The decoded signal that forms elects.Word line is selected timing signal φ _X00-φ _X11Through transmission gate MOSFETs Q ₂₄-Q ₂₇Being sent to corresponding word line gets on.

Though limited especially, here be to work as with address signal a ₀And a ₁When remaining on low level, this timing signal φ _X00Become and timing signal φ _xA synchronous high level.Equally, when with address signal a ₀And a ₁, a ₀And a ₁, and a ₀And a ₁When remaining on low level, respectively timing signal φ _X01, φ _X10, and φ _X11Become and timing signal φ _xSynchronous high level.

Therefore, address signal a ₁And a ₁Regard as a kind of word line group that is used among many word lines, distinguishing and select signal, corresponding to the word line group (W of memory cell ₀And W ₁, below be called " first word line group ") be coupled on the data line D, and corresponding to the word line group (W of memory cell ₂And W ₃, below be called " second word line group ") be coupled on the data line D.

Line decoder is being divided into two line decoder R-DCR ₁And R-DCR ₂The time, can be this line decoder R-DCR ₂Spacing (at interval) make with the spacing of these word lines and equate.The space that is wasted can not appear in its result on semiconductor chip.With MOSFETs Q ₂₀-Q ₂₃Be placed between each word line and the earth potential.With this NAND(and non-) output terminal of gate circuit is added to MOSFET Q ₂₀-Q ₂₃Grid get on, thus the word line that is in non-selected state is fixed on the earth potential.

Though do not limit especially, the word line here is positioned at its far-end one side (end opposite with code translator one side) and has the MOSFETs Q that resets ₁-Q ₄When receiving reset pulse φ _PwThe time, MOSFETs Q ₁-Q ₄Promptly enter " conducting " state, thereby selected word line two ends are reset to ground level.The capable group address signal of remaining 2 (bits) a ₇(a ₇And a ₇) and a ₈(a ₈And a ₈) as the switching signal (selection signal) of storing piece (with last storage array roughly the same and that be divided into mass part).

Row address buffer X-ADB receives from outer end A ₀～A ₈Add (OK) address signal of coming in, and form and add the synchronous internal address signal a of these address signals of coming in by the outer end ₀-a ₈, then again they are added to a following traffic pilot that will illustrate and get on.

Row switch C-SW connects its complementary data line D and D and shared complementary data line CD and CD selectively, as by MOSFETs Q ₄₂And Q ₄₃Illustrated.Presenting to these MOSFETs Q from the selection signal of column decoder C-DCR ₄₂And Q ₄₃Grid.

Column decoder C-DCR has its column selection timing, and is to be subjected to a data line options timing pip φ _yControl.In a predetermined column selection regularly, this column decoder C-DCR is to the internal address signal a from column address buffer Y-ADB ₉-a ₁₄And anti-phase internal address signal a ₉-a ₁₄Decipher, thus, form and select signal, again it is added to row switch C-SW.

Column address buffer Y-ADB receives from outer end A ₉-A ₁₄(row) address signal, and the internal address signal a of the address signal homophase of formation and outer end input ₉-a ₁₄, reach the anti-phase internal address signal a of address signal with the outer end input ₉-a ₁₄(following will concentrating two internal address signals represented to become a ₉- a ₁₄), then, again they are added to column decoder C-DCR.Equally, a ₀- a ₈To represent internal address signal a ₀-a ₈, and anti-phase internal address signal a ₀-a ₈

A N-channel-type precharge MOSFET Q who constitutes pre-charge circuit ₄₄Put between shared complementary data line CD and the CD.The input and the output node that will have a pair of main amplifier MA of the circuit structure that is analogous to sensor amplifier SA are connected to this shared complementary data line CD and CD.

In read operation, by being added to the timing signal φ on the data output buffer DOB _Rw, make this data output buffer DOB enter mode of operation; So it amplifies the output signal of main amplifier, and then this output signal is exported by outer end contact I/O.In write operation, by timing signal φ _Rw, make the output terminal of its data output buffer DOB present high impedance status.In this write operation, by being added to the timing signal φ on the data input buffer DIB _Rw, make data input buffer DIB enter mode of operation; So, this data input buffer DIB handle with add the corresponding to complementary write signal of the write signal of coming in from outer end contact I/O and be sent on this shared complementary data line CD and the CD.Like this, data are write in the selected memory cell go.In addition, in its read operation, by timing signal φ _Rw, make the output terminal of this data input buffer DIB present high impedance status.

The dynamic type memory cell of being made up of as mentioned above address selection MOSFET Qm and data-storing capacitor C s is being carried out in the process of write operation, in order to realize making satisfactory writing to this storage capacitance Cs, in other words, in order to prevent that the level breakdown when this data-storing capacitor Cs writes high level from appearring in causes such as threshold voltage owing to address selection MOSFET Qm, provided a word line boostrap circuit (not shown) being selected timing signal φ x starting by word line.Select timing signal φ owing to used this word line _xAnd inhibit signal, this word line boostrap circuit provides the high level that word line is selected timing signal φ x, this high level beyond supply voltage V _Cc

Each above-mentioned timing signal is to form by following circuit block diagram.

The circuit square frame of representing with symbol ATD is an address signal transition detecting device.Though do not limited especially, here this transition detecting device receiver address signal a ₀-a ₈(or a ₀-a ₈) and address signal a ₉-a ₁₄(or a ₉-a ₁₄), and detect the rising transition and the decline transition of these address signals.Though do not limited especially, here this address signal transition detecting device is by difference Input Address signal a ₀-a ₈And the AND(of several output signals of these exclusive OR circuit of several exclusive OR circuit of inhibit signal and one input with) circuit, and those a of same input ₉-a ₁₄Address signal circuit constituted.That is to say that the exclusive OR circuit of the inhibit signal of these receiver address signals and these address signals thereof is for each address signal is provided with.As address signal a ₀-a ₈In any one when changing, this address signal transition detecting device ATD just produces the capable group address signal transition detection pulse φ of a time synchronised that takes place with this variation _rEqually, as address signal a ₉-a ₁₄In any address signal when changing, the address signal transition that this address signal transition detecting device ATD just produces a row group detects pulse φ _c

The circuit of representing with symbol TG is the timing pulse signal generator, produces above-mentioned main timing pulse signal by it.That is to say, the timing pulse signal generator receive from the outer end contact add come write enabling signal WE and chip selection signal CS, also have address signal transition to detect pulse φ and φ in addition, thereby form the timing pip sequence.

What circuit symbol REFC indicated is an auto-refresh circuit, and it comprises address counter, timer or the like (not shown).This auto-refresh circuit is to enter low level by the refresh signal REF that makes the outer end contact to start.More particularly, REF becomes low level when this refresh signal, when this sheet selects signal CS to remain on the high level simultaneously, then correspondingly this auto-refresh circuit REFC is become duty.Then, this circuit REFC is control signal φ _RefAdd to traffic pilot MPX.This control signal φ _RefMake that this traffic pilot will be from refresh address counter CT within the circuit REFC ₁And CT ₂The internal address signal b of (will be illustrated below) ₀-b ₈Send line decoder R-DCR to.Therefore, the execution of refresh operation (refreshing automatically) is with the basis that is chosen as corresponding to a word line of internal address signal.In addition, when refresh signal REF is remained on low level, the work of this timer, and in each fixed time period refresh address counter (CT ₁, CT ₂) increase 1; So carry out continuous refresh operation (self refreshes) simultaneously.

For the refresh cycle of the reality that extends, thereby reduce power consumption, this auto-refresh circuit REFC has the function of address set.This function provides a refresh cycle to the memory cell of most of long data retention time, and the memory cell of those short data retention times is provided a refresh cycle.

Below will elaborate, with address signal b ₀-b ₈Be used as and refresh the address that those have the long data retention time memory cell of (400-1000 millisecond (ms)).On the other hand, with address signal C ₀-C ₈According to the counter CT within the circuit REFC ₃The output signal of (below will be described) adds to traffic pilot MPX.Address signal C ₀-C ₈Be used as and refresh the address that those have the memory cell of short data retention time (several milliseconds).Traffic pilot MPX is among refresh operation, perhaps address signal b ₀-b ₈Send line decoder R-DCR to, perhaps address signal C ₀-C ₈Send line decoder R-DCR to.

Fig. 2 is illustrated as the embodiment of a device realizing above-mentioned functions.What represent among the figure is the circuit diagram of the embodiment of this auto-refresh circuit REF and this traffic pilot MPX.

Although be not particularly limited, the address counter that is used to form the address signal that will refresh here is by two counter circuit CT that are connected in series ₁And CT ₂Constitute.To export the delta pulse φ that forms from the refresh control signal REF of outer termination point or according to the pulse of timing circuit (not marking), add to the first counting circuit CT ₁Input end.First counting circuit CT ₁Be five branch frequency counting circuits that usefulness 3 digit counters form, although do not limited especially at this.With this counting circuit CT ₁Least significant bit (LSB) b ₀And next bit b ₁, be used as corresponding to address signal A ₀-A ₈Among 2 bit address signal A ₀-A ₁Refreshing address signal; And the signal of remaining highest significant position is added to the second counting circuit CT ₂Input end as carry signal Ca.This binary counter circuit CT of 7 ₂Formation is corresponding to row group address signal A ₀-A ₈Among the address signal b of those remaining bits ₂-b ₈The feature of the present embodiment is to counting circuit CT with carry signal Ca ₂Least significant bit (LSB) b ₂Presenting, is not direct address bit b with last position ₁To this counting circuit least significant bit (LSB) b ₂Present.With this address signal b ₀-b ₈Being added to the following traffic pilot MPX that will be described gets on.

Saying on the other hand, is to utilize the first counting circuit CT ₁The signal of highest significant position just utilizes this carry signal Ca, carries out the refresh operation of the memory cell of those short data retention times.Though limit especially, be that carry signal Ca is added to one the 3rd counter circuit CT as the part of address switch circuit here ₃Input end.This counter circuit CT ₃It is one four frequency counter circuit.With its binary counter circuit CT ₃2 output signal d ₀And d ₁Be transformed into four by decoder circuit DCR and select signal DS ₀-DS ₃

These are selected signal DS ₀-DS ₃, as the selection signal of memory circuit, be used for specifying the address of word line, and these word lines are the memory cells of those short data retention times of being coupled.Preparation is used as the address storage circuit, is exactly storage circuit R ₀-R ₃; These storage circuit storages are used for specifying the address signal that four addresses on the word line are arranged altogether.These select signal DS ₀-DS ₃Be input to storage circuit R respectively ₀-R ₃Get on.

Fig. 3 represents corresponding to storage circuit R ₀-R ₃1 (signal C ₀) a practicable circuit embodiments.With other position (signal C ₁-C ₈) also be provided with similarly.Referring to Fig. 3, will select signal DS ₀-DS ₃Add to N-channel mosfet s Q ₇₁-Q ₇₄Grid.Although do not limit especially, be the fuse F that makes by polysilicon layer here ₁-F ₄Install Q respectively at MOSFETs ₇₁-Q ₇₄Source electrode and the ground potential points of this circuit between.These MOSFETs Q ₇₁-Q ₇₄Drain electrode link together jointly, and with P-channel mosfet s Q ₇₀Provide as the load field effect transistor.That is to say, at storage circuit R ₀In, be used for output signal C ₀Element circuit be by MOSFET Q ₇₁With fuse F ₁Constitute.When selecting storage circuit R ₁-R ₃In each storage circuit the time, according to the element circuit of similar setting, form the signal C that will provide ₀According to the address that those memory cells with short data retention time are coupled to these word lines on the word line, heat-treat by for example using the method for laser beam, then make these fuses F ₁-F ₄Resistance value change, perhaps fused.These are selected signal DS ₀-DS ₃Alternately provide high level.Therefore, " conducting " state that the MOSFETs of any selected storage circuit entered into.Consequently the high level or the low level address signal C that whether fuse and be consistent with the fuse of selected storage circuit ₀Send.Similarly, pass through signal DS from each ₀-DS ₃The storage circuit R that selects ₀-R ₃Among output its signal C ₁-C ₈

In this embodiment, owing to provided four groups of storage circuit R as shown in Figure 3 ₀-R ₃, therefore can refresh those memory cells that are connected to four short data retention times on the word line.As mentioned above, select signal DS ₀-DS ₃Function be to transmit selectively respectively at corresponding storage circuit R ₀-R ₃The middle address signal that keeps.The address signal C that will alternately export according to this method ₀-C ₈The traffic pilot MPX that is connecting below adding to.

This traffic pilot MPX selects and exports address signal a arbitrarily as the part of address switch circuit ₀-a ₈, signal b ₀-b ₈And signal c ₀-c ₈Constitute by following circuit component at this element circuit that transmits selectively among the multipath conversion MPX of a signal.

P-channel mosfet Q ₅₀Play pull-up resistor, in such a manner, with this P-channel mosfet Q ₅₀Grid fixedly receive on the earth potential of circuit.With this MOSFET Q ₅₀Source electrode be connected to supply voltage V _CCOn.This MOSFET Q ₅₀Be used as common load according to the N-channel-type driven MOS FETs of following three tunnel serial connection forms that will illustrate.By the way, this element circuit is to be used for corresponding address signal A ₀Internal address signal a ₀, b ₀And c ₀A circuit.

One road sequential circuit is by N-channel mosfet s Q ₅₇And Q ₅₈Constitute.Refresh control signal φ _RefAdd to inverter circuit IV ₃, again this phase inverter IV ₃Output signal add to MOSFET Q ₅₇Grid; Simultaneously, address signal a from address buffer X-ADB ₀Add to MOSFET Q ₅₈Grid.Other two-way sequential circuits are respectively by MOSFETs Q ₅₁, Q ₅₂, and Q ₅₃With MOSETs Q ₅₄, Q ₅₅And Q ₅₆Constitute.With refresh control signal φ _RefAll be added to MOSFETs Q jointly ₅₁And Q ₅₄Grid on.The MOSFET Q of road sequential circuit in the above-mentioned two-way sequential circuit ₅₂Grid, be added with carry signal Ca, and to MOSFET Q ₅₃Grid, be added with address signal C from storage circuit ₀In addition, the MOSFET Q of another road sequential circuit in the above-mentioned two-way sequential circuit ₅₅Grid, be added with inverter circuit IV ₂Output signal, this inverter circuit IV ₂That receive is carry signal Ca; And to MOSFET Q ₅₆Grid, send into the address signal b that produces by the refresh address counter circuit ₀

Another correspondence highest significant position (A ₈) element circuit, by the MOSFETs Q that is similar to the foregoing circuit structure ₆₀-Q ₆₈Constitute.

Below, we describe according to refresh operation of the present invention with reference to timing waveform figure shown in Figure 4.

Be not under the situation of refresh operation control signal φ at above a kind of this circuit of working as that is not illustrated _RefLow level make the MOSFET Q of traffic pilot MPX ₅₁And Q ₅₄(Q ₆₁And Q ₆₄) end, and make its MOSFET Q ₅₇(Q ₆₇) " conducting ".Therefore, this traffic pilot MPX sends address signal a ₀-a ₈, but do not send address signal b ₀-b ₈Or C ₀-C ₈

On the other hand, in the middle of refresh operation, this is added to the low level that refresh signal REF on the contact of outer end presents a relative short time, continues as previously mentioned in other words to be a low level, forms its delta pulse thus.On this time, this refresh control signal φ _RefPresent high level, and traffic pilot MPX is switched on those refresh addresses.That is to say, because refresh control signal φ _RefHigh level cause the inverter circuit IV of traffic pilot MPX ₃Output signal be low level, the institute so that MOSFET Q ₅₇And Q ₆₇Enter " ending " state.Thereby, suppress address signal a from address buffer X-ADB ₀-a ₈Send.At this moment, because refresh control signal φ _RefHigh level, cause the MOSFET Q of traffic pilot MPX ₅₁And Q ₅₄, Q ₆₁And Q ₆₄Or the like enter " conducting " state.If carry signal Ca is in low level, MOSFETs Q so ₅₂, Q ₆₂Deng just entering " ending " state, and MOSFET Q ₅₅, Q ₆₅Deng just entering " conducting " state.Therefore, this traffic pilot MPX adds to MOSFETs Q ₅₆, Q ₆₆Deng grid on refreshing address signal b ₀-b ₈On the contrary, if carry signal Ca is on the following high level that will illustrate, then with MOSFETs Q ₅₂, Q ₆₂Deng switching to " conducting " state, and with MOSFETs Q ₅₅, Q ₆₅Deng switching to " ending " state.Therefore, this traffic pilot MPX will send from storage circuit, and be to be added to MOSFETs Q ₅₃, Q ₆₃Deng grid on refreshing address signal C ₀-C ₈In other words, when this carry signal Ca is in low level, and when being in high level, will refresh the memory cell of those long datas retention time and the memory cell of those short data retention times respectively.

Counter circuit CT ₁Finish and the counting operation of negative edge synchronised to the delta pulse φ of its input.Owing to be with this counter circuit CT ₁The highest significant position signal produce this carry signal Ca, and it is added to next stage counter circuit CT ₂Input end, therefore, this counter circuit CT ₂On each negative edge of this carry signal Ca, finish the increment operation.So, on the angle of delta pulse φ, by counter circuit CT ₁And CT ₂The first refreshing address signal b that forms ₀-b ₈Increment operation, be interrupted with 1/5th ratio.

When this increment is operated once being interrupted, in other words, in a single day enter moment of high level at this carry signal Ca, then as mentioned above, this traffic pilot MPX switches, thereby it is sent remain on by selecting signal DS ₀-DS ₃In a memory circuit of selecting the signal appointment in address signal c ₀-c ₈, this selects signal is by with its counter circuit CT ₃Output signal decipher and generate.

Because so such mode of operation is this refreshing address signal b ₀-b ₈Increment operation be to finish by four delta pulses among five delta pulses, and a remaining delta pulse sends out the address signal c that is stored ₀-c ₈In other words, be under the situation of aforesaid 9 signals at address signal, complete refresh cycle of the present embodiment is not made up of 512 (=4 * 128) cycles, but is made up of 5 * 128=640 cycle.In this 640 cycles, be used to be connected to those and have refreshing of four word lines on the short data retention time memory cell, need altogether to carry out 128 times.That is to say, each bar word line is refreshed 32 times.In other words, for normality memory cell (having the long data retention time), during a refresh operation of its execution, the memory cell of those short data retention times just must be through 32 refresh operations.

When as mentioned above its refreshing address signal of change, then the transition that produces this address signal by address signal transition detecting device ATD detects pulse φ _rAnd φ _c

The transition of this timing pulse signal generator TG and its address signal detects pulse φ _rAnd φ _cThe selection circuit that resets to synchronised and once store array M-ARY.In other words, by means of timing pip φ _Pa1And φ _Pa2(φ _Pa1, φ _Pa2) make sensor amplifier SA enter off working state, thereby its complementary data line D and D are provided and the read data of front or the high level and the low level of the corresponding to quick condition of write data.In addition, make word line select timing signal φ _xAnd data line is selected signal psi _yBecome low level, thereby make each code translator enter off working state.Afterwards, precharge pulse φ _PcwPut high level one time, thereby, realize foregoing half precharge operation thus this complementary data line short circuit.After this precharge operation finishes, make word line select timing signal φ _xBecome high level, thereby select word line according to received address signal.And then, by means of timing pip φ _Pa1And φ _Pa2(φ _Pa1, φ _Pa2) make sensor amplifier SA enter duty, thereby amplify to prepare to read into the data that memory cell stored that complementary data line D and D get on, and it is sent to these complementary data line D and D gets on.As the electric charge of memory cell stores data, once since word line selection operation institute may be subjected to some lose, the level by direct reception complementary data line D and D have amplified also just has been resumed.By means of this mode of operation, refresh the data that memory cell stores.

In read operation or write operation, this column decoder C-DCR produces one and data line selection timing signal φ _yCorresponding to selection signal, and it is added to row switch C-SW.So, just pair of data lines D and D and shared complementary data line CD and CD have been connected together, caused the data line D that is coupled with this and the corresponding to data of D level just appear at this shared complementary data line CD and CD has gone up.In read operation,, the read signal that reads into this shared complementary data line CD and get on is amplified by main amplifier MA.By means of timing pip φ _RwHigh level, make data output buffer DOB enter duty, read to export D thereby externally send one on the tip node I/O _OutPassing through by means of timing pip φ _RwHigh level, make high level write signal and the low level write signal of its data input buffer DIB that enters duty, by shared complementary data line CD, CD, row switch MOS FETs Q ₄₂, Q ₄₃And complementary data line D, D(are above all not shown to this) write memory cell.

In refresh operation, when for example the time cycle of complete necessity of being made up of 640 cycles is arranged on 64 milliseconds (ms) one, refresh cycle for those normality memory cells is exactly 64 milliseconds (ms) so, (ms) and be exactly 2 milliseconds for those refresh cycles with memory cell of short data retention time, it is 1/32 of the former refresh cycle.

According to this method,, can reduce the number of times that refreshes widely really, thereby can reasonably reach lower power consumption compared with situation about in the prior art all memory cells all being refreshed with the cycle of same 2 milliseconds (ms).

According to the present invention, we have obtained following effect:

(1) the saltus step ground that refreshes that will have short data retention time memory cell inserts the refresh cycle, therefore, generally speaking, can make the refresh cycle lengthening.This just makes it might reduce the number of times that refreshes widely, therefore obtains the effect that reduces power consumption significantly.

(2) adopt (2 ⁿ-1) conduct of frequency division system counter circuit provides the circuit of the refresh cycle of those short data retention time memory cells that saltus step in the refresh cycle, and utilizes the highest significant position of this counter circuit.This just and then draw and can produce the effect of two kinds of refresh cycles by ball bearing made using.

(3) by a kind of refresh cycle in this two kinds of refresh cycles suitably is set, it just might to those very the memory cell of short data retention time prevent when handling as defective position.

(4), then improved the qualified percent of semiconductor memory product owing to above (3) point.

(5) it might prolong the time cycle of access memory.

Though below invention that the inventor is made made explanation particularly together with some embodiment; but do not need to speak more, the present invention never is only limited to above-mentioned embodiment, and we can say; not being separated within the protection domain that the present invention claims, can make various remodeling.

For example, in order to store the address signal C of N bar word line ₀-C ₈, it also can form Fractional-N frequency system counter CT ₃And N memory circuit of formation.

This counter CT ₁Also can be 9 frequency divisions (=2 ³+ 1) system counter.At this moment, this counter CT ₁Send out signal b ₀-b ₂

In the present embodiment, by the output signal (a of traffic pilot ₀-a ₈, b ₀-b ₈Or c ₀-c ₈) and inversion signal form its inner complementary address signal a ₀- a ₈But the complementary address signal of obtaining with row address buffer X-ADB a ₀- a ₈, can be added to traffic pilot MPX and get on.In this case, other address signal b ₀-b ₈And c ₀-c ₈, also be with complementary signal b ₀- b ₈And c ₀- c ₈Form be added to this traffic pilot MPX and get on.Adopt this measure, can make semiconductor memory provide very high operating speed.

Though this circuit be more complicated, but this traffic pilot MPX still preferably should be by means of adopting one to enter duty, perhaps for example enter the cmos circuit of high output impedance state, stop the appearance of DC current by control signal as previously mentioned.In addition, being used to produce the circuit of saltus step refresh cycle in the refresh cycle can be any circuit.This address storage circuit can be any circuit except the circuit that includes fuse, for example can be the circuit that the grid of MOSFESs is opened circuit.

The practicable circuit arrangement that constitutes this other peripheral circuits of dynamic ram can be adopted the characteristic of each side.For example, can be address signal from adding to come in address gating signal RAS and CAS synchronised and with the public address tip node of multipath conversion form.As refreshing starting system, might adopt the characteristic of each side in this case, in a system, at rwo address strobe signals RAS(CBR) before, make column address gating signal CAS become low level.In addition, can also utilize dummy unit to be formed for the reference voltage of memory cell read operation.

The present invention is the MIS(metal-insulator semiconductor at the electric capacity of memory cell) be effective especially during type electric capacity.This electric capacity can make semiconductor chip to its electrode, perhaps semiconductor region.Yet no matter which type of structure this capacitor may have, and the present invention share.

Can for example have the dynamic ram of inherent refresh circuit with expanded application of the present invention in many semiconductor memories.

Claims (8)

1, semiconductor memory, it has refresh control circuit, it is characterized in that, this refresh control circuit comprises the address counter circuit that forms refreshing address signal, points out the address memory circuit of concrete refresh address and the address switch circuit that is sent in the concrete refresh address that has in this memory circuit, and above-mentioned address counter circuit is finished many step increments operations at every turn.

According to the semiconductor memory in the claim 1, it is characterized in that 2, above-mentioned address counter circuit includes one and receives (2 of delta pulse ⁿ+ 1) first counter circuit of frequency division system, and second counter circuit that receives the highest significant position output signal of above-mentioned first counter circuit, wherein refreshing address signal is to be formed by each the output signal and each the output signal of above-mentioned second counter circuit of above-mentioned first counter circuit except its highest significant position, and the control signal that wherein adds to above-mentioned address switch circuit is that the output according to the above-mentioned first counter circuit highest significant position forms.

3, according to the semiconductor memory of claim 1, wherein above-mentioned address storage circuit stores address signal by cutting off fuse unit selectively.

4, semiconductor memory is characterized in that:

A plurality of memory cells;

Refresh the coupling device of the memory cell of assigned address with the period 1;

To the coupling device of the memory cell outside the memory cell that refreshes with the period 1, wherein be longer than the period 1 to refresh second round second round.

5,, wherein can repeatedly realize refreshing finishing in the time interval of once refreshing with the period 1 with second round according to the semiconductor memory in the claim 4.

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