CN85105547B

CN85105547B - Memory access control system for an information processing apparatus

Info

Publication number: CN85105547B
Application number: CN85105547A
Authority: CN
Inventors: 谷口俊夫; 住本勉; 熊谷多加史
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1985-07-19
Filing date: 1985-07-19
Publication date: 1988-06-08
Also published as: CN85105547A

Abstract

The present invention relates to a memory access controlling system which is used for an information processing device with a buffer memory and a main memory. In the system, when an access request exists, if a data block to be accessed is not in the address of the buffer memory, storage requirement data from a data register is written into the buffer memory before the first datum of the data read out of the main memory is written into the buffer memory, and then the data register is released to receive the next request.

Description

The memory access control system that is used for a signal conditioning package

The present invention relates to a kind of memory access control system, more precisely, relate to a kind of memory access control system that is applicable to signal conditioning package with a primary memory and a memory buffer.

In the signal conditioning package that needs high-speed data processing operation, provide one than the main memory memory buffer of high speed read/write data more, in memory buffer, leave the data block of using always in the data block of primary memory in duplicating of partial data is provided to those, therefore, make it possible to the access request of a CPU is responded fast.As a kind of signal conditioning package with memory buffer, this install below gave in the instructions open, as, U.S. Patent No. 3,735,360, " the high-speed buffer operation in multiprocessing system " or U.S. Patent No. 3,829,840, " virtual storage system.”

In such signal conditioning package, should allow and to be reflected in the primary memory in the Data Update that memory buffer is carried out with buffer system.Up to the present, (Store-through) in the access system, when producing access in the data block in memory buffer, these data also are stored in the respective data blocks of primary storage in so-called " storage-by ".According to this system, owing to increase to the access times of primary memory, the advantage of buffer-stored fails to bring into play.

On the contrary, a kind of system of all knowing for the people is arranged, as " depositing in " (Store-in) system, use this system, when data storage/access request produces, need the data block of access to exist in the memory buffer, these data are only deposited in memory buffer, and the poke of primary memory does not change at this moment." deposit in " in the system at this, provide one with memory buffer in the corresponding change bit table of each data block be used for storing the bit that indicates whether Data Update.When needs will replace a data block (I) in buffer storage from new data several piece (II) swap-in in the main memory, if the change indicating bit corresponding to data block (I) in aforementioned table is set, then data block (I) is swapped out to the swap-in operation of carrying out data block (II) behind the primary memory.If the change indicating bit is not set, then omitted the operation that swaps out of data block (I), data block (II) is sent in the memory buffer.According to this " depositing in " system, only just can not satisfy memory read write request from CPU by primary memory not being carried out access to buffer memory access, data block in memory buffer is swapped out in the main memory device, so that can carry out data processing at high speed.

; during the described in front information processing with buffer system is generally installed; if the data of access are not in memory buffer the time; the whole data block that then comprises these data will be sent to from primary memory in the buffer-stored, then this data block is deposited in the predetermined address in the memory buffer.Therefore, in treating apparatus, for example, a data block is made up of 64 bytes, and this data block transmits data D from primary memory to memory buffer with each machine cycle one 8 byte units ₀～D ₇, following point can appear in this case, that is, if produce a data D about 16 bit bytes ₀And D ₁A whole deposit request time, usually as shown in Figure 1, up to reading last the data D that enters memory buffer from primary memory ₇Write operation finish after, from the data D of the data register of storage request ₀And D ₁Write operation finished, data register just can be opened, and could receive next request.

An object of the present invention is to provide a memory access control system in having the signal conditioning package of memory buffer, in this system, can reduce the time of the data storage processing that requires when the data of wanting access are not in memory buffer.

Another object of the present invention provides a memory access control system in having the signal conditioning package of memory buffer, in this system, can reduce needed according to accessing operation from the time of primary memory to the memory buffer transmission block.

Another object of the present invention is to provide a high-speed memory access control method for the signal conditioning package with memory buffer.

In order to achieve the above object, a memory access control system that is used for a signal conditioning package according to the present invention comprises:

A first memory is divided into many;

A second memory, being used for one is that duplicating of partial data in the first memory left on unit basis in, this second memory can be with the speed access higher than first memory, and has the memory capacity more less than first memory;

A data register is used for storing the data of memory requirement temporarily;

An address register is used for storing the address of the data of memory requirement temporarily;

Decision maker is used for sending the duplicating whether in second memory of data block that decision signal indication comprises address data designated in the address register.

The first memory access control device is used for controlling the operation of sense data from first storage and writes the operation of data in first memory;

The second memory access control device is used for controlling from the operation of second memory sense data and writes the operation of data to second memory;

The 3rd control device, be used for when a data storage request produces, providing control signal to come the identification signal of response determine device to first and second storage control devices, it provides by this way, when with corresponding to the data block of this request be replicated in the second memory time, the data in the data register are written in the second memory; And if when data block above-mentioned not in second memory, after the data in the aforesaid data register were written in the second memory, duplicating of the remaining data from the respective data blocks that first memory is read was written in the second memory.

For example, in the signal conditioning package that utilizes the storer that is made of two-stage storage system (primary memory and buffering storer), first memory is equivalent to primary memory, and second memory is equivalent to memory buffer.; utilize in the signal conditioning package of multilevel memory system at another kind; this multilevel memory system further is included in the intermediate buffer memory between primary memory and the buffering storer, and this intermediate buffer memory can be that first memory also can be a second memory.

In an embodiment of the present invention.

Second memory has a data storage areas that is made of many data blocks;

Decision maker has one the 4th device, be used for producing positional information and specify zone in the second memory, with box lunch by the data block at the data designated place, address in the address register duplicate not in second memory the time, deposit duplicating of this data block of from first memory, reading in.

Second memory as starting point, writes the remaining data from this data block of the data of data register and first memory according to the address of address portions of registers content decision in by the scope from the positional information specified memory territory of this address.

Simultaneously according to the present invention, an access method of storage that is used for a signal conditioning package, this device comprises that a first memory that is divided into many data blocks is the second memory that duplicates that the partial data in the first memory is left on the unit basis in being used for one, this second memory can be to come access data than first memory faster speed

This method is made up of the following step

The first step when data storage request produces, is judged about duplicating whether in second memory corresponding to the data block of memory address;

In second step, when judging that in the first step data block corresponding to memory address is not in second memory, specify to be used to store the storage area that duplicates of above-mentioned data block;

In the 3rd step, before being sent to second memory from first memory data block, the data of memory requirement are write in the zone of appointment in the second memory;

The 4th step, the remaining data in the data block that will from first memory, read and do not comprise that the data of memory requirement deposit in the zone of appointment in the second memory.

Preferably only read out the remaining data in a data block of first memory, thereby can begin to write second memory from the data the next address of storing the data of asking.

Further feature of the present invention and advantage can become very clear by following description taken together with the accompanying drawings.

Fig. 1 is the sequential chart of data storage operations in the conventional store access control system;

Fig. 2 is one to be used for explaining the sketch of the relation between primary memory and the buffering storer;

Fig. 3 is a sequential chart, shows the example of the data storage operations in a memory access control system according to the present invention;

Fig. 4 is a calcspar, shows according to embodiment of memory access control system of the present invention;

Fig. 5 is a calcspar, at length shows the buffer storage location 30 among the embodiment, main storage unit 50 and ADDRESS HYGIENE device 23.

Fig. 6 is one to explain that the data of carrying out to memory buffer deposit the sketch of operation in.

At first relation between memory buffer 300 and the primary memory 500 is described with reference to figure 2.Primary memory 500 has a certain size such mode with each data block and is divided into many, and for example 64 bytes, and each data block are all specified by column address 0 to n and row address 0 to m.On the other hand, memory buffer 300 has and corresponding column address 0 to n of primary memory and row address 0 to 3.Therefore, in this example, in the data block in primary memory (m+1), concerning each column address, there be duplicating of 4 data blocks can be deposited into memory buffer at most.When needing further to deliver to the same biographies of a data block (II) from primary memory 500 in the memory buffer certainly, and be in this state: for example, one row of memory buffer 300 have had four data blocks, a data block (I ') of being selected by the method for a kind of least-recently-used (LRu-least Recently Used) system withdraws from from the buffering storer, and data block (II) is stored in and replaces this data block in the memory buffer, at this moment, if with the content of the data block (I ') that withdraws from and the content of the respective data blocks in the primary memory (I) is different, then data block (I ') is swapped out in the primary memory 500.

Compare with the described legacy system of Fig. 1, the feature of memory access control system of the present invention will be showed by the sequential chart among Fig. 3.That is, when from CPU about as two data D ₀And D ₁Storage/access request when producing, and these two data each all have 8 byte units and be included in not in the data block in impact damper 300, according to the present invention, with the data D in the data register ₀And D ₁The operating in from primary memory 500 of memory buffer that be written to begin before being written to relevant data block in the memory buffer 300.Has only remaining data D ₂To D ₇(do not comprise data D ₀And D ₁) be sent to the memory buffer 300 from primary memory 500.Article one, the order that is used for above-mentioned data transmission can delivered to the access controller of primary memory when the data of memory buffer write from data register.Because faster to the time of main memory access to the time ratio of buffer memory access, the first data D that from primary memory, is reading then ₂Data D before the arrival memory buffer in the data register device ₀And D ₁Write fully, and this write finish after data register can be discharged immediately.In addition, according to the present invention, the fraction data (CPU has produced the storage request for it) that do not comprise this data division, in the data of a data block, can from primary memory, be sent in the memory buffer, to such an extent as to the data block in memory buffer transmit the piece that can finish than legacy system many.

Fig. 4 is the calcspar of the embodiment of the expression memory access control system of the present invention that is used for carrying out above-mentioned storage access.In the drawings, reference number 30 is a buffer storage location that comprises a memory buffer 300 and an address circuit, and reference number 50 is one to comprise the main storage unit of a primary memory 500 and an address circuit.In this example, as two registers, CPU _sUsually can use accumulator system.The memory address that the one CPU provides, a request code and storage data are respectively charged into register 1a, among 2a and the 3a.On the other hand, the memory address that the 2nd CPU provides, a request code and storage data are admitted to register 1b respectively, 2b and 3b.By selector switch 1c, register 1a to 3a that 2c and 3c select or the content of 1b to 3b are sent into address register 1 respectively, in request code register 2 and the memory data register 3, address register 1 is by 3 fields, the first field A, and the second field B and the 3rd field C form.The first byte section A and the second field address B of address register 1 represent the block address part, and its 3rd field C represents the address portion in this piece.For example, the size of piece is 64 bytes, and the field C of address portion has 5 bits in the physical block.In the field A and B that represent the block address part, field B is used as the column address of buffer address array 5, as described above field B specify columns address.The figure place of field B is to be used to specify each row of buffer address array 5 and required number.For example, when columns n was 32, then the figure place of field B was 5.Sequence number 4 is used for controlling selector switch 1c, 2c and 3c for request receives controller.

Sequence number 5 is buffer address arrays, store with the first field A corresponding each have the address high order digit part of data block in primary memory 500 in the memory buffer 300.This buffer address array is made up of 0 to n row and every row have and memory buffer 300 similar 0 to 3 row addresses.Sequence number 7 is piece substitution tables, indicate the row address of each row in data block, thereby will withdrawing from, this data block can in memory buffer, add new data block from the buffering storer, sequence number 8 is tables of storage change indicating bit, and whether the poke that is used to refer to each data block in memory buffer changes.

When the storage address, request code and stored data are placed on

register

1,2 and respectively at 3 o'clock, whether check that by the data retrieval of buffer address array 5 data on the address are present in the buffer storage 300 or do not exist in address register 1.Finishing in such a way promptly of this data retrieval work: be used in the content that the value among the second field B is come 4 row of playback buffer address array 5 in the address register as a column address, and will compare by comparer 6a, 6b, 6c and 6d from the value among the value of the storage address that every row is read and the first field A address register 1.This comparer 6a to 6d respectively corresponding to rank addresses 0 to 3.By output according to each comparer, line number decision circuit 13 decision row addresses, sequence number 14 is coincidence detection circuitry, when one of them generation one in those comparers met output, this circuit was put an output 14S and is " 1 ".One selector switch 16 is controlled by the output 14S of coincidence detection circuitry 14.When output 14S was " 1 ", the output of decision circuit 13 line numbers was put into register 17 by selector switch 16.When the output 14S of coincidence detection circuitry was " 0 ", the output 9S that selector switch 16 allows code translators 9 was to the output decoding of the piece substitution table 7 that will offer register 17.Therefore, when being present in the buffer storage by the desired data block of CPU, the row address in the relevant data block is put into register 17, and in opposite situation, the row address in the data block that should change from the buffering memory is placed into register 17.The output 17S of register 17 in address register 1 the second and the 3rd field B and the output 1BC of C be provided to buffer storage.

The output 14S that meets decision circuit 14 also is imported into 3 input AND gates 19 and 20, one buffer storage access controller 21, an and main memory access controller 22, be used for output signal 11S that desired coding is deciphered, and the change indicating bit also is imported into AND gate 19 and 20 in the table of being selected by a selector switch 10 8 from code translator 11.The output 19S of AND gate 19 is supplied to buffer storage access controller 21, a main memory access controller 22 and a main memory ADDRESS HYGIENE device 23, and this corrector will be described in the back.The output 20S of AND gate 20 is provided and supplies with controller 21 and corrector 23.

When the output 14S of coincidence detection circuitry 14 and change indicating bit 10S be " 0 " and the output signal 11S of code translator when being " 1 ", the output 19S of AND gate 19 becomes " 1 ".When one when CPU produces a storage request, for example whole storage requests of described in front 16 bytes, signal 11S becomes " 1 ".Therefore, in this embodiment, when new data block when main memory is sent to the buffer storage, and operation does not swap out, the output 19S of AND gate 19 indicates the beginning of buffer storage access controller 21 storage operations as a drive signal, and the beginning of indicating the data transmission of main memory access controller 22.

The output signal 20S of AND gate 20 allows the data in buffer storage to be swapped out in the main memory as a control signal.When a coincidence detection signal 14S is " 0 " and change indicating bit 10S when being " 1 ", output signal 20S becomes " 1 ".When controller 21 received the level"1" of signal 20S, its allowed one to be swapped out from buffering memory 300 by signal wire 17S and 1BC data designated piece and to enter main memory, and this swap out finish after, put signal 21C and be " 1 ".AND gate 18 in the output circuit of change indicating bit 10S is controlled by signal 21C.When signal 21C was changed to " 1 ", the output of AND gate 18 was by reset.Therefore, the output 19S of AND gate 19 becomes the output 20S that " 1 " replaces AND gate 20; Thereby because 21 beginnings of buffer storage access controller are carried out storage operation and are begun the data block transfer operation by main memory controller to memory buffer.

Fig. 5 illustrates buffering memory cell 30, the details of main memory unit 50 and ADDRESS HYGIENE device 23.

In buffering memory cell 30, the second and the 3rd field B in address register 1 and the storage information 1BC of C are brought in the address register 32 by selector switch 31 at first period of storage.The output 32S of address register 32 carries out addressing to buffer storage 300.In addition, after address 32S was upgraded by an increment circuit 33 with circulating type function, this address output 32S was kept by a delay time register 34.Selector switch 31 is by control signal 21S ' control, and this control signal slave controller 21 is exported.In second period of storage and thereafter in the period of storage, the output of delay time register 34 is brought into address register 32.On the other hand, stored data 3S from 8 byte units of data register 3 output, be brought into a data buffer 36 by a selector switch 35, and be stored on the position of address 32S in the storage area, this position is at the selector switch 37a by being selected by row address 17S, on the row of selecting in buffer storage 300.

In the address register 1, the OPADD 1ABC of first to the 3rd field, the OPADD 1BC of the second and the 3rd field, and be imported into the main memory ADDRESS HYGIENE device 23 by the data block address 12S that reads from buffering address array 5 that selector switch 12 is selected.This corrector 23 comprises: an ADDRESS HYGIENE circuit 24, and this circuit causes skipping address 1ABC by a relative data length value, and this data length has been finished the storage request; Also comprise a lock-in circuit 26, produce an address 26S overleaf, be used for swapping out by combination of address 1BC and 12S; Also comprise a selector switch 25, select address 1ABC and any one of proofreading and correct among the 24S of address to come responsive control signal 19S; And also comprise a selector switch 27, and select any one among address 26S and the selector switch 25 OPADD 25S, come responsive control signal 20S.

Main memory unit 50 comprises: a selector switch 51, from the address 23S of main memory ADDRESS HYGIENE device 23 output with from the address of delay time register 54 outputs, select wherein any one; Comprise an address register 52, the output of temporary selector switch 51; And comprise that also one has the increment circuit 53 around function, the output that comes scheduler register 52.Selector switch 51 is controlled by a control signal 22S, and this control signal is slave controller 22 outputs.This selector switch is selected address 23S in first period of storage, and selects the address increased progressively, i.e. the address of delay time register 54 outputs from next and the period of storage followed, and insert address register 52.

In Fig. 3, relevant 16 bytes of being narrated are stored request entirely and will be described as an example.From the address 1ABC indication of the address register 1 output scope of arbitrary data of-8 byte units 64 byte data pieces shown in Figure 6.In this case, when the first data D that writes into by buffer storage access controller 21 started from address 101, data can indicate 102 places sequentially to begin to read from data D in the address from main memory 500.Main memory ADDRESS HYGIENE circuit 24 is used for according to the address 1ABC of number of responses 101.Be that respective counts 102 begins to produce main memory and reads from the address.On the one hand, among Fig. 6, data D is deposited in after the buffer storage 300, in corresponding 64 byte data pieces, must get back to boundary address 100 from storage address 32A.Equally, even in main memory storage unit 50, the reading of data D also must be got back to boundary address 100 from next address 52S after finishing.Increment circuit 33 and 53 and correcting circuit 24 carry out the addresses, front and upgrade, this is because aforesaid cause around function.

Get back to Fig. 5, the data (D that reads from main memory 500 ₂To D ₇) sequentially be provided to buffering memory cell 30 by line 50S, and be input to data buffer 36 by selector switch 35.In addition, when reading request produces,,, take out data buffer 39 and line 30S(and be provided for the buffering memory cell by selector switch 38 from the data that impact damper 300 or main memory 500 are read), deliver to CPU.

Enter main memory 500 if will swap out from the data block that buffering memory 300 is read, the output 20S of AND gate 20 becomes " 1 ".In this case, the selector switch in unit 23 27 is selected the output 26S of lock-in circuit 26 and is exported as main memory address 23S.Locking output 26S is an address value, this address value by the data block that will be swapped out in main memory address indicated value 12S and storage in the address field B and the value 1BC of C form, this address indicated value is read from buffering address array 5, and this storage address is from address register 1 output.The address of lock-in circuit output 26S designation data in main memory, promptly these data at first read out from buffering memory 300 and swap out.Therefore, in main memory storage unit 50,, write into above-mentioned address location and address location afterwards, thereby data are updated in main memory 500 from the data that buffering memory 300 is read and provided in proper order by line 30S.On the other hand, for the swap out work of buffer storage to the main memory data block, between buffer storage 300 and main memory 500, a high-speed buffer register is provided, this high-speed buffer register has and resembles memory capacitys many data block, and the data block of taking out and entering this buffer register from buffering memory 300 can be sent in the main memory 500 with free time after this.

In the above-described embodiment, the embodiment of the present patent application is the two-stage hierarchical storage device storage system of being made up of main memory 500 and impact damper 300 that has illustrated.Yet, in multistage hierarchical storage system, this system is between main memory and buffering memory, has one or more levels intermediate buffering memory, memory access control of the present invention can suitably be used between main memory and the intermediate buffer, between intermediate buffer and the intermediate buffer and the data transmission between intermediate buffer and the Must Significant Bit buffer storage.In this case, can be corresponding main memory than the memory in the low order in the present embodiment, and the memory on higher significance bit can be corresponding buffer storage.

In addition, provided formation in the above-described embodiment, thereby have only the data that need rather than write into the stored data of buffer storage 300, read from main memory 500, and utilize main memory storage ground corrector 23 that these data are sent in the buffer storage 300 from register 3.Yet, as an improved form, also may adopt a kind of like this structure, when all data sub-block are read from main memory, and when writing into buffer storage, the write operation of stored data is not carried out.In this case, because the operation of the data-storing from the data register to the buffer storage, carry out with walking abreast to main memory data sense order, the advantage that discharges data register rapidly is utilized, so desired next storage information can earlier be received.

On the other hand, the data transfer operation when producing the whole storage request of 16 bytes has provided explanation in the above-described embodiments, but the present invention obviously simultaneously can use any other stored data request, and is not limited only to above-mentioned said full storage request.

Claims

1, a memory access control system that is used for signal conditioning package comprises:

A first memory that is divided into many;

One second memory, be used for storing with duplicating of partial data that is the unit basis will be left in the above-mentioned first memory, this second memory can be coming access than first memory faster speed, and second memory is littler than the memory space of first memory;

One data register is used for the data of storing a memory requirement temporarily;

One address register is used for storing the address of the data of above-mentioned memory requirement temporarily;

Decision maker is used for sending a decision signal and indicates duplicating whether in second memory by the specified data place data block in the address in the above-mentioned address register;

The first memory access control device is used for control from the operation of above-mentioned first memory sense data with write data manipulation to this first memory;

The second memory access control device is used for control sense data operation and write data manipulation in above-mentioned second memory from above-mentioned second memory;

The 3rd control device, be used for when a data storage request produces, providing control signal to come the decision signal of response determine device to above-mentioned first and second memory access control apparatus, with box lunch corresponding to the data block of above-mentioned data storage request be replicated in the above-mentioned second memory time, the data in the above-mentioned data register are written in the second memory; It is characterized in that: described the 3rd control device provides control signal to respond from the next decision signal of above-mentioned decision maker to first and second control device when data storage request produces, when above-mentioned data block duplicate not in second memory the time, after data in above-mentioned data register were written in the second memory, duplicating of remaining data was written in the second memory in the above-mentioned data block that will read from first memory again.

According to the system of claim 1, it is characterized in that 2, described second memory has a data storage portions, this memory block has the capacity of a plurality of data blocks;

Above-mentioned decision maker has one the 4th device, be used for producing a positional information and specify in zone in the second memory, so as by the data block at the data designated place, address in the address register duplicate not in second memory the time the duplicating of above-mentioned data block that will from first memory, read store;

Above-mentioned second memory is in its scope of memory block that is begun to be written to the data the above-mentioned data register with from the remaining data in the data block of first memory that above-mentioned positional information determines as starting point by the address of the partial content of above-mentioned address register decision.

3, according to the system of claim 2, it is characterized in that: this system comprises that further the data length that is used for depositing according to storage proofreaies and correct from the device of the address value of above-mentioned address register output,

By this, above-mentioned first memory is the starting point remaining data (not comprising the data of storing from above-mentioned data device storage) the sense data piece sequentially from the above-mentioned address of proofreading and correct,

Above-mentioned second memory is followed the storage from the data of above-mentioned data register, will deposit in proper order from the data in the first memory.

4, according to the system of claim 2, it is characterized in that: above-mentioned decision maker has one the 5th device, in this device, whether stored a representative for the piece of each data in second memory needs above-mentioned data block is write indication information in the first memory, and when by the data block at the specific data place, address of address register duplicate not in second memory the time, this device output and the corresponding above-mentioned indication information of above-mentioned positional information data designated piece

Described the 3rd control device provides control signal according to above-mentioned indication information to above-mentioned first and second memory access control apparatus when data storage request produces, this control signal produces by this way, after the data block in second memory by above-mentioned positional information appointment is written to first memory, data in the data register are written to second memory, and data are written in the second memory from first memory then.

5, according to the system of claim 4, it is characterized in that also having a device, be used for the address value from address register output being proofreaied and correct according to the length of the data of require storage,

Above-mentioned first memory is the remaining data (not comprising the data of storing from data register) that starting point is sequentially read a data block with the address of above-mentioned correction,

The storage that above-mentioned second memory is followed from the data of above-mentioned data register will sequentially deposit in from the data of first memory.

6, an access method of storage that is used for signal conditioning package, this device have one and are divided into some first memory; With a second memory, be used for the duplicating of partial data of first memory being stored being the unit basis with the data block, this second memory can is characterized in that this access method of storage comprises with than the access of first memory faster speed:

The first step when a data storage request produces, is judged duplicating whether in second memory corresponding to the data block of memory address;

Second step, when in the first step, judge corresponding to the data block of memory address duplicate not in second memory the time, designated storage area stores duplicating of this data block in second memory;

In the 3rd step, before from first memory, being sent to this data block in the second memory, the data of above-mentioned memory requirement are written in the zone of appointment; With

In the 4th step, the remaining data of a data block of reading from first memory (data that do not comprise above-mentioned memory requirement) is written in the zone of appointment in the second memory.

7, according to the method for claim 6, wherein from first memory, only read out in the remaining data in the data block, thereby can begin to be sequentially written in the second memory from the data on the next address of the data of above-mentioned memory requirement.