CN85105488A - The progressive-scan tv equipment that is used for non-standard video signals - Google Patents

Abstract

Phase detectors in a progressive-scan tv receiver (202,204) are measured video " acceleration " memory of this receiver and " are read " (8f _Sc) and " writing " (4f _Sc) clock is with respect to the phase place of the double line frequency horizontal time-base (FB) of this display.The vision signal of deferred mount (34,36) to receiving from memory (30,32), poor (224) are that function provides delay between " reading " and " writing " clock phase value during with each " reading " memory, this delay reduces visible picture effectively.When this visible image also may occur in demonstration " non-standard " vision signal, when promptly the colour subcarrier of incoming video signal is different from the radio and television standard of appointment for the ratio of line frequency.

Description

The progressive-scan tv equipment that is used for non-standard video signals

The present invention relates to television equipment, more specifically say to relate to the orthogonal decomposition rate that television equipment that employing " lines by line scan " has increased display image effectively.

" line by line " the scanning television receiver has been known, wherein, improved horizontal frequency, promptly this scanning frequency is doubled, and each row vision signal shows twice, therefore it can provide and have the display image that has weakened the photo structure visibility, and the subjective orthogonal decomposition rate of having improved.In one was typically lined by line scan receiver, each row vision signal was within one that is stored in two memories.An incoming video signal in order to the standard line frequency in these two memories " is write " fashionable, and another memory " is read " twice with the line frequency of twice.Therefore, two video line of time compression in a standard line period are provided.The output of this memory is added on the display unit, and this display unit has the double horizontal frequency of " reading " to go out signal Synchronization with this memory.Therefore, the number of the display line of vision signal is doubled.

The invention of granting R.A.Dischert November 15 nineteen eighty-three is entitled as the United States Patent (USP) 4 of " TV with double level shows ", 415, the example of the receiver of lining by line scan has been described in 931, wherein the video line of Zeng Jiaing not by original scanning capable in interpolation.In addition, grant the United States Patent (USP) 4 of the exercise question of K.H.Powers for " having the television display system that reduces light image " in August 23 nineteen eighty-three, insert in having described the scan line that increases in 400,719 and being original scanning capable in, and obtained a kind of double scanning frequency receiver.Disclosed scheme is incorporated among the present invention as a reference in the above-mentioned patent.

When realizing lining by line scan of receiver with the circuit of processing digital signal, people can adopt random-access memory (ram) as the row storage.Typical Digital Signal Processing is to utilize a relevant clock for the sample of signal purpose (in the A/D converter), storage address control and other functions.For look being handled for simplicity, being typically clock is phase-locked on the integral multiple of color subcarrier.Say that for TSC-system formula vision signal this memory " is write " clock frequency and generally elected the frequency (4fsc) that is four times in colour subcarrier as, perhaps is approximately 14.3MHZ, the cycle is about 70ns.Clock frequency and be approximately the line period of 63.5nS TSC-system formula hereto, then a memory lines needs 910 unit in RAM, goes to store 910 frequency sample pixels (pictorial element).The requirement of sort memory says it is constant for the NTSCR standard signal, because in the TSC-system formula, each level all exists accurate 227.5 color subcarrier cycles.Therefore, when carrying out the D/A conversion on being four times in the frequency of colour subcarrier (4fsc), every provisional capital accurately exists 910(4 * 227.5) individual pixel.As long as memory " is read " twice that clock accurately is " a writing " clock frequency, when showing, then " speed that doubles " of Chan Shenging or the pixel of " time compression " will evenly distribute in the horizontal direction, and line up a line in vertical direction.

People here have realized that in the progressive-scan system of the type of having described, when display image, exist a delicate problem, and promptly what is the non-standard video signal of indication herein.Be meant that as " non-standard " vision signal one speech that has used in this article its color subcarrier and the ratio of horizontal line frequency can not accurately meet a kind of vision signal of broadcast standard of regulation (for example being 227.5) in the TSC-system formula.For example, wherein this video signal source can be a video disk playback machine, a video cassette recorder, an electronic game machine, or some other non-standard video signal sources.And the ratio of color subcarrier changes in a continuous scope under some restriction, and these restrictions can be included in the number range (for example, from 226.5 to 228.5), significantly depart from standard ratio.Under these conditions, the video sampling number (pixel) in horizontal cycle can not be that 910(4fsc " writes " clock generally).In other words, be included in the 4fsc clock cycle number of a horizontal line in the cycle and will be different from standard value, and this difference may comprise the part of a pixel.

The deviation of the sampling number of every row and preferred number (910) is insoluble, because this deviation has been represented the precession of A/D converter sampled signal clock phase with respect to input level synchronizing signal phase place, this precession effect, or " phase slip ", or " distortion " is the accumulation of horizontal timing error during whole each field scan.In addition, in the system of lining by line scan, one of them relevant 8fsc " reads " (2H) standard deflection frequency of clock with twice, is used for showing.This 8fsc " reads " precession of clock to the 2H deflection frequency, will double 4fsc and " write " precession of clock with respect to the 1H incoming video signal.This problem is that the system of lining by line scan is peculiar, and under this assumed condition, can cause 12%(or higher) line time at interval more than field time horizontal timing error at interval, perhaps cause regularly discontinuous of whole pixels between the respective columns.This visible effect is exactly scalloping, and burr or other are not wished the picture that occurs.

In view of the foregoing, a kind of admissible method is that " quickening " carries out preliminary treatment to vision signal before in the progressive scan processor (PSP) with conventional time base corrector (TBC).Be applicable to people's such as the visible Ito of example the United States Patent (USP) 4,249,198 of time base corrector of video tape recorder (VTR) reproducing signal and the United States Patent (USP) 4,443,821 of Kato.Cause will be quoted above-mentioned two patents, and in this insertion.In people's such as Ito patent, the digitized video that is provided by an asynchronous VTR is stored in the memory of TBC (one), and this memory location is to control according to the phase difference between an input video synchronization signal components and the constant reference signal (for example, machine inter-sync signal) with the delay before of this vision signal of storage.The TBC of Kato addresses " in the row " velocity error of proofreading and correct the VTR reproducing signal, and comprises a velocity error detector, is used for detecting line by line the velocity error that " writing " goes into vision signal in the memory.Output at the TBC memory has individual sampled level compensator, be used for adjusting the level of " reading " the video sampled signal that goes out from memory, make it become the function of the velocity error of detection, so that the sampled level that " reading " gone out is corrected for when equaling not have velocity error, due " reading " goes out sampled level.

In this article as can be seen: use conventional time base corrector can not solve the distinctive problem in (hereinafter all being referred to as " the pro-scan ") video display system of lining by line scan of depositing, problem in the system of lining by line scan not only comprises time base error (for example: " moving "), also comprise the non-standard signal that every capable number of pixels changes, and double " reading " at only each row of the system of lining by line scan and go out, and this variation has been doubled effectively.

The problem of narrating above can not be present among the conventional time base corrector, because every row " reading " once in the conventional time base corrector.In brief, in the display system of lining by line scan, for non-standard video signal (as hereinbefore defined), second memory " reading " operation can require a kind of first memory " to be read " the different time base compensation of operation, and each " is read " operation and can require slowed-down video compensation, and this compensation is the part of pixel period.In addition, if do not compensate, then, certainly will accumulate as previously mentioned owing to due to the non-standard signal, change " reading " error that causes by every capable number of pixels.

According to a kind of display unit of lining by line scan of the present invention, comprise being used to measure and " read " and the phase place of " writing " clock with respect to the memory of the horizontal time-base that shows, this device provides delayed video signal born again from memory, this signal is each memory when " reading ", the function of " reading " of measurement and the clock skew of " writing ".

With reference now to accompanying drawing,, with example explanation the present invention, in the accompanying drawing, identical unit is marked with identical identity code, wherein:

Fig. 1 is a block diagram of implementing television receiver of the present invention.

Fig. 2 is the more detailed block diagram of the part of Fig. 1 television receiver.

The television receiver of Fig. 1 comprises an input that is connected with TV signal source 10.When being connected to the antenna of an acceptance criteria broadcast singal, the signal that receives should meet a kind of television system, and (for example, NTSC), wherein the color sub-carrier number of cycles of each horizontal line is accurate known (for example, 227.5).When other video signal source is connected, such as a kind of " consumption electronic product ", video disk or video tape recorder etc., as having discussed in the past, the ratio of its colour subcarrier and line frequency may be different from accurate broadcast standard, if and this difference is not compensated, as hereinafter will going through, may cause demonstrating various observable pictures.

Input 10 be connected to a conventional design for a base band video output signal S is provided ₁Adjuster/IF processing unit 12.In order to simplify, the Audio Processing part is not shown among this figure.This baseband video signal S ₁Be added on an analog to digital (A/D) converter 14, and be applied on the timing unit 16.Unit 16 comprises conventional synchronizer and colour subcarrier wave detector and leggy locking ring, produces to comprise that phase place is locked into the (8f on octuple and the four times of color subcarriers respectively _Sc, 4f _Sc) memory " reads " and a plurality of timing signals of " writing ".Two/delegation frequency signal (FH/2) " is read "/" writing " selection usefulness for control storage, and two times of line frequency signals (2FH) are regularly used for 18 horizontal sweeps of receiver display.

Digitized vision signal S ₁Row alternately be applied to two progressive scan processors 20,22 respectively by change over switch, change over switch 24 is timing signal (FH/2) control of 1/2nd line frequencies that provided by timing unit 16.For the ease of discussing, suppose that change over switch 24 is in position up as shown in the figure, for vision signal S ₁Even number line deposit (" writing " goes into) processor part in, when change over switch 24 during in opposite position, for odd-numbered line, with signal S ₁" write " memory location of processor 22.

Processor 20 and 22 for example comprises the memory cell 30 of a conventional design and 32(separately, and a Random Access Storage Unit 16 receives that 4f " write " clock signal and 8f " reads " clock signal.Memory 30 and 32 output are incorporated into change over switch 40 through variable delay unit 34 and 36 respectively, use for display 18 through a digital analogue converter 42 again.Change over switch 40(position shown in the figure when even number line) output of memory 32 is incorporated into converter 42 and when the odd-numbered line, change over switch 90 is incorporated into converter 42 to the output of memory 30.

Each progressive scan processor 20 and 22 comprises delayed signal generator 50 and 52 respectively, and another variable delay unit 54 is also controlled in the delay of generator 50 control units 34, and variable delay unit 54 gives 8f _ScClock signal one variable delay is so that provide the clock signal C L-A of a distortion.Equally, generator 52 is incorporated into unit 36, inferior and another variable delay unit 56, and unit 56 provides the 8f of a variable delay _ScClock output signal CL-B.These two clock signals are incorporated into the input end of clock of D/A converter 42 through another switch 60.Switch 60 is synchronous with switch 40, so that make D/A converter 42 with progressive scan processor 20 and 22 alternately receiving video signals and clock signal.

Except handling variable delay, just as will be descr, the operation principle of the receiver of all lining by line scan all is conventional.Simply say digitized video S ₁Alternately be stored in memory 30 and 32.For example, " write " when delegation and to go into memory 30 devices, it has been deposited in memory 32 before this, and it just " is read " twice so, and the signal of analog form is got back in conversion in converter 42, then at display 18(for example, picture tube or Projection Display) in show.This display has double horizontal frequency (2FH), therefore, all shows two video line for each row that receives.Second row of per two row can As be well known in the artly insert, and perhaps second can be the accurate repetition of first row.Importance of the present invention is to determine the accurate starting point of each display line.And this accurate starting point is controlled by delay generator and variable delay unit in progressive scan processor 20 and 22 according to the present invention.

Generator 50 and 52 respectively comprise be used to measure corresponding memory " is read " and " writing " clock with respect to the circuit of double line frequency (2FH) the horizontal time-base phase place of display 18. Unit 34 and 36 can postpone the vision signal of regenerating from memory, this vision signal is each memory when " reading " operation, the function of " reading " of measurement and " writing " clock skew.Remember to say 4f for " non-standard " video input signals _ScThe phase place that memory " is write " clock is (slip) constantly handled with respect to the horizontal-drive signal component of incoming video signal, therefore also handles (with the speed that doubles) with respect to the horizontal deflection signal that is applied on the display 18.This " writing " clock is to measure at each top of " writing " between the departure date with respect to the phase place of horizontal deflection pulse (for example, the flyback pulse FB that obtains from display 18).This phase measurement can be expressed as " writing " pixel cycle (for adopting 4f _ScIt is 70nS that the TSC-system formula " is write " clock cycle) percentage, this " decimal " (hereinafter being referred to as TW) will be a number of a scope between 0 and 1.Number TW is stored, and when the row of this storage is regenerated from memory, is used for two " reading " operating periods then.When the row of memory was about to be shown, 8f was measured at the top of each in this two " reading " operation _Sc" read " phase place of clock with respect to horizontal deflection (flyback) pulse FB.These measurement results also can be expressed as percentage, and depend on that here it is that first of institute's storage line " read " beginning (TD-1), still second " reading " (TD-2) begin to be expressed as TD-1 and TD-2.

In general, for non-standard signal, this phase measurement is different, i.e. (TW) ≠ (TD-1) ≠ (TD-2).For this pixel is evenly distributed in the horizontal direction, and suitably line up a line in vertical direction, there are not " OK " or other undesirable pictures, in video channel, introduce selectively and postpone, therefore in fact the measured value of (TW=TD-1=TD-2) TW " is read " operating period and TD-1 comparison at first memory, and obtains the difference of (TW)-(TD-1)." read " operating period at second memory, carry out the comparison between TW and the TD-2 equally." read " operation for each, retardation (being expressed as the percentage that 35nS " reads " clock cycle) is added to shows signal by unit in processor 20 34 or the unit in processor 22 36 and gets on.So just proofreaied and correct the partial pixel circular error of non-standard video signal.

This correction signal, promptly the TC among the figure is applied to vision signal and the 8f that is used for D/A converter 42 _ScOn the clock, in vision signal, realize desired delay to guarantee this D/A converter.

Fig. 2 is a kind of suitable embodiment that explanation is used in delay generator in progressive scan processor 20 and 22.Flyback pulse FB is applied on two phase detectors 202,204, and these two phase detectors receive 4f respectively _Sc" write " clock and 8f _Sc" read " clock signal.Detector 202 and 204 is by " writing " and " reading " pulse (being provided by circuit 16) chain control.After flyback flyback pulse FB, when reading to save a 4f _ScWhen clock pulse arrived, this processor had write memory to first pixel.Detector 202 is measured flyback pulse and 4f _Sc" write " time difference between first cycle of clock, and (four a) binary number TW is provided, equal to differ 4f with this number _Sc16 of clock cycle/several numbers.This is equivalent to the magnitude resolution capability of about 4nS, says for practical application, is enough to be applicable to application of the present invention.Should deposit a latch 206 in through line frequency change over switch 208 by " writing " clock phase measured value TW, during next line, TW is latched into second latch 210.Change over switch 212 is synchronous with change over switch 208, so that the TW value of storage before " reading " to go out, and new TW value " is write ".

When a complete video line is deposited in memory 30, and " read " immediately to measure 8f with respect to flyback pulse FB by detector 204 _Sc" read " clock phase, and deposit the latch 220 of storage TD in.Be used for line by line the corrective delay TC of the variable delay unit of processor and be an adder 222 binary number " 16 " and storage numerical value TW addition, then in subtracter 224, from deduct that storage number TD determines.Therefore, for the video line of each (being 32 in processor 22 perhaps) regeneration from memory 30, the final numerical value of its delay compensation signal is represented by TC=TW-TD+16.Add severally 16, guarantee that TC is negative value never, has simplified subtraction circuit.This " compensation " is equivalent to a constant pixel delayed in whole system, and or can ignore (the overscanning district that it just is arranged in demonstration) or " read " processor storage and proofread and correct with the method for displacement one number in storage address.The scope of TC value is later on five binary digits from 0 to 31(addition), finish the control pixel delayed of this correction, will with one from 0 to 1 change, and pixel period is 15/16 signal delay quite (pixel period goes out to be approximately 35nS for " reading ").

Though, the generator 50(or 52 of Fig. 2) delay compensation be utilize handle part period of a pixel 16/several), this delay compensation can easily directly the time of being converted to handles.If so, consider this 4f _ScThe phase error of " writing " clock is with respect to 8f _Sc" read " clock and be doubled, Fig. 2 should be revised (simple 1 shift operation in binary arithmetic operation) divided by " writing " phase place value with 2.People it can also be seen that if use adder 222 though can follow subtracter 224, under the sort of situation, this subtracter must be handled negative.

Claims (5)

1, a progressive-scan tv equipment, it is by the input of a receiving video signals, comprise apparatus for video frequency signal store (30,32) device, be used for " writing " goes into signal and forms from the device of the clock signal of storage arrangement read output signal " reading " and " writing " with generation, each row signal that it receives according to the handle of TV signal generation that receives all becomes multirow, and be added to output signal on the display unit (18), and the line-scanning frequency of display unit (18) is selectable, so that each the row signal that receives is demonstrated said multirow.

It is characterized in that this equipment also comprises:

Be used to measure each said " reading " and " writing " clock signal device (50), and be used for postponing device (34) as the outputting video signal of the function that differs between " reading " and " writing " clock signal phase amount with respect to the phase place of the line synchronizing signal that links with display unit.

2, according to the equipment of claim 1, wherein for each row of the signal that receives, its outputting video signal includes repeated row.

3, according to the equipment of claim 1, wherein for each row of this signal that receives, this outputting video signal also comprises many row, has at least delegation to insert from this signal that receives.

4, according to claim 1,2 or 3 equipment, when wherein this deferred mount (34) was with each " reading " memory, difference postponed this outputting video signal as function between " reading " and " writing " clock phase value.

5, according to claim 1,2 or 3 equipment, wherein measurement mechanism is by forming with lower member:

One first phase detectors (202) " are write " when going into this storage device when each delegation vision signal, " write " phase place of clock with respect to line synchronizing signal according to one first chain control signal measurement; With

When one second phase detectors (204) " are read " to go out this storage device when each delegation vision signal, " read " phase place of clock signal with respect to line synchronizing signal according to second chain control signal measurement.

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