CN85105460A - Control method in the digital computer - Google Patents

Abstract

In the beginning of each data of processing and between tailend, the structure of a guide unit (directory unit) can store and relevant address and the control data of several high-speed caches (cache) data exchange, this guide unit has the ability the relevant capsule information of handling are in regular turn done one relatively with the corresponding data in being stored in it, so that whether conflict is arranged on the determination procedure exists.If conflict is arranged, then produce some controlling signal and go to eliminate this conflict, in addition, exist address and control data in the guide unit can be taken whole work datas of CPU are deposited in the appropriate location of high-speed cache.

Description

Control method in the digital computer

The present invention is relevant with the digital computer system, and the saying of the tight utmost point is the control element of this class computer system CPU inside of touching upon.

One of improved target of computer system is the amount that increases the system handles data.For asking like this, when needing the operative scenario of higher speed, cache memory has been used in the operation that to store data is purpose, that is to say, take out and calculate by main memory through CPU, amended data only exists in the high-speed cache (cache), and the data after the change is not sent main memory back to basically except under special case.In application case on the docket, also can notice, computer system can have the CPU main memory of common use when operation more than 2, in such system, up-to-date data item may only exist in the high-speed cache of a certain CPU, and in prior art, can allow data in the high-speed cache in some CPU, direct access under the requirement of another CPU of system.

But under the requirement that strengthens computer system processing data quantity, system must come work in the mode of streamline (pipe line), that is to say, in each time period in computer work cycle (cycle time slots), a series of instruction sequences can be sent to system input, and needn't wait previous instruction to finish.Therefore, in the pipeline organization that 5 time periods are arranged, can allow 5 different instructions under continuous different phase, to finish the work simultaneously.

The system that in the application case of aforementioned together pending trial, illustrates, whenever data moves into high-speed cache or when shifting out in it, be that mode with a whole message block (block) transmits, in the concrete practice of being lifted, each message block is made up of the data of 8 words (word), even yet that CPU is the word that is addressed to unit group work is little of a hyte (byte), whole message block contains addressed word and all is admitted to cache stores in the CPU.Data moves into high-speed cache than can reducing the suitable time from being moved into by main memory by CPU, this method need can control data flow (flow) with the data after guaranteeing to change can be correct the other data of the message block of taking out with main memory merge.

Basically, purpose of the present invention is providing an improved computer system to strengthen its DATA PROCESSING amount.

Another object of the present invention is in the computer system that an improvement is being provided, and how the method for managerial data flow is described under a pipeline system computer architecture.

Of the present invention advance a purpose shown in computer system in provide the method for a control caches exchange data, this method can allow several processors in the pipeline system computer system get same data.

When finishing whole purposes, can provide a guide unit according to the present invention, in the beginning of each data of processing and between tailend, can store and several relevant address and the control datas of high-speed cache data exchange, this guide unit has the ability the relevant capsule information of handling are in regular turn done one relatively with the corresponding data in being stored in it, whether there to be conflict to exist on the determination procedure, if conflict is arranged, then produce some controlling signal and go to eliminate this conflict, in addition, exist address and control data in the guide unit can be taken whole work datas of CPU are deposited in the appropriate location of high-speed cache.

The accompanying drawing summary

When reading, can more understand the present invention, comprise in the accompanying drawing from following detailed description and appended figure:

Fig. 1 is the calcspar that includes this type of electrical brain system of the concrete practice of the present invention.

Fig. 2 is the calcspar that is applicable to this Type C PU in the computer system shown in Figure 1.

Fig. 3 is the calcspar of structure middle port shown in Figure 2 (port) unit.

Fig. 4 is the storage guide that the present invention is specialized, its square key diagram.

The calcspar of Fig. 5 and Fig. 6 is described some function of storage guide shown in Figure 4 in detail.

Detailed Description Of The Invention

These accompanying drawings of now more careful reference, in computer system shown in Figure 1, have a processor (CPU) 2 and the 2nd CPU4, also have (CIU) 6 and the 2nd central interface unit (CIU) 8 of a central interface unit (central interface unit), the 1st CPU2 has way and the 1st CIU6 and the 2nd CIU8 swap date, the 2nd CPU4 can with the 1st CIU6 and the 2nd CIU8 swap date.Same, more than one I/O unit (Input/output units) is (I/OU) respectively available, these unit basically the CIU6 of system and 8 and the I/O peripheral unit between be to connect in multiplex (Multi plexed) mode.The 1st main memory unit 14 is connected with the 1st CIU6, and be same, and the 2nd main memory unit 16 is connected with the 2nd CIU8, and in such system, central processing unit 2 and 4 is carried out the calculating and the processing of data as usual.

Data is sent to I/O unit 10 or from its place's reception data, one of function that central interface unit 6 and 8 has can be between central processing unit and I/O unit and affiliated main memory thereof the traffic (traffic) of overhead.

Main memory unit 14 and 16 provides the data of the position that stores to deposit source book and to have been handled by CPU, in after this illustrated system, can see each central interface unit 6 and 8 can with one of two central processing units 2 and 4 swap date, these two central interface unit all with I/O unit 10 and 12 swap dates.In addition, in the concrete practice that the present invention lifted, one of these two CIU have the ability and system's main memory swap date under second half, therefore, can understand shown in this two half system between the have the ability mutual exchange of the data of doing.

Because the ability of mutual exchange material is arranged, some unit of system are necessary each other fully synchronously, for asking like this, control center 18 is available, in fact, the 18 suitable more further CPU of control center, the function of this CPU is in the action of the basic controlling of initialization system, comprise between the working cell synchronously.

Structure shown in Figure 1 has illustrated the working environment that this is.

Fig. 2 demonstrates formant or the subsystem in the CPU, all CPU2 as shown in Figure 1 and another have the CPU4 of same structure, CPU2 is the same also to have high-speed cache, and as shown in Figure 2, high-speed cache is divided into two parts or the unit is illustrated in the concrete practice of being lifted.One partly is instruction buffer memory 20, after this it is denoted as I-cache, another of high-speed cache partly is regarded as computing (operand) buffer memory 22 and after this is denoted as O-cache, wait more detailed explanation is arranged in trying a case in aforementioned Shelly and Mr.'s Tlubisky co-applications, central location (central unit) 24 with pipeline organization (CUPS) has been controlled the action of entire process device 2, instruction pick up that (fetch) device 26 can provide or the address of move instruction word to Instructions Cache 20 exclusive disjunction buffer memorys 22, after Instructions Cache was received the address of depositing instruction by instruction pick-up 26 places, phase reaction was that the instruction of this double word (Double word) is sent to instruction pick-up 26 by high-speed cache 20 or 22.Instruction pick-up 26 deposits a series of instruction or collect in the instruction storehouse (stack) in regular turn, and this storehouse is the part in the instruction pick-up 26.

Get instruction in the instruction storehouse of order by instruction pick-up 26 of the central location 24 of tool flowing water stack architexture (CUPS) according to formula.This CUPS unit 24 has 5 sections pipeline organization, this structure aforementioned co-applications wait try a case and Wilhite and Mr. Shelly together apply for waits to try a case, S/N 434, more detailed explanation is arranged in 196, CUPS handles the instruction that is obtained by instruction pick-up 26, and holds the decoding of operation code and the combination of computing address.

After this, can more detailed description, if required data exists in the high-speed cache, such data will be through divider (distributor) 28, is sent to more suitable in several execution (execution) unit one after being taken out by it and goes execution.

In the concrete computer system of giving an example in this place, the 1st in several performance elements is a central performance element (central excution) 30, the structure of this element is particularly suitable for carrying out the fundamental operation of computer, for example simply transmit (Moves), add, subtract etc., the further characteristic of this central performance element (CEU) 30 is that it can carry out computing on the basis of intending a reception (AS-received), the 2nd executive component is denoted as a virtual and peace manager (Virtual and security manager) (VMSM) 32, this element is carried out and virtual store (virtual memory), the special and security-related special instruction of operating system of instruction that data security is relevant and execution.The 3rd performance element is denoted as binary arithmetic operation device (BINAU) 34, the structure of this element tends to carry out the binary arithmetic instruction such as multiplication and division and floating-point operation instruction especially, the 4th executive component, in the practice of this explanation, be denoted as one numeral/literal performance element (DECCU) 36, this element is particularly suitable for carrying out and digital operation, literary composition one numeral and the relevant instruction of position word string.

Performance element 32,34, in 36 each all has an input storehouse, is respectively each performance element and collects, and confirm the instruction and the data of input in regular turn, same, performance element 30,32,34, all there is the storehouse of the result of depositing (result) each unit in 36, is respectively the result that each performance element is collected and confirm in regular turn to carry out.Formation (queue) 38 is carried out in instruction, and the order according to formula under center cell 24 controls of pipeline organization stores away the execution word of formation (queue).Collection controller (collector control unit) 40, the word that uses instruction to carry out formation goes to control the order that reads of final data, these data are present in performance element 30,32, in the storehouse as a result of each unit of 34 and 36, the result of these execution can see through being configured under such control situation of a selector switch 46 and deposit in main safe storage 42 or the storage stack 44.Formation 38 is carried out in instruction, collection controller 40, and main safe storage 42, storage stack 44 and selector switch 46 all are one to be denoted as the sub-assembly of gatherer (collector) 48.

More than all the prerequisites of explanation be the needed data of in high-speed cache 20 or 22, looking for.If needed data is not in high-speed cache, then main memory 14 promptly can be picked to obtain required data through CIU6, then, CIU sees through port unit (ports) 50 again, picked up by cache element 20 or 22, when the data that so obtains has deposited high-speed cache in, the action of CPU promptly as described above mode carry out.Out-of-date by the processing of the performance element more than 1 or 1 when the selected data that arrives, data will be by depositing in the structure of getting back to high-speed cache in the storage stack 44.

Fig. 3 shows the functional block diagram in port (ports) unit 50 that Fig. 2 quoted, and the major function of port unit 50 is the control that the interface is provided between CPU and CIU.Port unit has two main programs (sequences) to finish aforesaid control.Wherein the 1st relevant with the operating state of CPU streamline and interior high-speed cache thereof, the 2nd, port unit is duplicated the guide (directory) of high-speed cache and preserved, and after this is cited as and duplicates guide.

Finish these control function; port unit has some subitem assemblies; the 1st of these subitem assemblies is a pipeline dynamic controller 52; the 2nd such subitem assembly is one and duplicates guide dynamic control unit 54; in addition; also have one to duplicate guide 56; with an instruction storehouse (I-stack) protected location 58; a port is stored guide 60 and a zone (zones) controller 62; each subitem assembly all can see having some lead-in wires to pass in and out on these elements; these lines are to represent the signal of this type but not specify actual lead; signal is sent to or from these assemblies, simultaneously, has indicated many dotted lines respectively on CIU and CPU; these lines point out that the primary clustering in the computer system is not included within the port unit 50, and the assembly of port unit can with the aforementioned components swap date.

Pipeline dynamic controller 52 is that a logical circuit can provide between port unit 50 and CPU as main control interface.Streamline is carried out dynamic controller 52 and is located the signal that receives orders by computing buffer memory (O-cache).Because computing buffer memory (O-cache) and Instructions Cache (I-cache) are used in the work of CPU sometimes, so pipeline dynamic controller 52 must react to some extent to the command signal that relates to Instructions Cache (I-cache), will use computing buffer memory (O-cache) simultaneously as long as use Instructions Cache (I-cache), the order meeting that Instructions Cache (I-cache) comes is identical with the order that is come by computing buffer memory (O-cache), but has a signal can represent that its retrieval that relates to computing buffer memory (O-cache-only) data maybe can be to two memory search data in the command signal that computing buffer memory (O-cache) comes.Also can receive from the high-speed cache place signal point out to retrieve high-speed cache the result that is with " together " (HIT) or " difference " (MISS) represent this signal.The data that pipeline dynamic control module 52 comes these next orders of CPU and " result for retrieval " (SEARCH RESULTS) signal and other unit has mutual relation, after this have more detailed description, control module 52 also provides order and the controlling signal CIU under going to other assemblies of port unit 50 and the control command signal being sent to.

In addition, CPU under pipeline dynamic controller 52 can be sent to controlling signal, for example, one " depositing in " (STORE) or " writing " order (WRITE), controller 52 can be sent one " depositing in " control (STORE) signal to the result of gatherer 48 as the retrieval high-speed cache, controller 52 also provide one (BREAK) " interruption " controlling signal to high-speed cache also/or provide one " time-out " (HOLD) controlling signal to CUPS unit 24, these two signals of back are pointed out in the course of action of streamline, continuing to carry out called program can make the processing of back produce wrong result, that is, " interruption " (BREAK) and " time-outs " (HOLD) the signal control CPU work that temporarily stops CUPS unit and high-speed cache can continue to attempt program shown in the execution again with after eliminating in interference effect.

Pipeline dynamic controller 52 is also accepted " removing " that come by the CUPS unit (CANCEL) signal, this signal points out that in inside, CUPS unit one abnormal situation having taken place makes the signal in all streamlines behind a certain specific period to be eliminated, certainly, the CUPS unit elements will be reset the work of streamline.

Duplicate guide dynamic control unit 54 and can when guide 56 is duplicated in retrieval, produce some controlling signal.In CPU inside, each high-speed cache 20 and 22 all exists with the form of data array (data array) or guide array (directory array), and is general, and the address of guide An arrayed recording data is in the data array under data then exists.When high-speed cache is retrieved, the address of the data of looking for will be retrieved in guide, in port unit spare shown in Figure 3, duplicate the duplicate that guide is actually the guide array of 2 high-speed caches in the CPU, duplicating of guide can allow to do access faster in the port unit when data searching, because the guide that duplicates in guide and the high-speed cache can independently be retrieved, also can retrieve simultaneously.Duplicate guide gravity flow waterline dynamic controller 52 places and receive a command signal, the relevant action of this order control CPU, duplicating guide 56 also can receive " order " relevant with the data exchange by the CIU place and (COMMAND) reach " address " (ADDRESS) signal, these data can be from the place beyond the affiliated CPU, for example, the another one of two CPU shown in Fig. 1.

Just like filing June 7 nineteen eighty-three, serial number 511,616 together the application wait try a case in illustrated person, these two CPU work under the basis of shared main memory, simultaneously, both can be to identical block data work, CIU is provided when providing certain control method can make data transmit between CPU and main memory by certain sequence, the back also can be seen in more detail, duplicate guide 56 and also receive the address data of storing guide 60 by port, when duplicate guide received one by pipeline dynamic controller or the order that comes by CIU after, expression has caused certain control and address signal, is used for retrieving duplicating the interior record of guide to determine whether addressed block data is present in the affiliated high-speed cache.

So duplicate guide 56 produce " in " (HIT) or " not " (MISS) signal together be sent to as result for retrieval (search result) and with a command signal and duplicate guide dynamic control unit 54, these signals have been pointed out the source and the character of the required command signal of starting retrieval.This duplicates guide dynamic control unit 54, so use by (COMMAD) " order " of duplicating guide 56, and (SEARCH RESULT) " result for retrieval " signal, store (SEARCH RESULT) " result for retrieval " signal of guide 60 and the mutual relationship that some other signals such as (INTERFERENCE) " interference " by pipeline dynamic controller 52 reach (ALLOCATE SWAP REQUESTED) " transposition adjustment demand " signal by port, whether the data exchange shown in deciding is carried out smoothly, or problem has taken place.Owing to duplicate guide 56 mainly is under the certain way of CIU requires, the content of retrieval high-speed cache, duplicating guide dynamic control unit 54 will provide a set reaction signal to get back to CIU, and this reaction signal is one (REQUEST DONE) " request finishes ".On the other hand, when if data will be shifted out (swapped out) by affiliated high-speed cache, unit 54 meeting generations, one " transposition " (SWAP) signal gives CPU to start the formula of a transposition (swap), unit 54 also can be sent one and be denoted as the signal of (SWAP BUFFER ADDRESS) " transposition impact damper address " to CIU simultaneously, the one co-applications case of pending trial as described above is described in the numbering 511616.The usefulness of one displacement with impact damper (SWAP buffer) temporary transient storage of conduct when shift motion is arranged in the CIU.When a shift motion when carrying out, the dynamic control element 54 of autographic register can provide one (SWAP EXECUTING) " transposition is carried out " signal to be sent to the flowing water waterline and carry out dynamic controller 52.

Sometimes normal data exchange may need one section new data is deposited in the address that high-speed cache distributes, and former to have had the data of this address still be useful, because, put the data mode according to normal high-speed cache, unique effective one section backup data promptly is present in the high-speed cache, this section data is moved back into earlier in the main memory before must depositing in new data, and such demand need allow pipeline dynamic controller 52 locate to obtain an order from computing buffer memory (O-cache).And then produce one " transposition configuration needs " (ALLOCATE SWAP REQUIRED) signal by the pipeline dynamic controller and be sent to and duplicate guide dynamic control unit 54, duplicate then guide 56 will start a displacement formula data by CPU migration CIU pipeline dynamic controller 52 in program, use and produce one and end signal to high-speed cache, the action of displacement is done earlier, pipeline dynamic controller 52 and duplicate guide dynamic control unit 54 and can notify mutually each other and whether have interference to be found by the other side, these disturb can hinder shown in the correct execution of control.Same, CIU can duplicate guide dynamic control unit 54 to any data of its discovery or the error notification on the program, controller 54 must get off ongoing program interrupt then, received " mistake " (ERRORS) or " interference " (INTERFERENCE) indication of this class if duplicate guide dynamic control unit 54, unit 54 will be notified and duplicate guide 56 and heavily cover the order of carrying out retrieval (search).When retrieving again, the situation of interference should can be eliminated.

In the instruction pickup unit (I-fetch) 26 in Fig. 2, there is an instruction storehouse to have in it in advance by high-speed cache 20 and 22 instructions of taking out.Going out instruction by cache prefetch and putting between the time of instruction storehouse, CPU also instructs with these, and the data of demand may be changed the interference that causes in the CPU action, on the other hand, instruction by the high-speed cache taking-up, its used related data may be in the program of streamline, and all may there be when instructing the instruction of storehouse the Data Processing that computer system is made the mistake in any situation handling continuously these.

Take place for fear of this situation; instruction storehouse (I-stack) has a protected location 58; in instruction stack protection unit 58; each position of instruction storehouse (I-stack) all has a working storage (register) corresponding with it; the address that high-speed cache address that instruction pick-up (I-fetch) comes and the port that will be understood storage guide 60 are discussed is compared; whether can noisy situation exist with decision; it is invalid for this situation of problematic instruction the action of proposition to be become; after if such a disturbance regime is found; instruction stack protection unit 58 will transmit a removing (cancel) signal and pick up (I-fetch) device to instruction according to the character of disturbance regime, to eliminate the selected record of instruction pick-up.In other words; if high-speed cache has received that one " writing " (WRITE) order; be written to data in the address that high-speed cache sets, this address also can be sent to instruction storehouse (I-stack) protected location, and the content of good and instruction storehouse (I-stack) is compared.If " together " (HIT) this signal; instruction stack protection unit 58 can " the instruction storehouse is removed " (FLUSH I-stack) signal be sent to instruction pick up (I-fetch) device with eliminate (HIT) " in " all later instructions of this signal; this " the instruction storehouse is removed " (FLUSH I-STACK) signal also is sent to pipeline dynamic controller 52 and goes; send one by it again and suspend (HOLD) signal, temporarily quit work till the instruction storehouse is eliminated to the CUPS unit.

Port storage guide 60 will be described in a more detailed discussion below, mainly contain a working storage of depositing the address data in it, and this working storage is stored to be to handle in pipeline organization and the address of each data of still being untreated.This port storage guide 60 receives the address data of being come by high-speed cache and receives a command signal by streamline controller 52 places, under this command signal control, there is the address data in the suitable address in the port storage guide in port storage guide, shown in the concrete practice in, the working storage of port storage guide is made up of one 4 * 4 record array (array), that is to say that 4 layers of record (entry) are arranged, every layer has 4 groups.Shown in each record in the concrete practice form by one 40 (bit) long word, the address that has comprised one 16 actual storage in it, the address of one 11 high-speed cache and the high-speed cache identification code of 1 position (is the address of computing buffer memory O-cache or Instructions Cache (I-cache) with differentiation).The high-speed cache level signal of 2 bits (which kind of level the address of indication high-speed cache is), the transposition identifying signature of 2 bits is (when needs replace, point out to replace address in the impact damper) and 8 work banners (Flag), which kind of work with what point out to be required to combine with aforementioned address is, 16 temporary records should be able to be adjusted voluntarily with all working of finishing under the pipeline organization arrangement (scheduled) in the port storage guide.

Whenever CUPS element 24(Fig. 2 of streamline sent in the record of a running) time, address under it can be admitted to port storage guide 60, and point out by the order of pipeline dynamic controller 52 working storage of port storage guide 60 should be retrieved whether to have another still uncompleted action also to use same address in the decision pipeline organization.After having passed through such comparison, if there is no identical address in port storage guide, then the address of new record can be placed in the array of port storage guide.Opposite, if when the person refers to an address together in finding to have another record and discuss in port storage guide, then that signal can be brought judgement (HIT) " together ", to determine record that this is new and original compatible still mutual exclusion of record, if can not cause mutual exclusion, then new record will be regarded as one and be categorized as " not " record (MISS), opposite, if caused mutual exclusion, then have a controlling signal and be sent to CPU and provide necessary corrective action to get rid of mutual exclusion, the mutual exclusion meeting is admitted in the computer system wrong data.

Also remember to pick up the input end that address data that (I-fetch) device 26 obtains should be sent to instruction stack protection unit 58 by instruction.Same address data can be sent to the input end of port storage guide 60; this address will be compared with the high-speed cache address data that before deposited port storage guide 60 in; if in port storage guide, do not find identical address, this port storage guide can send as one " difference " of result for retrieval (search result) (MISS) signal to instructing stack protection unit 58 to go.If opposite, what find is identical address, then have one " together " (HIT) signal can support judgement and (HIT) whether can cause and conflict and in computer system, produce error result with decision signal " together ".If truly have conflict to exist; then there is one " result for retrieval " (Search RESULT) signal can be sent to instruction stack protection unit 58 pointing out this phenomenon, and sends " the instruction storehouse is removed " (FLUSH I-stack) signal by instruction stack protection unit 58 again.

Same, when signal was seen through certain structure and is replicated guide 56 and receives by CIU, expression had been sent an order and address here by CIU place, and whether this address can and exist some address that duplicate guide to compare, exist in the high-speed cache to determine this piece data.Subsequently, duplicating guide 56 send an address to go to port storage guide, to determine whether this address is identical with the present address that does not execute as yet in the pipeline organization, the result of this address comparison is sent to via port storage guide 60 and duplicates guide dynamic control unit 54.If do not have this address in the port storage guide, the result for retrieval of then sending can be one " difference " (MISS) signal, if the result is one " together " (HIT) signal, then available this " together " (HIT) signal judge whether subsequent processing can produce the useless result of conflict with decision.If like this, duplicate guide dynamic control unit 54 and can produce a suitably instruction, order is duplicated guide 56 and is sent request signals again after conflict disappears, or one " interference " (INTERFENCE) signal deliver to pipeline dynamic controller 52, optionally carry out corrective action to make CPU or CIU.

Another function of port storage guide 60 is when CPU is handling a selected data, CPU is moved relevant address and control data store.After CPU had finished Data Processing, the gatherer 48 that the result of processing can be deposited CPU went.When the data in the gatherer 48 will be sent back to cache stores, can store guide 60 to port and produce an order, produce the address of high-speed cache and select signal by storage guide 60 again, feasible data of being come by gatherer can be deposited in the high-speed cache.When the data of being come by gatherer was deposited high-speed cache, port storage guide 60 was also delivered to the address of data and is duplicated guide 56.Therefore the address record that duplicates the guide preservation can be identical with the high-speed cache of depositing data.When having one in the order of being sent to port storage guide 60 to " write into " of high-speed cache (WRITE) during signal; the address of high-speed cache also can be sent to instruction stack protection unit 58 and go; whether the data that instruction stack protection unit 58 is deposited it and its inside more relatively has an instruction and present " writing " (WRITE) to instruct and conflict mutually in the instruction storehouse with decision.If such conflict is arranged, then instruct the stack protection unit to produce some controlling signal, to carry out the corrective action of necessity to streamline dynamic controller and instruction pick-up.

Shown in the concrete practice in, data is that the mode with every section 8 words is sent to high-speed cache by main memory, the position of each address of high-speed cache (location) has 2 words or accounts in every section 8 words 2.Therefore, exist each address in the port storage guide 60 to be 2 words.The action of CPU in fact may not need be used whole double word, in fact may be less one or more hytes of a word in the double word.In multiple occasion, the including address and may send here from main memory or by the high-speed cache in another CPU of this 8 fields, the CPU characteristic in this computer system are that CPU needn't wait the data of whole section 8 words to move on to high-speed cache fully can to handle its existing data.

Because the step by the primary access data is quite slow, the data that CPU handled deposits high-speed cache in before might being deposited in high-speed cache in the data of main memory in advance.If like this, then deposited in old information lid that the data of the processing of high-speed cache will be come by main memory in the past by CPU, new data after making this handle is destroyed to be fallen, avoid this situation, zone controller 62 has been recorded one group of Region control signal to each notes in port storage guide 60, each address in port storage guide corresponds to the record of a double word of high-speed cache, and each type families is made up of 4 hytes (Byte) or zone.Therefore, will comprise 8 zones or hyte in each double word.The zone of each double word, with a position that exists in the zone controller, the position of complying with its place concerns to be represented.

As shown in Figure 3, this zone controller is received the order of the storage that CPU sends here, and expression CPU is instructed to will be to a certain the action that address deposits in of high-speed cache.Zone controller 62 is accepted by CPU gatherer 48 or is directly come the specific region signal by the DECCU unit 36 of CPU.The Region control signal is pointed out that zone of double word or hyte are kept by CPU and is used as Data Processing.These signals are formed one and are forbidden that (inhibit) signal funding material record uses from the zone of other source of information (source).After finishing the data exchange, zone controller can be received " order finishes " (COMMAND COMPLETE) signal from the CIU place and the record in its storehouse is washed off, this same signal can produce another " record reset " (ENTRY RESET) signal and be sent to port storage guide 60, the acting on being stored in banner (FLAG) relevant with a certain data logging in the port storage guide in to reset of this " record is reset " signal.

The calcspar of port storage guide system 60 is described by system shown in Figure 4 in more detailed mode.This port storage guide has comprised one group of memory array (array) 64.In the concrete practice that is exemplified, the arrangement of memory array has 4 levels to be respectively level 0 according to the design of Fig. 4, level 1, level 2 and level 3.Have 4 group records in each level, constitute the memory array component that 16 group records are arranged.At port storage guide memory array 64(port store directory memory array) in each notes record include the address (the inferior bit of actual address (least significant) partly) of a high-speed cache, the number of pages of a reality (status of a sovereign unit of actual address (Most significant) partly), a high-speed cache authentication code (high-speed cache is instruction buffer memory or computing buffer memory under differentiating), a high-speed cache level sign indicating number, a transposition (SWAP) impact damper address and several definition record purpose banners (Flag).Being regarded as input signal by the next address data of CPU is added in the input of selector switch (selector) 66 via (PRIMARY ADDRESS) input end that is denoted as " initial address " among Fig. 4, same, the address signal that is come by CIU is taken as that input signal is added on the end points that is denoted as " main storage system address " (MEMORY SYSTEM ADDRESS) and as the 2nd input of selector switch 66, and address signal herein is meant by main memory or the address signal sent here by the CPU to CPU.

Have in the array 64 one " writing " (WRITE) logic 68 be to be subjected to one to write/remove input controller 70(write/clear entry control unit) control.Writing/remove in the input signal of input controller 70 has one " storing marking " (STORE TAG) signal, and this signal is added to port storage guide and goes some as additional command signals." storing marking " signal is level (LEVEL) and the group (SET) that one 4 signal is used for distinguishing 54 li each notes records of array.Write/remove the access control signal that has in other input signals of recording controller 70 to come from affiliated CPU, these signals are denoted as " access control of high speed master cache " (PRIMARY CACHE ACCESS CONTROL).Element 70 also has an input signal that is denoted as " main storage system interface control " (MEMORY SYSTEM INTERFACE CONTROL), and the controlling signal of this signal representative by CIU is as the control data by main memory or the 2nd CPU.Writing/remove 70 pairs of arrays 64 of recording controller provides output signal with the selection of control as the source of information that is deposited in, this data is from high speed master cache (primary cache) or from main storage system, and the position of input and sequential then are from selector switch 66.

As previously mentioned, when work, can use pipeline dynamic controller (the internal work state of CPU under the expression), duplicate guide (the action situation that expression is come by CIU or main storage system), or instruction pick-up (its task is that the working routine that a new data is sent into CPU is gone to handle), address and other correlativity data be the reference port storage guide supplier of institute then, " read in " in the input signal of (READ) logic 71, the address signal of a part is from the instruction pick-up, initial address, main storage system address and " storing marking " signal, these signals can selectedly be added on the logic 71, with reading specific the electing property of address of memory array 64.The address of new data can and port storage guide 60 in the address read of memory arrays 64 be that unit is compared to organize (set), this address relatively be to carry out by an address Compare Logic device 72, in Fig. 5, have more careful explanation.

If the address of new data is not in array 64, then new data can and write/remove under the control of recording controller 70 and enter in the array via selector switch 66, if, opposite is, identical address is arranged in memory array 64, then Suo Shu banner can be used to judge whether the execution to determine original instruction can cause incorrect or conflict phenomenon, if do not have this incorrect and conflict generation, then program can continue to carry out and not be interrupted, if, opposite, the continuation execution of program can cause conflict or incorrect phenomenon, then have one " interruption " (BREAK) signal can be sent to suitable query device (interrogating unit).

Combination/starting access controller 74(combine/enable access control unit) can be by choosing suitable banner in the array 64, this element has detailed explanation in Fig. 6, " together " of address (HIT) or " difference " (MISS) signal be added to main storage system interrupt logic device (memory system break logic) 76 after can be selected, pipeline organization interrupt logic (pipeline break logic) 78, or instruction picks up the input end of interrupt logic (I-fetch break logic) 80, and interrupt logic is to do suitable selection by the action that retrieval is added to the input address signal of address Compare Logic device 72 and is added to the input controlling signal of combination/starting access controller 74.Be added on the corresponding elements by " interruption " or " not interrupting " (BREAK or NO-BREAK) signal of element 76,78 or 80 new demand is delayed, after any this conflict is excluded, begin again.

As previously mentioned, " storing marking " (STORE TAG) signal is confirmed the address of each record in the array 64, and is sent to the control of input end to carry out as to be that writes/remove recording controller 70.Through after the effective record controls, " storing marking " signal can be deposited " storing marking device " 82, as gatherer 48(Fig. 2) when Quasi gets the data that will handle from CPU ready and deposits back high-speed cache again, " storing marking " signal that corresponds to this data item can be taken out by storing marking reservoir (store tag storage) 82, and be added to " reading on (READ) input end 71 from array 64, to take out the address of data, be sent to high-speed cache and go of array 64.The address that array 64 each level come can be fed to selector switch (selector) 84." storing marking " signal also is sent to selector switch 84, the signal of choosing that level with decision can be sent to high-speed cache through the data write buffer (CACHE write information buffer) 86 of high-speed cache, and the data of gatherer can be deposited in the suitable address of high speed memory system.

Among Fig. 5 port storage guide array 64 and relevant address Compare Logic 72 thereof are had more detailed explanation.Have the Address of 4 levels in the shown array 64, be denoted as level 0 in the drawings, level 1, level 2 and level 3.Each level has 4 groups of data and is denoted as group 0 respectively, group 1, group 2 and group 3.Can see among the figure, each level is with 3 outlet selectors.For example, level 0 has the 1st selector switch 88, the 2nd selector switch 90 and the 3rd selector switch 92 attached it, 88,90 with the input of 92 each selector switch respectively with level 0 in 4 groups of independence data do other and be connected, the input control and the address signal of selector switch 88 and instruction pick-ups join, and selector switch 90 joins with " pipeline organization address " (pipeline ADDRESS) signal and controlled by it, and this signal is the corresponding signal under the CPU inner port storage guide.Selector switch 92 is to join with " main storage system address " (MEMORY SYSTEM ADDRESS) signal, and this signal is the address signal that CIU comes.

Same, the part of array 64 levels 1 also have 3 attached selector switchs respectively with level 0 under selector switch 88,90 is corresponding with 92, and be subjected to identical control, secondly, the level 2 and 3 of array 64 has 3 attached selector switchs respectively, and these selector switchs also are subjected to the control mode identical with 92 with selector switch 88,90.

Aforesaid 12 selector switchs have 12 comparator bank 94 corresponding with it respectively, and each selector switch all joins with the input end of its affiliated comparer.One of input end of the 1st comparer of the output of selector switch 88 and comparator bank 94 joins, but make the corresponding address signal of the output signal and instruction pick-up of being chosen relatively, if the address that the and instruction pick-up comes is identical, and this address is deposited in a certain group of array 64 levels 0 then, and the output of the 1st comparer of comparator bank 94 will produce (HIT) signal of " together ".

The several inputs system of selector switch 90 respectively organizes memory body from array 64 levels 0, and can react to some extent pipeline organization address signal, the output of selector switch 90 is sent to one of the input end of the 2nd comparer of comparator bank 94, and compare with the high-speed cache address signal that affiliated CPU comes, if high-speed cache address signal is identical with one group of address signal by selector switch 90, the 2nd comparer 94 will produce the signal of (HIT).The output of the 3rd selector switch 92 is sent to one of the input end of the 3rd comparer of comparer 94, and compare with " main storage system address " signal that comes by CIU, herein, also be the same, if the address signal that CIU comes is identical with the address signal of a group selector 92, then comparer can produce " together " signal (HIT).All can see the output of 3 comparers and institute's corresponding selection device to 1,2 and 3 each level and be compared, and each level also all there are affiliated " address is picked up in instruction " signal, " pipeline organization address " signal and " main memory address " signal.

As shown in Figure 5, with level 0,1,2,3 the outputs of the 1st comparer under out of the ordinary are sent to instruction shown in Figure 4 respectively and are picked up interrupt logic device 80 as its input signal, and are same, with level 0,1,2,3 the outputs of the 2nd comparer under out of the ordinary are delivered to pipeline organization interrupt logic device 78 shown in Figure 4 respectively as its input signal.Then, with level 0,1,2,3 the outputs of the 3rd comparer under out of the ordinary are delivered to main storage system interrupt logic device 76 shown in Figure 4 respectively as its input signal.Instruction pick-up address, the pipeline organization address, be sent to selector switch 88 with the main storage system address, 90,92 and comparer 94 as the input controlling signal, shown in the concrete practice in, it is that group address can be sent to comparer 94 that these address signals have 2 positions to be used in these several levels selecting, and the address of selected therewith again level of the other part of aforementioned address and group is at comparator bank 94 places relatively.

The front was carried, can be in Fig. 6 with more detailed angle explanation combination/starting access control logic 74, and shown array has 4 levels that store data equally, on figure, be marked as level 0 respectively, level 1, level 2 and level 3, each level have 4 groups of data again, it is denoted as group 0, group 1, group 2 and group 3, as shown in Figure 5, herein too, each level of array 64 all has the selector switch under in the of 3.The 1st selector switch 96 under each level of 4 levels has respectively, under each level one group of 4 groups of data as one of input signal of selector switch, the control that group is selected (I-fetch set select) signal is picked up in the instruction that selector switch 96 is added thereon, 4 selector switchs 98 of the 2nd group belong to each level of level 0-3 respectively, and added the control that thereon pipeline organization group is selected (pipeline set select) signal, 4 selector switchs 100 of the 3rd group belong to each level of level 0-3 respectively, and added the control that thereon main storage system is selected signal (Memory system select), 12 selector switchs 96,98, with each input of 100, all identical to each level, in this way, 96, each selector switch of 98,100 forms banner data (Flag information) with 4 groups of data of affiliated level as input signal.The output of 4 selector switchs 96 is received instruction and is picked up interrupt logic device 80(and see Fig. 4) locate, the banner data can be sent over, pipeline organization interrupt logic device 78 places are received in the output of 4 selector switchs 98, banner can be sent over, and main storage system logic device 76 places are received in the output of 4 selector switchs 100, and banner can be sent over.

As shown in Figure 4, it is that output banner by address comparative structure shown in Figure 5 and structure shown in Figure 6 is produced that several output signals are arranged, these signals are at the interrupt logic circuit 76 of Fig. 4,78, combination in 80, in fact whether can cause conflict phenomenon in the CPU action with decision by address " together " signal (HIT) of Fig. 5 output, if meeting, port storage guide can send a correspondence " interruption " (BREAK) signal go to the suitable unit of CPU or CIU, to produce necessary interruption conflict phenomenon can be eliminated.It should be noted that, if in address Compare Logic 72, produce address " together " signal result (HIT), if be not set and have corresponding banner in output place of Fig. 6 circuit, then the address in the array 64 will be an invalid address, and can obtain one " difference " signal result (MISS), this is because after the purpose of the address data being sent into port storage guide array is finished, and can reset relevant banner, in fact, that is this part of array 64 dispose.

In the operation, when the instruction that relates to affiliated or the addressing of CPU self high-speed cache is arranged whenever, containing the high-speed cache address of addressed data and real page number can be sent to array 64 and store away, the front was carried, write down the recognition signal that the data of being deposited should contain high-speed cache in addition 64 li a certain of array, draw (lead) number before the high-speed cache, transposition buffering address, banner with a plurality of setting input functions or purpose, in the concrete practice shown in the present, the banner that 8 units are arranged, Yian row's position are selected the mode of work or are looked for the working method of data.The some of address data is used for explanation in level shown in the array, is that group address is addressed to.

When instruction can be used for handling by CPU, then related data address will be written in the suitable address of array 64.This address can be retained in the there always, up to shown in work or till several work are done.

When new instruction comes, the address meeting of the related data that is come by CPU or CIU and the address that is present in the array 64 are compared, if identical address is arranged, then have the processing that is subjected to CPU in the structure of showing that data that one " together " signal result (HIT) points out to relate to this new instruction has been present in streamline in array 64.This one " together " (HIT) signal be sent to suitable one and interrupt signal element (BREAK signal unit) 76,78 or 80, handle the address banner data that has memory body by these elements, if when having new instruction to be performed, whether can produce conflict with decision.For example, some instruction may be read the data of just being revised by CPU in the high-speed cache, and then the result of back one instruction has a condition and makes it invalid.Some DATA PROCESSING does not have problem when carrying out, but picture other processing more recited above can deposit wrong or invalid data in the high-speed cache at last, and certainly, this can make the also data of output error of computer.If interrupt logic (BREAK Logic) circuit finds to have this conflict to exist, then the interrupt logic element can produce one " interruption " (BREAK) signal go to the suitable unit in the computer system, to interrupt the execution of disturbed instruction, and after conflict is eliminated, re-execute this instruction, to finish this DATA PROCESSING in the pipeline organization.

If the interrupt logic element does not find have conflict to take place, then can allow to carry out new processing, exist in the array after suitable banner can be set simultaneously.

Opposite, if the result of the address comparison of depositing is " different " signal (MISS) in the address of new instruction and the array, then with can deposit in the array 64 than the relevant address of new instruction and control data shown in address in, and be stored in wherein till the work of institute's directive command is done always.CPU handle data during this period of time in, the several working storages relevant with processing are not adjusted with the address of the high-speed cache that stores last data, therefore, after Data Processing is intact, the result of data can place in the gatherer and Quasi deposits into high-speed cache fully, at this moment, " storing marking " signal of element 82 can be to array 64 read in steering logic 71 addressing in addition, to read the address of a high-speed cache, well the data of gatherer is deposited in the high-speed cache, the high-speed cache address of this taking-up is sent to high-speed cache, makes that the data of gatherer can be deposited in this address.

Therefore, according to the present invention, (store-into-cache) form power supply brain system that deposits in that can propose a cover high-speed cache uses, the used CPU of this computer system is the formula work according to streamline, the method system of its control data flow process sees through the program of streamline in order to avoid throw into question when the system handles data, and the funding material is handled the address that in good time keeps high-speed cache when using.

Claims (16)

1, in the computer system that central processing unit (central processor unit) and main memory are arranged, aforesaid central processing unit inside has one to save as the high-speed cache of groundwork, simultaneously, in such system, aforesaid central processing unit is with the form of streamline (pipeline) and the control method work of some control data flow processs, avoiding in the design of streamline taking place the afoul result of instruction, being characterized as of said method:

The method that memory body stores data, but the position that a plurality of addressing are arranged in the memory array, in being set the position of address, aforementioned array can store data, these data are and existing relevant address and the function banner of each instruction in aforementioned pipeline organization, the method that compares the address data, the address data system relevant with each new instruction is present in the aforementioned array, this method can detect the situation of using identical data in preceding several remain unchanged executory instruction and aforementioned new instructions, under the situation of address unanimity, can produce one " together " (HIT) signal, the method of arbitration functions banner data, this data corresponds to the address that same condition takes place in the aforementioned array, carry out aforesaid new instruction with decision and whether can cause conflict, aforesaid determination methods comprises that still one produces " interruption " (BREAK) method of signal, make when clashing, can provide indication aforesaid computer system.

2, in the control method of the computer system described in the claim 1, said memory array has 16 positions that can set address can supply memory up to 16.

3, in the control method of the described computer system of claim 1, said memory array has the position that can set address, and the address of its setting is relevant with selected data, and this data is to be stored in the aforementioned address data in the memory body.

4, in the control method of the described computer system of claim 1, a method that can receive aforementioned address data is arranged, this address data is relevant with aforesaid new instruction, all from central processing unit or aforesaid main storage system.

5, in the control method of the described computer system of claim 4, aforesaid array has several layers, and every layer can have many group records.

6, in the control method of the described computer system of claim 5, aforesaid array has 4 layers, and every layer can have 4 group records, aforesaid each layer and aforesaid each all independently addressing of group.

7, in the control method of the described computer system of claim 6, one outlet selector method is arranged in the aforesaid comparative approach, selector switch in this method combines with aforementioned each layer respectively, to finish an in check selection, chooses the address data relevant with each group record.

8, in the control method of the described computer system of claim 7, aforesaid relative method also has relatively a method, and the connected mode of the comparer in this method makes it can be relatively by output address data of selecting in the aforementioned array and the address data by aforementioned new instruction.

9, in the control method of the described computer system of claim 8, in the outlet selector method relevant with aforementioned each layer, array selector is arranged, and each element of aforementioned array selector is all received different addressing sources respectively, makes selector switch work according to its addressing signal of sending here.

10, in the control method of the described computer system of claim 9, in aforesaid central processing unit, also has an instruction pick-up, and the address signal that has a selector switch and aforementioned instruction pick-up to send here in aforesaid several selector switchs joins, the address data of the pipeline organization that the 2nd selector switch and aforementioned high-speed cache come is joined, the 3rd selector switch then joins with the address data that aforementioned main storage system is come, so that suitable reaction to be provided.

11, in the control method of the described computer system of claim 10, in aforesaid determining method, also have an outlet selector method to join with aforesaid each layer respectively, to finish an in check selection, choose function banner data.

12, in the control method of the described computer system of claim 11, respectively with the aforementioned outlet selector method of aforementioned each layer associated in the 1st selector switch, join with the function banner controlling signal of aforementioned instruction pick-up, the function banner controlling signal that the 2nd selector switch and aforementioned high-speed cache come is joined, the function banner that the 3rd selector switch and aforementioned main storage system are come is joined, so that suitable reaction to be provided.

13, in the control method of the described computer system of claim 12, aforesaid determining method also has one to interrupt the signal logical method, the aforementioned selected function banner data of this logical and and " together " (HIT) signal join and the reaction of generation necessity.

14, in the control method of the described computer system of claim 13, the 1st in the aforementioned interruption signal control method interrupts the signal logic element, with (HIT) signal and the aforementioned function banner document signal of having selected join by aforementioned " together " of aforementioned instruction pick-up, the 2nd interrupt signal logic element and aforementioned " together " of coming by high-speed cache (HIT) signal and the aforementioned function banner document signal of having selected join, and the 3rd interrupt the signal logic element and (HIT) signal and aforementioned functional banner document signal join by main storage system next aforementioned " together ".So that suitable reaction to be provided.

15, in the control method of the described computer system of claim 1, qualitative by a method institute that adds, this method is controlled by a controlling signal of being come by aforementioned central processing unit, data after this controlling signal is pointed out to be handled by aforementioned central processing unit Quasi is got ready and can be deposited in the aforesaid high-speed cache, the selection of address is by selecting in the address data that is stored in aforementioned array under the data, and this method is delivered to aforesaid high-speed cache to selected address and gone so that aforesaid data is deposited in the address of aforementioned appointment.

16, in the computer system that central processing unit and main storage system are arranged, have one in the aforesaid central processing unit to save as the high-speed cache of groundwork, simultaneously, in such system, aforesaid central processing unit is with the form of streamline and the control method work of some control data flow processs, avoiding in the design of streamline taking place the afoul result of instruction, preceding method in respect of:

Just each instruction in aforementioned pipeline organization, its relevant address and function banner data deposit in the selectable position of memory array; Address data under each new instruction and the address data that is stored in the aforementioned array are compared, all use the situation of same data with several instructions before detecting and aforesaid new instruction, when if consistent address is arranged, promptly produce one " together " signal, judge again by aforementioned " together " (HIT) the function banner data confirmed of signal carry out aforementioned instruction with decision and whether can produce conflict, promptly produce one " interruptions " signal and give aforesaid computer system if having conflict as indication usefulness.

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