CN85105145A - Provide quadrature-related two resolutes vector and the device of mould value - Google Patents

Abstract

Apparatus of the present invention, be used for calculating two quadratures, one correlated components signal (I and Q) vector and amplitude and the hardware quantity that uses is minimum.It is the logarithm value at the end to produce respectively with B that the amplitude of orthogonal signal adds to ROM50 as address code.In device 60,62, the greater of logarithm value subtracted each other and obtain two absolute values the value difference value | D|.Difference D is used as the ROM64 that address code is added to sequencing, producing a corrected value F,

Wherein: F=0.5Log (1+B-2|D|)

This value F supply with 66 make its with two logarithm value in the greater addition, addition and inverse logarithm by 70 calculating, thereby determined two orthogonal signal I and Q vector and amplitude C.

Description

Provide quadrature-related two resolutes vector and the device of mould value

The present invention relates to be used to calculate two quadrature correlated components signals vector and the Circuits System of amplitude, purpose of the present invention especially is to reduce the demand of circuit and still finishes required calculating.The present invention has general applicability, but especially is applicable to digital television receiver, in this digital television receiver, wishes to handle with minimum hardware combine digital vision signal.

In many electronic systems, must determine orthogonal signal vector and amplitude.For example, in digital television receiver,, can carry out AUTO FLESH easily by the phase place and the amplitude of control chrominance vector.This carrier chrominance signal, normally with IQ colour mixture signal or (R-Y) and (B-Y) form of the represented orthogonal signal of colour difference signal occur.Therefore, want to carry out the control of requirement, just must partly determine the amplitude of chrominance vector according to quadrature component.

As everyone knows, with quadrature component squared magnitude sum sqrt again, just can determine the amplitude of resultant vector, the mlultiplying circuit that utilization is asked square amplitude, with the adding circuit of square value addition and to the evolution circuit of the quadratic sum sqrt of addition, also can realize asking the purpose of resultant vector amplitude.In addition, by the amplitude of resolute is supplied with the ROM (read-only memory) of sequencing as address code, with produce corresponding to the vector of supplied address code and the output valve of amplitude, also can realize this function.

The people that are engaged in work in the signal processing technology field very clearly understand, and each method in the said method all requires a large amount of processing hardware, and required hardware quantity is that ultralinear ground increases along with the increase of signal bits.In addition, when broadband signal was handled in real time, necessary component can not obtain at an easy rate.These factors especially become restricted defective in digital television receiver.Because in digital television receiver, requiring quantity with circuit component to maintain minimum value and these elements is that form with VLSI (very large scale integrated circuit) (VLSI) realizes.

According to the present invention, vector and the amplitude (for example, I and Q) of amplitude calculating circuit conversion quadrature-coherent signal be the logarithm sampling value Log of B at the bottom of becoming logarithm _B| I| and Log _B| Q|.With these two logarithm sampling value Log _B| I| and Log _B| thereby Q| subtracts each other and obtains a difference D=Log _B| I|-Log _B| Q|.This difference is used to calculated correction value, and this corrected value equals 0.5Log _B(1+B ^-20).With corrected value and corresponding Log _B| the addition of I| value, and, just obtained quadrature-relevant resolute I and the vector of Q and amplitude of C with its sum logarithm of negating.

According to further embodiment of the present invention, the vector of being touched upon and amplitude calculating circuit the amplitude of orthogonal signal I and Q is converted into B is the logarithm sampling value Log at the end _B| I| and Log _B| Q|.With Log _B| I| and Log _B| the Q| sampling value is subtracted each other, and just obtains the absolute value of difference:

｜D｜＝｜Log _B｜I｜-Log _B｜Q｜｜

This absolute difference | D| is used for calculating a corrected value, and this corrected value equals 0.5Log _B(1+B ^-20D1).Log _B| I| and Log _B| among the Q| bigger logarithm value and associated corrected value mutually adduction determine itself and opposition numerical value so that obtain vector and the amplitude of C.

In the accompanying drawings:

Fig. 1 is a block diagram, and it shows the Circuits System of the typical prior art that is used for carrying out AUTO FLESH in digital television receiver.

Fig. 2 is a Circuits System block diagram, and it has shown and is used to produce the vector of orthogonal vector of the present invention and the Circuits System embodiment of amplitude.

Fig. 3 is that the part of Fig. 2 Circuits System is launched block diagram.

Circuits System 20 illustrations of Fig. 1 one and in digital television receiver, carry out the AUTO FLESH circuit arrangement.AUTO FLESH circuit 20 is arranged in the colour signal processing section of receiver and quadrature～correlated color resolute I and the Q that separates the carrier chrominance signal C that the back obtains from composite video signal is handled.Suppose that carrier chrominance signal sends out (continued on next page) with colour subcarrier quadruple rate (as 3.58MHZ) and give birth to and phase modulation is carried out in sampling and make it corresponding to I and Q axle, the result with certain produce in proper order the amplitude of the I and the Q of a string :+In ,+Qn ,-In ,-Qn ,+In _{+ 1},+Qn _{+ 1},-In _{+ 1},-Qn _{+ 1}Or the like, the n here, n+1 or the like, the period of expression sampling carrier chrominance signal C.Be noted that "+" and "-" signal indication sampling phase, rather than the polarity of representative sample.And then we suppose that sampling value is digital form (for example, being 8 bit parallel PCM signals).Be that base of a fruit green grass or young crops (DChin) serves as the disclosed instructions of topic with " a kind of auto tone circuit that is used for television receiver " in 501,896 the U.S. Patent application in series number, can find detailed description sort circuit with reference to its content.In U.S. Patent Application Serial 4,402, (HGLewis serves as to inscribe to have touched upon to be used for producing the schematic circuit of suitable I of a string and Q amplitude with " clock generator that is used for the DCTV Digital Color Television signal receiver " Jr) to 005 medium and small HG Lai Weishi.

Speak briefly, circuit 20 shown in Figure 1 is phasing degree whenever chrominance vector of following operation when being in the particular range of the value relevant with the colour of skin, by with respect to I resolute rotation chrominance vector C, carries out AUTO FLESH.Yet chrominance vector C is represented with the form that is actually quadrature colour mixture signal phasor I and Q or by quadrature colour difference signal (R-Y) with (B-Y) by its component.In order to narrate, the present invention will use I and Q component signal to set forth.A rotation of circuit 20 outputs carrier chrominance signal, this signal is actually by represented corresponding to quadrature colour mixture signal I ' and the Q ' of the chrominance vector C ' that rotates.

A series of samplings of I and Q are added to terminal 22, from then on are sent to magnitude demodulator device 24 and angle wave detector 26 again.According to the present invention, magnitude demodulator device 22 will produce the amplitude of vector and the C of orthogonal component signal I and Q, for example:

$\mathrm{C\; =}\sqrt{I{}^2\mathrm{+\; Q}{}^2}$

And on bus 28, produce this signal.Angle wave detector 26 produces a signal on bus 30, the angle Q of this signal representative is corresponding to the angle between chrominance vector C and I sampling axle.Angle signal Q is added to ROM32 and 34 as address code, and they produce and be added to the sine and the cosine value of the corresponding argument of address code of their input ends respectively.For the angle Q within the angular range that does not belong to the colour of skin, ROM programmed is added the sine and the cosine of angle value with output institute, and for the angle Q that belongs in the angular range relevant with the colour of skin, the ROM generation is corresponding to the sine and the cosine of the angle of Q+ △ Q.△ Q wherein represents the rotation angle that requires and is that of Q goes out number.

Sinusoidal and cosine value is added to multiplier 36 and 38 respectively, and in multiplier 36 and 38, they are taken advantage of by amplitude C, thereby have produced the flesh correction resolute respectively on bus 40 and 42

I '=CCosQ and Q '=CSinQ

From following theoretical derivation, we can more clearly understand the course of work of instantaneous amplitude wave detector 24:

$\mathrm{C\; =}\sqrt{I{}^2\mathrm{+\; Q}{}^2}$

Log _BC＝Log _B $\sqrt{I{}^2\mathrm{+\; Q}{}^2}$

＝0.5Log _B（I ²+Q ²）

＝0.5Log _B（I ²·（l+（Q ²/I ²）））

＝0.5（Log _B（I ²）+Log _B（l+（Q ²/I ²）））

＝0.5×2Log _B｜I｜+0.5Log _B（l+B ^-2(Log _B ^｜I｜-Log _B ^｜Q｜）

＝Log _B｜I｜+0.5Log _B（l+B ^-2(Log _B ^｜I｜-Log _B ^｜Q｜）

＝Log _BI+F（Log _B｜I｜-Log _B｜Q｜）

＝X+F（X-Y），

Here, for narration optimum implementation of the present invention, represent two logarithm value Log respectively with X and Y _B| I| and Log _B| the higher value of Q| and smaller value

Log _BC＝X+F（｜D｜）

Here | D|=X-Y or represent two logarithm value Log _B(I) absolute value of difference and (Q).

So, C=Log ^-1 _B(X+F(|D|))

According to following equation:

C＝Log ^-1 _B〔X+F（｜D｜）〕

Magnitude demodulator device 24 has been determined the vector of orthogonal component signal I and Q and the amplitude of C.

For this purpose, the burst of being made up of the I and the Q amplitude at terminal 22 places is added to assembly 50, has so just determined to be the logarithm value Log|I| and the Log at the end with B _B| Q|.Assembly 50 can be a ROM, and it has I and the Q amplitude input port as the address code input.Can will program so that provide relevant logarithm value with the corresponding respectively storage unit of address code at the output port place of ROM50.Owing to used the ROM of definite logarithm value, so needn't calculate in real time.

In order to obtain high precision, the significance bit by utilizing digital logarithm is to greatest extent selected the end B of logarithm.Especially for the system that is prepared for handling corresponding to the И-position logarithm value of M-position sample of signal (comprising sign bit), B equals at the bottom of the logarithm:

Ln ^-1〔 (Ln2 ^{M - 1}- 1)/(2 ⁿ- 1) 〕

Here, Ln represents natural logarithm.

Log _B| I| and Log _B| the Q| value is temporarily deposited in latch 52 and 54 respectively in response to corresponding I and Q clock signal.Log _B| I| and Log _B| Q| latch 52 and 54 output are delivered to plurality selector switch 56 respectively and are produced the Log that exists at present in latch 52 and 54 than decimal selector switch 58 at their output terminals separately _B| I| and Log _B| the higher value of Q| value and smaller value.

In Fig. 3, will be to narrating greatly and than the course of work of decimal detecting device 56 and 58.Log _B| I| and Log _B| the Q| signal be added to respectively subtracter 100+Ve and-the Ve input end, and the sign bit of the difference that subtracter is produced is tested.The if symbol position is " O ", then means difference:

（Log _B｜I｜-Log _B｜Q｜）

For+Ve, and Log _BBe two logarithm value Log _B| I| and Log _B| bigger one among the Q|.On the other hand, the if symbol position is " 1 ", and Log then is described _B| I| is one less in two logarithm value.The input port of traffic pilot 102 is added with Log respectively _B| I| and Log _B| Q| signal, the big input value (being X) in its two inputs of output port response sign bit generation.Similar to X, traffic pilot 104 is in response to the less input value (be Y) of sign bit in its two inputs of output port generation.

Two input Log _B| I| and Log _B| the polarity of the smaller value Y of Q| is asked negation by 2 the complementary circuit 60 that is coupled to than decimal selector switch 58 output.Circuit 60 comprises that one is used for all are imported the phase inverter that negation is asked in the position; Least significant bit (LSB) unit at the number of asking negation adds " 1 " totalizer with 2 the complement code that produces the input number.

Summing circuit 62 is with two input Log _B| I| and Log _B| 2 the complement code of the smaller value Y of Q| and corresponding higher value X addition, so that produce two input Log _B| I| and Log _B| the difference between the Q| | the absolute value of D|.Difference | the absolute value of D| is added to assembly 64, and it produces a value at output terminal:

F（｜D｜＝0.5Log _B（1+B ^-2D））

Assembly 64 can be a ROM, two input Log _B| I| and Log _B| the absolute value of difference between the Q| | D| adds to this assembly as address code, and this ROM is programmed so that it equals F(|D| one of output terminal output) value.

By Delay Element 68 higher value being postponed a reasonable time at interval, is to arrive summing circuit simultaneously with corresponding correction value really to make higher value basically, and then, summing circuit 66 is with the output F(|D| of assembly 64) and two input Log _B| I| and Log _B| the higher value X addition of Q|.Assembly 70 produces the inverse logarithm Log of the output valve of summing circuit 66 ^-1 _BThereby obtain being substantially equal to the numerical value of amplitude C of the vector of orthogonal signal I and Q.

By means of an example, will the application of the magnitude demodulator device of being touched upon be described.

If 7-position chroma sampling comprises sign bit (being M=7) and И-position logarithm (that is И=7).

B=1.033161, the end B for logarithm has used the equation that provides above.

F（｜D｜＝0.5Log _B（1+B ^-2｜D｜）

＝0.5Log _B（1+1.033161 ^-2｜D｜）

Calculate:

If I=8, Q=24

Log _B｜I｜＝64，Log _B｜Q｜＝97

X=97(is Log _B| I| and Log _B| the higher value of Q|)

Y=64(is Log _B| I| and Log _B| the smaller value of Q|)

D＝X-Y

＝97-64

＝33

F(|D|)=2, (from the F-table, detect)

LogB $\sqrt{I{}^2\mathrm{+\; Q}{}^2}$ ＝X+F（｜D｜）

＝97+2

＝99

$\mathrm{C\; =}\sqrt{I{}^2\mathrm{+\; Q}{}^2}$

＝Log ^-199 _B

=25.27(estimated value)

≈ 25.3(actual value)

Be noted that by the figure place (being И) of increase sample of signal or the figure place (being M) of logarithm value, can obtain the value of finding the solution of degree of precision.In this example, along with each F(D) increase, the quantitative value of value D reduces.In addition, by reducing each F(D) increment of value changes the bigger number with the codomain that obtains D, can improve the precision of the value of finding the solution.

What also will note is, for the difference D of 7-position sampling representative, according to the F-table, has only required 7 corrected value F(D) (promptly 1～11).Therefore, by suitable decoding, the scale of ROM can be reduced greatly described ROM address enter code word.

The present invention does not need mlultiplying circuit and has only a little accuracy table, therefore and above-mentioned other technologies compare, hardware cost is lower and what obtain is the more high-precision value of finding the solution.

Claims (13)

1, be used to produce the relevant resolute of pair of orthogonal vector and the device of amplitude, it is levied and is:

Be used to receive the device 22 of described pair of orthogonal one relevant resolute amplitude;

Be used for to described vector produce associated a pair of be the device 50 of the logarithm value at the end with B;

Be used for described two logarithm value are subtracted each other device 56～62 to obtain a difference D;

Be used for producing and equal 0.5LogB (1+B ^-2D) the device 64 of corrected value;

Be used for device 66 with described corrected value and described another logarithm value addition; And

Be used to produce the inverse logarithm of described adding device output valve so that obtain the device 70 of a C value, this C value in fact just equal described quadrature one relevant resolute vector and amplitude.

2, according to claim 1 described device, it is characterized in that:

Be used for determining the device of 2 complement code of a described logarithm value, and,

Be used for the device that complement code and described another logarithm value with a described logarithm value 2 are obtained described difference D.

3, according to claim 1 described device, it is characterized in that:

Described corrected value generation device is to be made of-ROM, and a difference D is added to this ROM as address code, and this ROM by sequencing so that in corresponding storage unit, holding relevant F(D) value.

4, according to claim 1 described device, it is characterized in that:

Described difference forms device and comprises the device that is used to calculate the absolute value D of difference between two logarithm value; Described corrected value generation device, it produces one and equals 0.5Log _B(1+B ^-2|D|) corrected value F(D); And be used for device with the greater addition of described corrected value and described logarithm value.

5, according to claim 4 described devices, it is characterized in that:

The described absolute value that is used to calculate two logarithm value differences | the device of D| comprises the device that deducts the smaller of described logarithm value from the greater of described logarithm value.

6, according to claim 4 described devices, it is characterized in that:

The device of described calculating logarithm value difference comprises:

The device that is used for the bigger and less value of definite described logarithm value, and

Be used for deducting another device of the person of reducing from the greater of described logarithm value.

7, according to claim 6 described devices, it is characterized in that:

Described substracting unit is made up of following array apparatus:

Be used for determining the device of 2 complement code of described less logarithm value; And

Be used for 2 complement code of described less logarithm value and described big logarithm value are obtained mutually the device of absolute value of the difference of two logarithm value.

8, according to claim 7 described devices, it is characterized in that:

Described 2 complement code determines that device comprises:

Be used for the position of described less logarithm value is asked the device of negation;

Be used for the least significant bit (LSB) unit of asking the negation value to described less logarithm value and add " 1 " to produce the device of described 2 complement code.

9, according to claim 6 described devices, it is characterized in that:

The described big logarithm value of determining the device output terminal in described bigger and less logarithm value is added to described adding device.

10, according to claim 9 described devices, it is characterized in that:

The described bigger logarithm value of determining the output of device in described bigger and less logarithm value is added to described adding device by a Delay Element, thereby really makes described adding device receive described big logarithm value simultaneously with relevant corrected value basically.

11, according to claim 1 or 4 described devices, it is characterized in that:

Described logarithm value generation device is made of a ROM, and the amplitude of described a pair of vector adds to this ROM as address code, and this ROM by sequencing so that in each storage unit, comprise relevant numerical value.

12, according to claim 4 described devices, it is characterized in that:

Described corrected value generation device is made of a ROM, an absolute difference | D| adds to this ROM as address code, and this ROM by sequencing so that in corresponding storage unit, comprising relevant corrected value F(|D|).

13, according to claim 1 or 4 described devices, it is characterized in that:

Described inverse logarithm generation device comprises a ROM, and the output of described adding device is supplied with this ROM as address code.And this ROM by sequencing so that in each storage unit, comprise relevant opposition numerical value.

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