CN85101348A - The central processing unit of multiple data channel (CPU) structure - Google Patents

Abstract

Various functional units are comprised that the central processing unit of computing machine organizes together the special functional unit that makes main arithmetical unit and comprise a coprocessor can the visit data register, and can be from cache memory access literature constant and data.Make the closely coupling of functional unit and main data channel by a versabus, allow the CPU sequencer to shift according to multiple situation simultaneously, these situations can be differentiated by detection line.The parity checking that functional unit sends is than a late clock period of result, so the parity checking passage can not influence the cycle of machine.This structure allow to select some not the microcode of usefulness check whether the CPU operation correct, promptly when the double bus mistake than the time can stop the operation of CPU.

Description

The central processing unit of multiple data channel (CPU) structure

The invention relates to the central processing unit (CPU) in the data handling system.Or rather, the invention relates to the tissue of various functional units, also can make main arithmetical unit (ALU) and various special function unit visit data register, access literal constant and data from cache memory comprising central processing unit (CPU).

In data handling system, central processing unit is the part that system carries out data processing, logic, arithmetical operation and other data conversion.Among the CPU physics of each parts be connected with logic, be among the CPU physics of arithmetical unit and various registers and traffic pilot to be connected with logic be to be called data channel.

The CPU of most of prior arts has a forms data channel architecture, and promptly this structure makes the data stream of passing through CPU only through a passage.

The design of the CPU of some prior art has the multiple data channel.These CPU have adopted a lot of multiport registers.Yet such layout need be with big traffic pilot.For example, in a CPU that 30 registers are arranged, each traffic pilot all need be equipped with the input ports that width is 30 row, could be to all register services.

In addition, the CPU of prior art can be can not be pipeline organization also, just will be divided into two-stage or multistage in time, carries out a micro-order by data channel like this and will divide several steps to carry out.Pipeline organization makes by the data throughout of CPU to be accelerated, and this is owing to allow some part of different continual commands to carry out simultaneously.Such as, when carrying out the back segment of article one instruction, also can carry out the leading portion of second instruction.

Data channel with regard to the above-mentioned prior art of employing known to the inventor is adequate to general task, yet every kind of mode is all just like next or a plurality of shortcomings.The common characteristics of CPU of the register of employing multiport and the multiple data channel of traffic pilot are owing to used the bigger traffic pilot of width just to need relative a large amount of parts.In addition, the use of this traffic pilot is to the restricted effect cycle length of CPU, because traffic pilot is wide more usually, its corresponding gating time just must be long more.

The CPU of non-pipeline structure can not reach the instruction throughput of pipeline organization usually in the prior art.

Using another characteristics of the multiple data channel CPU of wide traffic pilot in the prior art is to have the dirigibility that can carry out access simultaneously to plural data register content.Yet this dirigibility is a kind of advantage of falseness, is the result of last operation because the result of statistics shows the most common operation number.

Therefore, although available data channel scheme is arranged in the prior art, see also with the viewpoint of price ratio from performance and performance to leave some room for improvement.

In most of prior art system, CPU does not partly check, otherwise just need add the expensive hardware that is used to check in addition.And then the CPU of prior art is generally and finishes micrometastasis, needs more connection between detection logic and various functional unit.

Therefore, the purpose of this invention is to provide the datapath structure of CPU, this kind structure can overcome the shortcoming of one or more prior art datapath structures.

Another object of the present invention provides one and has the cpu data channel architecture of multiple data channel.

Further aim of the present invention provides the CPU structure of a multiple data channel, and this structure can reduce the port of register and reduce and use wide traffic pilot.

Another object of the present invention provides the CPU structure of a multiple data channel, and this structure allows CPU to carry out more than one operation in each instruction cycle.

For those the people that general technology is arranged aspect the present technique, as long as the claim of checking this instructions and accompanying drawing and enclosing just can be understood these purposes of the present invention and advantage is clearly.

Announced a kind of CPU of multiple data channel, data source wherein, as the multiregister file, high-speed buffer register, the literature literal register, ALU output and special function output register have constituted two groups of operand bus, supply with ALU for one group, another group is supplied with the special function unit group, and the function of this group unit is controlled by microcode.

Each operator trunk is from traffic pilot, and this traffic pilot has compiled possible Data Source, comprises the register of preserving last ALU and special functional part operation result.

Prior art multiple data channel structure uses one or more big traffic pilots data source to be carried out the multipath conversion of single-stage usually, and the present invention is to use two level production lines, wherein the first order is finished the decoding of registers group and other register traffic pilot, and secondary series is to main traffic pilot addressing and control ALU and the function of special function unit.The control of specific function comprises from N special function unit selects one and define its function.

Specific function is to arrange in the mode of tight coupling, and an assisting data channel and one group of N special function unit are wherein arranged, and multinomial function can be carried out in each unit, and joins with main ALU data channel.In fact can realize any specific function, as, as auxiliary ALU; Access scratch-pad register group; Barrel shifter; In multicomputer system, pass through bus and other processor interface of interprocessor; With the main memory interface; Carry out and interrupt; Read/write access to reloadable control storage; Interval timer; I/O channel interface etc.

Owing to have many data channel, just might realize inspection to various cpu subsystems.This inspection is transparent to system user.In some operation, can select some not usefulness microcode so that when two buses lose than the time, stop CPU and turn round.

Fig. 1 is the block diagram of CPU of the present invention.

Fig. 2 is a block diagram of realizing the auxiliary ALU of specific function.

Fig. 3 is a block diagram of realizing the scratch-pad register array of special function unit.

Fig. 4 is the hardware block diagram of the parity checking generator of specific function.

Fig. 5 is the block diagram that the special functional module condition is checked hardware.

The structured flowchart of whole data channel has been described in Fig. 1.In this preferable embodiment, Unit two are arranged as source resource.ALU10 and special function unit 12a, 12b, 12c ... 12n is supplied with by available data resource.The output of ALU10 enters main junction 14, and the output of 12 special function units is to enter special main bus 16.(output of a unit promptly once can only be arranged)

The source of these two data sources is that two groups of buses promptly are respectively main bus J and K, 18 and 20, and be the source with 4: 1 traffic pilots 22 and 24 respectively, private bus is respectively SJ and SK, and 26 and 28, be the source with 4: 1 traffic pilots 30 and 32 respectively.The selection of traffic pilot realizes that by the microcode field this is readily appreciated that the people that those have the general technology level in the field.In this preferable embodiment, 4: 1 traffic pilots have been used, those people that present technique is familiar with will easily observe, and it can provide one to have the system that more input connects, and dirigibility not necessarily can increase but this will increase the complicacy of hardware.

Each traffic pilot can not obtain the several data source simultaneously.4: 1 traffic pilots 22 and 30 of supplying with J bus 18 and SJ bus 26 data have several Data Sources; Be J register 34, CD register 36, M register 38 and SM register 40.4: 1 traffic pilots 24 and 32 of supplying with K bus 20 and SK bus 28 data are with M register 38, and SM register 40, K register 42 and LIT register 44 are the source.Note because can be public to the data source register M38 and the SM40 of M and SM data channel, data channel and being enriched, be data source register M38 and SM40 any one side by ALU10, stride across J bus 18 and K bus 20 via J register 34 and K register 42, also can be by special functional module 12a to any one any one side of 12n, via SJ4: 1 traffic pilot 30 and SK4: 1 traffic pilot 32 and SJ bus 26 and SK bus 28.

Introducing the various registers that use in the preferable embodiment of the present invention and the function of bus in this respect will be good.Though those people that have the general technology level in this area are easy to observe these regulations to a certain degree arbitrariness is arranged, and function and the various layout that also can specify other for various buses and register within the spirit and scope of the present invention, and other priority.

M register 38 is deposited the result of former former head ALU, via M bus 14 output of ALU10 is sent to its input.SM register 40 is deposited is the result of original any special functional module of selecting in from 12a to 12n.

J register 34 and K register 42 are being deposited separately by a content of selecting in a plurality of registers, mainly are the contents of selecting from registers group 46.Registers group can be packed into from M register 38.The people who is familiar with this art can recognize that J and K register also can extract data from other register, such as extracting data by traffic pilot from programmable counter or memory address register.

CD register 36 is being deposited the output content of addressable cache 48, this cache is from being sent into by line 49 by SM register 40, last main register is a LIT register 44 in these registers, this register such as its name indication the literature constant that provides by microcode field 50 is provided.

Registers group 46 is controlled by several microcode fields, its explanation: a certain register, be any one, and send to J register 34 and K register 42; From M register 38 is input to some registers that registers group.Indicator storage (not shown) and microcode come together to select the register that will write and read.This register can or can be made it or increased or subtract from M bus 14 input by the microcode section.The field of these registers of packing into that are useful on is the second level in micro-order, be useful on the field of reading in the first order.

As above-mentioned, the operation of data channel is preferably finished by a streamline that has at least the secondary microcode to form among Fig. 1, is narrated as relevant pending application book, and this application book sequence number is 537,038 applying date was, on September 29 nineteen eighty-three, another sequence number is 537,429, the applying date is with previous, these two applications transfer same assignee, and obviously, this is in conjunction with in the present invention.

In the preferable embodiment of the present invention, article one, the first order microcode bit field of the micro-order addressing function that translates microcode comes strobe register group 46, traffic pilot 52 is selected from a plurality of registers in the input that is put into J register 34, to 42 inputs of K register, traffic pilot 54 has above-mentioned identity function.Traffic pilot 52 and 54 has formed the passage that leads to the register of access seldom, as programmable counter, and memory address register, or status register.Those people that have the general technology level in this field will appreciate that and are characterized in allowing more multiregister access not harming to make under the master register passage situation.

The second level microcode bit field of micro-order is to 4: 1 traffic pilots 22,24,30 and 32 decodings and control and definite ALU10 and the 12a operation to the special functional unit of 12n.About special functional unit, to the selection of n the special function unit of 12n, and definite its function people of having a general technology level in this area will recognize that any bit position in the microcode field of use all can use to the part of second level microcode bit field in order to control 12a.Except CD register 36 is that all registers all are to be energized simultaneously when could encouraging when cache memory is peeked.The microcode field can send inhibit signal ((not shown) to CD register 36.Some register (M, SM, CD and multiregister file) can be under an embargo in micrometastasis selectively.See pending application, sequence number 537,886.

Layout in this data channel of preceding narration is preferable enforcement of the present invention, from reducing the viewpoint of cost and raising performance, dirigibility to a certain degree is provided, this give the hardware complex situations and multi-functional between conciliation is provided, this is clearly to those have the general technology level in this field people.

Each special function unit all can be used for carrying out one group of relevant work in from 12a to 12n.Such as, can be that auxiliary ALU is used for the logical OR arithmetical operation and sends the result back to the SM bus.

Fig. 2 is the embodiment of special function unit as ALU.ALU unit 100 has the input 102 that is connected to SJ bus 26 and is connected to the input 104 of SK bus 28, and also there is its oneself output 106 ALU unit 100, is connected to impact damper 108.Impact damper 108 is sent the result of ALU back to SM bus 16.Owing to there is the special function unit more than two to be connected on the SM bus, impact damper 108 has way to prevent bus conflict, could control the SM16 bus guarantee when a special function unit is selected by having only.Like this, impact damper 108 has OE(to allow output) input end, this is driven by decoding unit 110.Field 112 in the second level of microcode drives decoding unit 110 and all special function units that are connected to SM bus 16 is driven similar decoding unit.Each decoding unit under certain condition, only recognize in the present microcode field 112 all possible microcode in conjunction with in one.Like this, having only a decoding unit can start an impact damper receives special function unit on the SM16.

Second microcode field 114 is connected with ALU unit 100 in the second level of microcode.The operation that this microcode Field Definition is undertaken by ALU unit 100.

Be in operation, any special element always is connected in SJ and SK bus as ALU unit 100, and so always its function gets ready in order to finish.Whenever can only there be a function can control the SM bus.This selection be by microcode field 112 decision and by code translator 110 decodings, and make impact damper 108 drive SM buses 16.

ALU100 might produce ALU=0(and 116 represent with numeral) output, this can be used for carrying out certain detection.As previously mentioned, can be chosen in the original instruction no microcode and produce operation by CPU, as shown in FIG. 1, its result just is placed on SJ and the SK bus.If it is designs like this that these microcodes detect subroutines, the result's hypothesis that promptly appears at simultaneously on SJ and the SK bus equates, whether the final step that can be used as in this detections of the output 116 of ALU100 is determined by the hardware effort of this microcode inspection correct so.The result of this point in program can be used to stop processor except ALU=0, this is to lose ratio because SJ26 and SK28 have produced.The method whether this just provides the various piece of a kind of CPU of checking normally to move, these parts do not have other test mode (as parity checking), do not need to increase a large amount of circuit yet.Check with the normal system running and carry out simultaneously, do not influence performance.Do not need to use the special functional module of 12a such as simple ADD macro instruction to 12n.

The operand of two additions is sent to ALU10 on J bus 18 and K bus 20.Owing to the dirigibility of data channel, same operand can be sent to specific function ALU100 simultaneously in addition.During next one clock, the result of main ALU and special ALU just can send in M register 38 and the SM register 40.Then, these results can be transported to the input 102 and 104 of specific function ALU by traffic pilot 30 and 32.Microinstruction field 114 are carried out audit function, promptly allow ALU100 carry out a subtraction, if online 116 indicated results are not zero, so just stop CPU.Like this, just verified the correct running of ALU and many control channels.

What the example of another special function unit had been implemented in CPU of the present invention is multi-address scratch-pad storage.Scratch-pad storage 120 can be made of RAM and other suitable storer or register device, and as shown, respectively with SJ26, SK28 is connected with the SM16 bus.The SJ bus is used as the data input port of scratch-pad storage 120, and the SK bus is employed a part of address as to middle result memory 120 accesses the time.Another part address of scratch-pad storage 120 derives from microcode field 114.

As in the example of ALU, decoding unit 122 inspection microcode fields 112 have been chosen the intermediate result storage 120 that can arrive SM bus 16 to determine whether specific bit patterns.Yet not resembling decoding unit 110 decoding unit 122 with ALU100 has two outputs.One of them is a line 124, only provides on the permission output terminal that an information is attempted by scratch-pad storage 120.This allows the output terminal of input is the output that is used for forbidding scratch-pad storage 120.Like this, just can be connected with SM bus 16 selectively.Second output line 126 be used for driving the read-write input of scratch-pad storage 120, and whether definite scratch-pad storage will carry out read or write.

Generally, can find out from the example of top that microinstruction field 112 normally are used for selecting special function unit, and its output is delivered on the SM bus 16.Microcode field 114 is owing to carry out special addressing function or determine its function for special function unit.

Parity checking normally transmits with data delivery, and 12a wants a late clock cycle to the special function unit transmission parity checking of 12n.Otherwise if the data serial that 12a exports to special function unit generation parity checking and the special function unit of 12n, then the generation of parity checking will be slowed down the cycle length of machine.

Prevent slowing down of cycle length, 12a sends parity information to the special function unit of 12n than the late clock of data message.The time of parity checking generation does not influence time minimum period of CPU like this.

In Fig. 4, describe special function unit and produced the mechanism of parity checking.

Fig. 4 has illustrated the special function unit of 12a to 12n, its input and SJ bus 26, and SK bus 28 is connected, and its output is connected with SM bus 16.Except that these buses, Fig. 4 has illustrated that SJ parity checking bus 26a and SK parity checking bus 28a drive the input of specific function module and SM parity checking bus 16a, and it is driven to the 12n special function unit selectively by 12a.As directed all special function units of special function unit 12a the same (comprising) have by or produce the operating unit 200 of parity elements 202 and specific function, such as they ALU100 among Fig. 2, or scratch-pad storage 120 among Fig. 3.The parity checking of a unit be by or produce the character depend on special functional unit.Such as, if special function unit is a scratch-pad storage, parity checking is just along with the data that will store in the scratch-pad storage are passed through together.If specific function operation 200 is ALU, parity checking will produce according to the result of ALU.

Other situation comprises a counting operation as special function unit, if input state and input parity checking are known, which type of parity checking can adopt a kind of algorithm to come this function of prediction result is.As on record in the present technique, there are many hardware design can be according to input operand and the operation prediction that is carried out parity checking.Parity checking by or generation unit 202 also can adopt the mode of these parity checking predictions.

By parity checking by or parity check bit first efficient clock pulse after it produces of producing of generation unit 202 place it in the SM parity checking bus delay register 204 when arriving.

Now can notice microcode field 112, it is to be used for the specific special function unit of gating 12a in the 12n as discussed earlier, and it is to be used for driving decoding unit 206 in the drawings.Decoding unit 206 is similar with 122 with the decoding unit 110 among Fig. 3 to Fig. 2 on function, yet it also will handle the another kind of function relevant with parity checking here.The part of the output of decoding unit 206 is to carry out the function of SM bus output via impact damper 208, and it is as a kind of on record prohibiting function in the drawings.The output of decoding unit 206 also drives delay time register 210 to the SM parity checking data input is provided.The permission of SM parity checking driving delay time register 210 driving output buffers 212/forbid that impact damper 212 is sent to SM parity checking bus 16a with the result of SM parity checking bus delay register.

Those have the people of general technology level to will be appreciated that the result of the specific function operation in square frame 200 arrives SM bus 16 by impact damper 208 in this field, therefore by register 204 and 210 clock delays, carry the previous clock period so arrive SM parity checking bus 16a than parity bit.Yet, drive parity check 216 for compensating this parity checking bus 16a.The output of SM register 214 is sent to parity check device 216 as the parity check bit of not deposited of coming from SM parity checking bus 16a.Because the parity check bit on SM bus parity bus 16a has been delayed a clock period, the SM register 214 that is added to the parity data bus makes the clock period of data output delay on the SM bus 16, and data and parity check bit just can be accepted simultaneously in parity check unit 216 like this.

The notion of parity checking is understood in announcement of the present invention in general, and promptly each word has a check bit, and those have the horizontal people of general technology can find out the method that also can adopt other in this field.Such as, the different field of the topped whole word of available a plurality of parity check bit.With two parity check bit, half of each topped word (person top, bottom).

Fig. 5 shows the block diagram of the condition inspection hardware capabilities of specific function module, and its hardware configuration allows the CPU sequencer to shift according to different testing conditions.

The 12a that is arranged in that narrated as the front is the unit of various specific functions to each special functional module unit of 12n, and they can carry out various detections to the parameter of its action need.Such as, if special function unit is ALU, the various detections that can carry out can comprise the setting of carry digit, ALU=0, the ALU result of plus or minus.

All be equipped with two traffic pilots 130 and 132 in each special function unit 12, via microcode field 114 parts, be respectively it and select from many available testing conditions, 114 microcode fields were discussed in Fig. 2,3,4.In this field, have the people of general technology level will recognize that to select two special tests have to a certain degree arbitrarily, and can therefrom select the more or less detection of number, can change the number (as 130 and 132) of traffic pilot like this. Traffic pilot 130 and 132 output drive two buses via impact damper 138 and 140 respectively, i.e. STESTA bus 134 and STESTB bus 136.Similar to the form of describing in Fig. 4 at Fig. 2, when not driving STESTA line 134 or STESTB line 136 yet, the SM bus just the output of impact damper 138 and 140 is forbidden neither driving when 12 special function units and its relevant portion.The impact damper 138 and 140 the input of forbidding are driven by decoding scheme 110, and decoding scheme 110 be that microcode bit field 112 is deciphered.When referring to these special function units in front, this had discussed.

Like this, when having selected a special function unit and microcode field 114 parts have also been determined one or one group of detection, the result of these tests by traffic pilot 130 and 132 and impact damper 138 and 140 be placed on STESTA line 134 and the STESTB line 136.

The terminal of STESTA line 134 and STESTB line 136 is sequencing conditional transfer hardware cells 139.The function of sequencing transfer hardware cell 139 is to use the testing result that is provided by STESTA and STESTB bus to carry out micrometastasis and forbids some microcode line selectively when producing some micrometastasis.The 26S Proteasome Structure and Function of sequencing conditional transfer hardware cell 139 is in the pending application case, and sequence number is: 537,886, and same assignee is given in full disclosure in the applying date 1983,9,29 as the present invention, and obviously, this is in conjunction with in the present invention.

Here the specific highway width that illustrates is to consider specific use and definite.What the inventor adopted is the two bit parity check positions that add of 16 bit wides, and the actual bus width that uses among the present invention is a kind of selection of design.

The number of various registers and use are not to show to be confined to these examples just as an example.Those have the people of general technology level to understand in the art, if follow the inherent rule of designing technique, the present invention can adopt TTL, ECL, CMOS, MOS, NMOS or other technology also can obtain this function.

Register, traffic pilot, ALU can realize with the part of logic element that separates or gate array or general LSI with special function logic.

Claims (1)

1, the structure that is used for the streamline CPU of data handling system comprises:

The arithmetic logical operation device that is used for first data channel carries out arithmetical logic to operand and handles;

In second data channel, be used to handle a plurality of devices of selecting specific function of operand;

A plurality of first register settings are used to store operand to be processed.

A plurality of first multipath conversion apparatuses are used for picking out an aforesaid operations number from above-mentioned first register setting.

A plurality of second register settings are to connect the above-mentioned first multipath conversion apparatus, are used to deposit the above-mentioned operand of selecting;

A plurality of second multipath conversion apparatuses are for doing further to select in the above-mentioned operand of selecting and the result of its selection being put on the first and second above-mentioned passages;

Bus unit is to be used for the result of above-mentioned arithmetical logic and above-mentioned special functional device is sent back to the first and second above-mentioned register settings.

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