CN85101313A - Central processing unit (CPU) micro jump structure that strengthens - Google Patents

Abstract

The hardware of carrying out the microcode transfer in a kind of central processing unit can carry out microcode with two kinds of friction speeds to be shifted, and the dirigibility that has the additional row that is prohibited from entering streamline selectively in transfer.Can use a tentative transfering channel for the testing result that does not reach as yet, and during clock suspension, if testing result is wrong, this exploratory passage can lead to correct diverting the aim.A return stack is arranged, its pack into and descend to push away be separated to adapt to two kinds of speed of transfer.Microcode can be encased in the return address storehouse with literal or the numerical value of depositing, and allows to carry out the transfer of vectorization and return in nominated bank after a delay is called.

Description

Central processing unit (CPU) micro jump structure that strengthens

What the present invention relates to is the central processing unit of various data handling systems.What more particularly, the present invention relates to is the micrometastasis of used each micro-order group in the central processing unit of data handling system and the hardware of carrying out micrometastasis.

The notion of micrometastasis, i.e. the transfer of the microcode level scope of micro-order in the central processing unit of data handling system, it is well-known that this notion formerly has in the technical field.People know in the central processing unit of data handling system, can carry out micrometastasis according to the result that selected testing conditions is selected down.In using the data handling system of pipeline organization, realize that micrometastasis can carry out according to the result who detects, and these testing results are to obtain in the process of the microcode field of different stage in carrying out micro-order.In some prior art, the ability that " soon " shifted is only done by system, and the testing result that promptly shifts institute's basis is to read during first order microcode field in carrying out given micro-order.Other system then only has the ability of doing " slowly " transfer, promptly is according to the result who carries out the testing conditions that second level microcode produces in the micro-order.In prior art, also have after capable a transfer of microcode as the system that can carry out micrometastasis, forbid that other microcodes are advanced into the function of streamline.The essential condition of forbidding the capable execution of back microcode depends on whether function that this microcode is performed and it is consistent with this transfer, and this shifts then is to be realized according to the result of this microcode testing conditions by CPU.

These not only for the designer of system provides dirigibility, and may design a kind of like this system as the micro jump structure scheme of prior art, and it can make more judgement, thereby can work on the higher level of separating.However, the design of system hardware with and the course of work still can make improvements.

For example, can not only can carry out fast transfer but also can carry out the system that slow-speed moves, just flexible not as two kinds of all executable systems of transfer.Such system generally can not carry out more than one detection in the time of any specific, even can not carry out more than one detection when carrying out any one micro-order.In such system, fast micrometastasis only can be done by some system, and slow micrometastasis only can be done by some system.The condition that the system that can only do fast micrometastasis is produced in the time of can not carrying out the second level according to existing micro-order is finished transfer.The obvious cause that causes this shortcoming is that the decision condition that shifts is carried out in request, is to take place on the time cycle of evening after transfering part detects.

On the other hand, only can carry out then necessary many clock period of grade of system that slow-speed moves,, before the microcode that execution diverts the aim, just lose a clock period like this so that obtain the jump condition that second level micro-code instruction produces.

Another shortcoming of carrying out the prior art that slow microcode shifts is: system lacks the dirigibility of forbidding selectively that before making branching decision the delegation of adding or two row microcodes are advanced into streamline.Equally, the prior art system that those can finish quick micrometastasis then lacks the dirigibility that the delegation or two that forbade existing row or descending microcode before making branching decision selectively is advanced into streamline.

Further, if a prior art system is after making the judgement of micrometastasis according to the testing conditions that has obtained, can also allow to carry out additional number row microcode, so this system general equal can not call a subroutine and then turn back to arbitrary other microcode capable on, and only can get back to produce the microcode that shifts that microcode after capable capable on.

Another shortcoming of present employed micrometastasis parts is: for carrying out fast and the hardware used of micrometastasis at a slow speed, generally all verifications mutually are unless use the verification parts that add in the prior art.

It no matter carry out the system of any micrometastasis, generally will adopt a return address storehouse again.System is that processor is pointed out a return address with this storehouse as a vector, shifts the microcode continuation operation of carrying out before the generation so that make.The present inventor recognizes the structure of return address in prior art, all has common characteristic, and the return address of promptly packing into is not to separate from storehouse with the method for rotation.This just causes the increase with the central processing unit hardware costs of reducing of dirigibility.

Therefore, one object of the present invention is exactly can make the central processing unit that slow-speed moves again a kind of structure is provided for doing fast transfer.

Another object of the present invention provides a kind of micro jump structure, and this structure can be carried out more than one detection when carrying out arbitrary micro-order.

Another purpose of the present invention provides a kind of micro jump structure; This structure can forbid when microcode shifts at a slow speed that arbitrary row or two of additional row is advanced into streamline doing.

A further object of the present invention provides a kind of micro jump structure; This structure can forbid when doing quick micrometastasis that the capable arbitrary row or two of existing or descending microcode is advanced into streamline.

Of the present inventionly advance a purpose and provide a kind of micro jump structure; The additional row of this structure in both can execution pipeline can be called a subroutine again, and when subroutine is returned, and still can carry out in the control store microcode of row arbitrarily.

Another object of the present invention provides a kind of micro jump structure; This structure can be carried out quick and two kinds of microcodes transfers at a slow speed, and the function that mutual verification is carried out in operations quick and two kinds of microcode transfer hardware at a slow speed is arranged.

An also purpose of the present invention provides a return address storehouse used when carrying out micrometastasis, and packing into of its return address can be separated from the rotation of storehouse.

For all these purposes of the present invention, as long as study instructions of the present invention, accompanying drawing and claim Hui Ming Liao just have the people of general technology level in this area.

Disclosed in this invention is for carrying out the employed a kind of structure of micrometastasis in a CPU.This structure can be carried out the next line microcode in control store selectively, or carry out delegation by the pointed microcode of certain vector, and this vector has produced positive testing result and has occurred when carrying out the first order microcode of existing micro-order, and this vector also can occur according to the execution result of the second level microcode of existing micro-order.When two testing conditions all are met, and the detection of being finished when carrying out first order microcode and carrying out second level microcode is all justify, and the pointed transfer address of result of then carrying out second level microcode will have precedence over another address and chosen.

If chosen a certain micrometastasis, then can all be forbidden or be forbidden wherein arbitrary in the instruction that has also entered streamline that causes micrometastasis, or all be not under an embargo those.

In addition, a hardware logic extra block can make system work on, and supposes that promptly result of determination is not do micrometastasis, but continues the streamline of packing into; If but this hypothesis is incorrect, system's correctable error, and in the time after a while, another vector is set on the address of this micrometastasis.During this address is removed and packs into, suspend circuit other clock with halt system.

When judgement is a microcode when calling, just the return address is placed on the storehouse of return address.This return address not necessarily is exactly that address of hanging up when producing micrometastasis, also may be the arbitrary address in the control store.The return address storehouse of packing into is to separate from the rotation of storehouse.

Fig. 1 is the block diagram of a double speed micrometastasis hardware in the preferable embodiment of the present invention.

Fig. 2 is after micrometastasis takes place, the block diagram and the logical diagram of the hardware operation that can arbitrarily forbid operating in the streamline.

Fig. 3 after the false supposition of execution micrometastasis is made, draws the hardware logic diagram that is back to correct address again, comprising the hardware that is used to suspend each system clock when drawing back into row.

Fig. 4 is the preferable embodiment block diagram of the return address storehouse of design according to the present invention.

Fig. 5 carries out the hardware block diagram that micrometastasis is judged, this judgement can be selected from several testing conditions.

Micrometastasis is the function that a kind of machine is carried out microcode.This function refers to can forbid carrying out descending microcode, and goes to carry out another series of instructions, and the address of this instruction is according to the resultant vectorial appointment of certain testing conditions.To seem particularly useful during central processing unit hardware logotype described in the present invention and the pending application application, and specify positive pending application application here, its sequence number is 537886; 537429; With 537038, the applying date is September 29 nineteen eighty-three.

Micro-order generally reads from control store, just it can be taken out as long as desired microinstruction address is placed on the control store address bus.At first referring to Fig. 1, in the present invention, the address that microcode is capable is to be presented on the control store bus 10, and the width of this bus can be decided as required, but will adapt with the number of address bit in the system.Control store bus 10 is by 4: 1 traffic pilots (4: 1MUX) 12 drive of control store address bus.Traffic pilot 12 is selected from three kinds of data sources: through line 16 from control store address register (CSAD) 14; Through connecting 20 from quick micrometastasis register (FAST) 18; With through line 24 from obtaining data the micrometastasis register (SLOW) 22 at a slow speed.

When carrying out continuous microinstruction operation, promptly when micrometastasis did not take place, control store bus 10 was returned feedback through line 26, and added 1 in increment circuits 28, and sent back in the control store address register 14 after the next clock of this system.Like this when operate as normal, in the address register 14 of control store, and join through line 16 and traffic pilot 12.

But when requiring micrometastasis, traffic pilot 12 is just from quick micrometastasis register 18 or select a vector address at a slow speed the micrometastasis register 22.This selection is according to satisfy detecting (SMET) trigger 30 slowly and satisfy the state that detects (FMET) trigger 32 and come surely soon, and these two kinds of triggers drive the selection input port A and the B of traffic pilot 12 respectively through line 34 and 36.As shown in Figure 1, control store address register 14, quick micrometastasis register 18, the micrometastasis register 22 at a slow speed, and SMET trigger 30 and FMET trigger 32 all are that the clock by this system is driven through line 38.

SMET trigger 30 and FMET trigger 32 all are that the result by one of multinomial testing conditions 40 is driven, and these testing conditions are added on the slow detection selector switch 44 through multichannel line 42, drive SMET trigger 30 by the slow detection selector switch through line 46 again, also be added in addition on the fast detecting selector switch 48, drive FMET trigger 32 by the fast detecting selector switch through line 50 again.The related content of this respect will be given further explanation in conjunction with Fig. 5.Slow detection selector switch 44 and fast detecting selector switch 48 are selected each testing conditions 40 from multichannel line 42 all according to the content of giving the microcode field of finishing earlier.Slow detection selector switch 44 uses the partial microcode field of this microcode, selects the condition that it will be done from each testing conditions 40.Microcode field in 48 uses of fast detecting selector switch first order microcode is selected the testing conditions that it will be carried out from each testing conditions 40.

Use the hardware of this particular requirement, can according at a slow speed or the result of fast detecting make supposition, i.e. the detection of being done when carrying out first order microcode field, or supposition is made in the detection of being done during the microcode field of the second level.Like this, the preliminary judgement of micrometastasis just can be made before the actual result that obtains detecting.Though this hardware capability has been accelerated the operation of system significantly, it is wrong that this supposition is likely, if made the supposition of a mistake, the clock of this system then can suspend, and simultaneously a correct vector is added on the control store address bus 10.This function is finished by suspending logical block 56.Suspend logical block 56 and be connected to slow detection selector switch 44 through line 58; Or be connected on the fast detecting selector switch 48 by line 60, can infer that like this judgement of being done gives final decision.An additional signal that is added on the line 62 has been forbidden the clock of each selected register, until having produced correct vector.Suspend the operation of logical block 56 and will give further explanation in conjunction with Fig. 3.

Be used for quick micrometastasis register 18 and at a slow speed the vector of micrometastasis register 22 select to finish by traffic pilot.Specifically, traffic pilot (MUX) 64 added a vector for quick micrometastasis register 18 through line 66, and micrometastasis register 22 has added a vector and traffic pilot (MUX) 68 gives at a slow speed through line 70.Traffic pilot 64 and 68 has several information sources.Traffic pilot 64 and 68 can obtain a vector through line 74 from return address storehouse (RAS) 72.Traffic pilot 64 can also obtain a vector from certain part of first order microcode field, this is to obtain through the output terminal of line 78 from row control store (HCS) 76.This shows that certain part that is added to vector on the quick micrometastasis register 18 and is by first order microcode provides, another part of this grade microcode has then provided the testing conditions that may cause this vector selected.

Traffic pilot 68 can obtain a vector from a second level microcode part from the output terminal of second level register (R2REG) 80 through line 82.Like this, the part of second level microcode field can provide the vector that this system shifts, and this transfer is according to a certain specific testing result, and this testing result is that another part by this second level microcode provides.

Carrying out at a slow speed transfer instruction and diverting the aim between the departure date, will have two row microcodes may enter streamline, using hardware of the present invention, can decision making and forbid entering or forbidding wherein delegation of these two row microcodes, or two row are not all being forbidden.Equally,, also can make a determination and forbid the operation of existing code line, perhaps play the operation of line code, or both not forbid all carrying out a certain quick microcode when shifting.The hardware of being responsible for finishing this function is non-operation instruction generator (NoP GEN) 84, and it can produce NoP1 and two kinds of signals of NoP2 respectively through line 86 and 88.The judgement that NoP generator 84 is made is according to satisfying detection triggers 30 slowly and satisfying the output condition of detection triggers 32 soon, and through line 90 from a bit field of the second level microcode of second level register (R2REG) 80 with through the bit field of line 94 from the third level microcode of third level register (R3REG) 92.

Determining which vector will be selected by traffic pilot 64 and 68, is to control by the field of the first order and second level microcode respectively.

As shown in Figure 1, the time clock on line 38, with the quick micrometastasis register 18 or the content of micrometastasis register 22 at a slow speed, or the content in the control store address register 14 is delivered on the control store bus 10 by traffic pilot 12.The content of control store address bus 10 will be recorded in the first-level address register (RIADR) 96 along with next time clock obviously.The used time clock of content of depositing the control store that is taken out by this signal is with last identical.Like this, engrave when given arbitrary, the content of RIADR96 also is a vector, shifts return address after carrying out in order to demarcate microcode.

The content of RIADR96 arrives the return address through traffic pilot (MUX) 98 and pushes away stack (RAS) 72.Because the input of this return address storehouse 72 is through traffic pilot 98, therefore with regard to have one be placed on R1 address register 96 originally in different vector insert in this return address storehouse.Shown traffic pilot 98 also has another input end, is from SK bus 100, and this SK bus 100 is shown in Fig. 1 of pending application application, and its sequence number is 537877, and the applying date is September 29 nineteen eighty-three.

One of method that realizes enhancing micrometastasis ability of the present invention is to use someway, according to the micro-order that will carry out, makes the microcode vectorization.For this purpose, the access traffic pilot 68 of micrometastasis register 22 data at a slow speed also can provide data by going into oral thermometer, and this table can be deposited a vector to the micro-order of carrying out possibly.Therefore, transfer ability of the present invention has the ability that makes the microcode vectorization according to this instruction.

Transfer instruction enter streamline and make want branching decision during in, will have code and enter streamline.The preferable embodiment of hardware of the present invention can forbid selectively that these codes enter streamline.Because these streamlines are not always to require to forbid, be code so its selection can be compiled with the form of microcode.

Now referring to Fig. 2, this is for forbidding the used hardware block diagram of each line code selectively, and has given explanation to this structure of forbidding.Two bit fields in carry out shifting microcode, promptly before inoperation bit field (ENoP) 102 and back inoperation bit field (LNoP) 104, all can selectedly be used for forbidding each row microcode.If one shift fast, ENoP field 102 can be forbidden the second level microcode operation of existing row; If one is shifted at a slow speed, ENoP102 then forbids the second level operation of next line code.If a quick micrometastasis, the LNoP field can be forbidden the next line microcode in streamline, and if one is shifted at a slow speed, the LNoP field then can be forbidden the second level operation that more the previous stage microcode is capable in streamline.

102 and 104 microcode positions are with other microcode field, according to clock period successively, by second level register (R2REG) 80 and third level register (R3REG) 92.When these two microcodes were in the second level in the streamline, they were with satisfying detection triggers (FMETF/F) 32 soon, decided which microcode is capable need be forbidden.When these two microcodes were positioned at the third level of streamline, they were just with satisfying detection triggers (SMET F/F) 30 slowly, decided which microcode is capable need be forbidden.

In the preferable embodiment shown in Fig. 2, since the hardware that makes a determination based on door, if so clearly satisfy detection triggers 32 soon and satisfy all not set of detection triggers 30 (promptly not keeping logical one) slowly, not shifting selected, so all microcode provisional capital can not be under an embargo.If but any one or two in these two triggers have been set, forbid that so the capable judgement of microcode works with the ENoP 102 and LNoP 104 parts of this microcode fully.If this two bit code all is not a logical one, do not have then that microcode is capable will be forbidden.If but in this two row delegation or two row are arranged all are logical ones, forbid that the ruuning situation of parts is as follows.

The situation of doing quick transfer is to suppose to satisfy soon detection triggers 32 set.Like this 106 and 108 two with door one of input end on one " 1 " will appear.If LNoP position 104 set then one " 1 " occurs with the output terminal of door 106, this is the signal that the next line microcode is forbidden in expression.If ENoP position 102 set, then one " 1 " appears in the output terminal with door 108, and this is the signal that will forbid that existing microcode is capable.Regardless of the state of SMET trigger 30, will cause with the appearance of a logical one of door 106 output terminals or a logical one appears in door 110 output terminals, NoP1 signal 112 also becomes logical one like this.NoP1 signal 112 is to be used for forbidding the operation carried out according to a certain result that first order microcode is selected.Or the output of door 110 will be delivered to the D end input end of trigger 114.Trigger 114 through a clock cycle delay after, with or the door 110 output terminals logical one deliver to or the door 116 input ends, again to NoP2 input end 118.NoP2 input end 118 is all second level operations that are used for forbidding microcode.

When a logical one had appearred in output terminal that satisfy detection triggers 30 slowly, this logical one just was sent to and door 120 and 122.One " 1 " that 102 places, ENoP position in third level register occur will make and door 122 work.With the output of door 122 is to forbid the signal of bar micro-order down, and it will be sent to 118 and produce NoP2's or door 116 places.Be set if be arranged in the LNoP position 104 of third level register, it will by with door 120 or door 110 output terminal insert one " 1 ", to keep 112 NoP1 output.This position " 1 " is loaded into the output terminal of trigger 114 and warp or door 116 to NoP2 after a time clock.

In the preferable embodiment of the present invention, can do supposition earlier for the testing result that does not draw as yet; Result according to these suppositions can make the micrometastasis judgement.Since be to infer, it but is wrong situation that the final discovery of the supposition of making is arranged unavoidably.Hardware of the present invention is placed on correct value respectively in SMET trigger 30 and the FMET trigger 32 by the time-out logical block 56 among Fig. 1, it places correct address on the control store address bus by 4: 1 traffic pilots 12 again, and the correct value of NoP1 and NoP2 is placed line 86 and 88.

Referring to Fig. 3, existing described be to be used in reference to parts to correct address at interval.

Be speculated as example with the mistake that may make, quote a high-speed buffer that is used to deposit instruction or data.In arbitrary high-speed buffer,, can produce a signal and point out high-speed buffer " not normal " if desired data or code do not occur.

The hardware of high-speed buffer and high-speed buffer " not normal " is being well-known in the art, also not within the scope of the invention simultaneously.Disclose purpose of the present invention for reaching, can suppose that the not normal signal of high-speed buffer is a logical one that appears on the line 200.This logical one have only when the microcode field is pointed out to infer just by with door 202.In order to point out that this supposition is used at a slow speed or this microcode field of immediate mode, be deciphered the signal that comes across respectively on line 204 and 206 to produce.Occurring a logical one in these two lines just represents to do to appear a supposition.No matter which logical one appears, all can through or door 208 make with door second input end of 202 and open.Drive trigger 210 and D input end and and door 212 and 214 with the output of door 202.One " 1 " appears on line 204 and 206, and becomes with output terminal with door 202 and concern the time, just represent once to do to appear a certain supposition.Can produce a signal in this case and should be abolished, so that proofread and correct FMET32 or the current value of SMET30 trigger with the quick still slow detection operation of pointing out to be in operation at that time.Decide SMET30 with door 212 and this signal of 214 usefulness or FMET32 need revise.

See Fig. 1 temporarily, these signals with final decision power are sent into line 58 and 60 respectively.The effect of the trigger 210 among Fig. 3 is before clock suspension, makes currently just to be finished in the executory clock period, to avoid this CPU locking.Certainly, be that the vector that has a mistake in a clock period appears on the control store address bus 10 under the situation of mistake in supposition.And its correct selection will be added on the control store address bus 10 by traffic pilot 12.Remove SMET30, outside FMET32 and the trigger 210, the clock of all registers has all stopped one-period.As shown in Figure 3, this is to be connected to and door 218 by the signal with phase inverter 216, and inhibit signal caused and produce.

Now referring to Fig. 4, shown is a preferable embodiment of return address storehouse.This return address storehouse can be made up of some traffic pilots and register.The effect of traffic pilot is the mode that register is connected into passage, a closed loop or return feedback.Though those of skill in the art in the art know that all sort circuit is arranged can arbitrary number of level, the present embodiment shown in Figure 4 is to have N level sort circuit to arrange.

Earlier referring to traffic pilot MUXo 220, this MUXo 220 can will be from the signal of the MUX98 return address storehouse RASo 222 that packs into through line 224 as can be seen, or receive the content of return address stack register RASN 226 through line 228, or, also can receive the content of RAS1232 through line 234 through the content circulation of line 230 with the RASo under it 222.Equally, MUX1236 both can be on line 238 will have been packed RAS1232 from the signal of MUX98 into, also can receive the content of RASo222 through line 240, or through the content of line 242 circulation RAS1232, also can receive the content of RAS2244 through line 246.

Only there are these two traffic pilots of MUXo220 and MUX1236 just can receive signal from MUX98.All other traffic pilot then only can be accepted the content of a register in this system, or its content of register of circulating, or receives the content of next register.By this kind method, various data just can advance stack down or go up and release stack, or stay among storehouse.

The control of traffic pilot selects logic device 270 to insert a signal realization on line 272 by one.This signal controlling all traffic pilots in the storehouse of return address, and determined the type of flow of each register.Select logic device 270 to be driven by the signal (production method of this signal is narrated in conjunction with Fig. 2) of NoP1 and NoP2 and the output of SMET30 and FMET32 trigger (see figure 1).In addition, can deliver to selection logic device 270 places through line 274 from a field of microcode second level part.

The operating process of storehouse is as follows.The general logic device 270 of selecting makes each stack register form self circulation, and when certain subroutine was called, a return address just was admitted among the RASO or RAS1 of this storehouse, this depends on appearance be fast or slow-action use.Select logic device 270 its content with each register of storehouse to be pushed ahead for the certain condition of each traffic pilot of storehouse.Microcode has determined it is that the RIADR register 96 or the content of SK bus 100 will be sent into storehouse.

If be subroutine call at a slow speed, then when this call instruction is in the second level of execution, microcode field 274 just makes the MUXo RASo that packs into.If the set of SMET trigger, then when next time clock, storehouse just pushes away under the quilt.

Similarly, be quick calling as what occurred, then when this instruction of calling be when being positioned at the second level of execution, just MUX1 can be driven and be encased in RAS1.But with slow-action be with different, unless FMET trigger 32 set pack into and under push away all and can not take place.

As can be seen from Figure 4, pack into or push-down operation is separated.By using this kind storehouse, just can use this kind hardware, i.e. the hardware that should provide a return address additional copy to finish usually until this branching decision.

The pop-up of storehouse, or the operation of returning from subroutine call is as follows.

In returning at a slow speed, microcode field 274 makes each traffic pilot of storehouse release stack (being also referred to as pop-up) on the content in the register with SMET trigger 30 by selecting logic device 270.This move be that instruction in this return address is when being in the third level of execution and in the set of SMET trigger.Be added in the traffic pilot 64 during time clock before stack pop-up of the output of RAS1232.

Similarly, when returning soon when this link order is in the second level of execution and FMET set, just with stack pop-up.It should be noted owing to be pipelining, push away down and pop-up between can clash.Under this conflict situations, both all can not occur, and can carry out but pack into.

If fast or slow-action with or the second level returned the term of execution, the signal of NoP2 has appearred at the output terminal of selecting logic device 270, at this moment no matter be to pack into, push away down or pop-up all can not take place.

The another kind of design proposal of this storehouse has been to use the dual ported register assembly, it data can be deposited in storehouse and from storehouse during sense data with used address pointer separately.

Now referring to Fig. 5, this is one and is used for detection selection logic diagram quick and that slow detection is selected.The operating process of these modules is as follows.As shown in Figure 5, a large amount of testing conditions in 40 places is admitted to the input end of traffic pilot (MUX) 302 among the figure.Selecting which input to make it is to be finished by a microcode field in this microcode first order of diagram 304 places by traffic pilot 302.The output of traffic pilot 302 is admitted to 2: 1 optimum traffic pilots (2: 1MUX) 308 input end through line 306.Another input source of 2: 1 traffic pilots 308 is then from a field of microcode, and this testing conditions is satisfied in its decision is that positive what still bear for " very " is " very ".Traffic pilot 308 is driven by the input end 58 or 60 that final decision power is arranged, and this depends on this parts representative is selector switch or rapid selector at a slow speed.The output of traffic pilot 308 is to satisfy detection line 46 or 50, and this depends on which module what discussing is.So far, the those of skill in the art in this area as can be seen, any in a large amount of testing conditions all can be respectively applied for SMET 30 or the set of FMET32 trigger, the selection of its condition is controlled by this microcode fully.The appearance of a certain optimal conditions is the result that the lastrow microcode is selected testing conditions.

Claims (1)

1. In the central processing unit of data handling system, the hardware that is used to carry out micrometastasis comprises:

   The device that can preserve one first address is used for the continuous micro-order of following neighbour that will carry out;

   The device that can preserve one second address is used to carry out quick micrometastasis;

   The device that can preserve a three-address is used to carry out micrometastasis at a slow speed;

   Selecting arrangement is used to select one of above-mentioned first, second and three-address, and it can be sent on the control store address bus;

   The parts of controlling above-mentioned selecting arrangement are with the testing conditions of response with the microcode selection.

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