CN2917137Y

CN2917137Y - TD-SCDMA synchronizer

Info

Publication number: CN2917137Y
Application number: CNU2006200427690U
Authority: CN
Inventors: 张宇
Original assignee: JESON WIRELESS Ltd
Current assignee: JESON WIRELESS Ltd
Priority date: 2006-06-13
Filing date: 2006-06-13
Publication date: 2007-06-27
Anticipated expiration: 2016-06-13

Abstract

A TD-SCDMA synchronizer is provided, which comprises a 48chips band and 64chips band arranged in an emitter TD-SCDMA sub-frame to respectively or synchronously discriminate waves, acquire characteristic window time slot, compare the reference time slot captured by the receiving terminal with the characteristic window time slot. Current sequence of base station can be confirmed according to the relative position of the comparison. Meanwhile, the sequence of the receiving terminal is synchronized with the base station sequence. The utility model has advantages of simple design, easy implementation, production in batch and lower cost.

Description

The TD-SCDMA synchronizer

Technical field

The utility model relates to a kind of at 3G mobile communication TD-SCDMA synchronizer.

Background technology

WCDMA, CDMA2000 and TD-SCDMA have formed three big 3G mainstream standard, and wherein TD-SCDMA is classified as one of 3G standard by country, 3GPP TSG RAN and International Telecommunication Association.All technical advantages of comprehensive TDD of TD-SCDMA and CDMA have air interface flexibly, and have adopted synchronization CDMA, smart antenna, software radio, a series of new and high technologies such as low spreading rate, baton handover and joint-detection.Simultaneously, TD-SCDMA has the highest spectrum efficiency in three standards.Along with to covering on a large scale and the progressively solution of problems such as high-speed mobile, TD-SCDMA will become the 3G solution of optimum cost.

In the mobile network, the signal that repeater and trunk amplifier (be called for short " dried putting ") send base station and mobile phone amplifies respectively and transmits, and is indispensable auxiliary overlay device in the large-scale network-estabilishing, and it shows in the 2G network is fully showed.Because cost advantage and easy to use is widely used in indoor covering in building and network and mends blind.

The time division duplex of TD-SCDMA is different from the Frequency Division Duplexing (FDD) of other 2G and 3G standard.The upward signal of TD-SCDMA and downstream signal are in same frequency range, and different time transmits.And the upward signal of frequency division duplex system and downstream signal, transmit by frequency range duplexer is at interval arranged simultaneously at different frequency range.This shows that upward signal and downstream signal are vital in the TD-SCDMA system synchronously, effect accurately synchronously is equivalent to the up-downgoing frequency range interval in the frequency division duplex system.

TD-SCDMA repeater and dried putting by a time-division switching are controlled the transmission at different time of upward signal and downstream signal.This time-division switching must be synchronous with the time-division switching of base station, thereby avoid the mutual interference mutually of upward signal and downstream signal.

Summary of the invention

The purpose of this utility model is to provide a kind of TD-SCDMA synchronizer, realizes synchronously that with the base station it is synchronous in the TD-SCDMA system to solve upward signal and downstream signal thereby the signal that receives is carried out the detection analysis.

For reaching above-mentioned purpose the utility model 48chips section in the transmitting terminal TD-SCDMA subframe and 64chips section are carried out detection respectively or simultaneously, obtain the characteristic window time slot, reference time slot and the contrast of characteristic window time slot with the receiving terminal intercepting, determine the current sequential of base station, adjust to the base station sequential receiving terminal sequential synchronous.

The voltage of detection output is delivered to the threshold level comparison circuit, relatively exports the Transistor-Transistor Logic level signal with presetting reference voltage, and this Transistor-Transistor Logic level signal is delivered to wave analyzer.

Wave analyzer is to deliver to d type flip flop after the output of threshold level comparison circuit, d type flip flop output and the output of threshold level comparison circuit, deliver to a two AND circuit simultaneously, two AND circuit export another d type flip flop to, this d type flip flop output 48chips section and 64chips section characteristic window time slot, the characteristic window time slot is delivered to a 5ms cycle counter, and the cycle of this cycle counter is identical with the length of subframe.

The frame structure of TD-SCDMA is divided into 2 5ms subframes with the radio frames of 10ms, and each subframe is divided into seven conventional time slots and three special time slots that length is 675us again.These three special time slots are respectively DwPTS (descending pilot frequency time slot), GP (protection time slot) and UpPTS (uplink pilot time slot).From shown in TD-SCDMA subframe structure figure as can be seen, some time slot is unique in each subframe time slot, only occurs once.By analysis, wherein 48 Chips sections and 64 Chips sections are unique in each subframe structure, do not repeat, and the length of 48 Chips sections and 64 Chips sections and level intensity all be better than other available characteristic window, so be selected as the characteristic window time slot in the synchronous circuit.Reference time slot by the intercepting receiving terminal, contrast respectively simultaneously with 48 Chips sections and 64 Chips sections, determine the position of 48 Chips sections and 64 Chips sections, thereby determine the benchmark sequential of TD-SCDMA synchronizing sub-frame, adjust to the base station sequential receiving terminal sequential synchronous.

Superior effect of the present utility model is that method for designing is simple, is easy to realize, is convenient to produce in batches and reduce cost.

Description of drawings

Fig. 1 is a schematic block circuit diagram of the present utility model;

Fig. 2 is the threshold level comparison circuit of Fig. 1 and the circuit diagram of wave analyzer;

Fig. 3 is the structure chart of TD-SCDMA subframe.

Embodiment

See also accompanying drawing 1,2, shown in 3, a kind of TD-SCDMA synchronizer of the utility model, 3 pairs of transmitting terminal base station signals of receiving terminal detecting circuit 1 carry out power detection, the analog voltage signal of output is delivered to threshold level comparison circuit 4, relatively produce the Transistor-Transistor Logic level signal with a reference voltage that presets, this Transistor-Transistor Logic level signal is delivered to the d type flip flop 51 of wave analyzer 5, a two AND circuit 52 is delivered in d type flip flop output 51 and 4 outputs of threshold level comparison circuit simultaneously, two AND circuit 52 export another d type flip flop 53 to, this d type flip flop 53 obtains 48chips section 9 and 64chips section 10 characteristic window time slots, 48chips section 9 and 64chips section 10 characteristic window time slots are delivered to a 5ms cycle counter 6,5ms cycle counter 6 is a count pulse with local clock 2, cycle period is 5ms, identical with the length of subframe, reference time slot contrast with this 48chips section 9 and 64chips section 10 characteristic window time slots and receiving terminal intercepting, determine the current sequential of base station according to the relative position of 48chips section 9 and 64chips section 10 characteristic window time slots and reference time slot, receiving device is adjusted to sequential and the current sequential in base station, thereby the sequential between realization and the base station is synchronous.

Claims

1, a kind of TD-SCDMA synchronizer is characterized in that:

48chips section in the transmitting terminal TD-SCDMA subframe and 64chips section are carried out detection respectively or simultaneously, obtain the characteristic window time slot, with the reference time slot and the contrast of characteristic window time slot of receiving terminal intercepting, determine the current sequential of base station, adjust to the base station sequential receiving terminal sequential synchronous.

2, a kind of TD-SCDMA synchronizer according to claim 1 is characterized in that:

3, a kind of TD-SCDMA synchronizer according to claim 2 is characterized in that:

Described wave analyzer, be to deliver to d type flip flop after the output of threshold level comparison circuit, d type flip flop output and the output of threshold level comparison circuit, deliver to a two AND circuit simultaneously, two AND circuit export another d type flip flop to, this d type flip flop output 48chips section and 64chips section characteristic window time slot are delivered to a 5ms cycle counter with the characteristic window time slot, and the cycle of this cycle counter is identical with the length of subframe.