CN2907100Y - Long-range submarine high speed data transmission circuit - Google Patents
Long-range submarine high speed data transmission circuit Download PDFInfo
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- CN2907100Y CN2907100Y CNU200520142004XU CN200520142004U CN2907100Y CN 2907100 Y CN2907100 Y CN 2907100Y CN U200520142004X U CNU200520142004X U CN U200520142004XU CN 200520142004 U CN200520142004 U CN 200520142004U CN 2907100 Y CN2907100 Y CN 2907100Y
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Abstract
The utility model discloses a long-distance underwater high-speed data transmission circuit for the towed line sonar. The circuit is composed of an RS485 receiving circuit, an FPGA logic circuit, a HOTLink transmitter and receiver circuit and a crystal oscillator circuit. Wherein the FPGA logic circuit is composed of a converted circuit of series parallel connection, an FIFO circuit, an RS485 accepting state control circuit, a HOTLink accepting state control circuit, a HOTLink sending state control circuit, a multiplexer and a priority decision circuit. The underwater data transmission circuit provided by the utility model has the advantages of liable performance, high data transmission speed and miniaturization, being used for the underwater high-speed data transmission of the towed line sonar.
Description
Technical field
The utility model relates to a kind of remote underwater high-speed data transmission circuit, particularly a kind of remote underwater high-speed data transmission circuit that is used to drag the linear array sonar.
Background technology
At present, the prior art to the high-speed underwater digital data transmission mainly contains:
As document 1: digital sonar design principle, Li Qihu, the Anhui education publishing house, 2003.2 and document 2:John Walrod.ATM Telemetry in Towed Arrays.In:Undersea Defense Technology1997.Hamburg, Germany:June 24-26, introduced in 1997: the linear array sonar of being made up of the underwater sensor array that drags occupies an important position in Underwater Acoustics Engineering all the time, and the linear array sonar all drags greatly developing in the big state in each ocean.It is early stage that to drag the linear array sonar to adopt be analog signal transmission, be that directly delivering to the base station with the form of analog signal carried out digital conversion and signal processing after sensor signal output was amplified through filtering, its deficiency is signal attenuation and distortion seriously, and inter-signal interference is bigger.
As document 3:Planning Systems Incorporated.SAKI
TMATM-SONET Network Node (SAKI
TM-NIC-7) .2002.04 and John Walrod.ATM Telemetry in Towed Arrays.In:Undersea Defense Technology 1997.Hamburg, Germany:June 24-26, disclosed in 1997: U.S. PSI (Planning Systems Incorporated, abbreviation PSI) company has developed the underwater digit transport module ATM-SONET node based on atm technology, and this node is adopted by the state-of-the-art linear array TB-29A fine rule battle array of dragging of USN.
At home, the underwater digital data transmission circuit that does not also domesticize fully at present.
In the existing underwater high-speed data transmission technology, exist main shortcoming as follows:
(1) remote analog signal transmission technology has following shortcoming: the diameter of towing cable and weight are along with the increase of hydrophone array is increasing, and signal attenuation and distortion are serious, and inter-signal interference is bigger etc.;
(2) deficiency of existing underwater digital transmission circuit based on atm technology is: the restriction that data transmission rate is subjected to atm technology can not further improve; Complexity that realizes in view of atm technology and the restriction of dragging linear array towing cable internal diameter simultaneously realizes that based on the underwater digital transmission technology of atm technology miniaturization has very big difficulty and complexity on engineering.
Therefore, the deficiencies in the prior art just need a kind of improved remote underwater high-speed data transmission circuit.
The utility model content
The purpose of this utility model is to solve the diameter of towing cable in the existing underwater simulation formula transfer of data and weight along with the increase of hydrophone array is increasing, and signal attenuation and distortion are serious, the problem that inter-signal interference is bigger; The purpose of this utility model also is to solve the complexity based on the ATM data transmission technology, realizes the miniaturization of module, reliability; The purpose of this utility model also is in order to realize the production domesticization of underwater digital data transmission circuit; Thereby the utility model provides a kind of dependable performance, message transmission rate height, miniaturization, is used to drag the remote underwater high-speed data transmission circuit of linear array sonar.
To achieve these goals, the utility model is taked following technical scheme:
A kind of remote underwater high-speed data transmission circuit as shown in Figure 1, comprising:
RS485 receiving circuit 1 is used to receive packet;
HOTLink transmitter/receiver circuit 3 is connected with described fpga logic circuit 2;
Crystal oscillating circuit 4 is connected with described RS485 receiving circuit 1, described fpga logic circuit 2, described HOTLink transmitter/receiver circuit 3 respectively, is used to provide clock signal.
In the foregoing circuit, further, described RS485 receiving circuit 1 adopts the RS485 host-host protocol to receive two paths of data, is mainly used in the packet that receives low data rate.
In the foregoing circuit, further, described fpga logic circuit 2 as shown in Figure 2, comprising:
The one FIFO (first in first out is called for short FIFO) circuit connects 21;
Second fifo circuit connects 22;
First serial-parallel conversion circuit 23 is connected with described first fifo circuit 21;
Second serial-parallel conversion circuit 24 is connected with described second fifo circuit 22; The input of described first and second serial-parallel conversion circuits is connected with described RS485 receiving circuit 1 respectively, be used to receive the two paths of data that described RS485 receiving circuit 1 receives and will change after data import described first and second fifo circuits respectively;
The 3rd fifo circuit 25 is used to receive the circuit-switched data bag that described HOTLink transmitter/receiver circuit 3 receives;
RS485 accepting state control circuit 26 is used to control the state of described RS485 receiving circuit 1;
HOTLink accepting state control circuit 27 is used to control the accepting state of described HOTLink transmitter/receiver circuit 3;
The output signal of described first fifo circuit 21, second fifo circuit 22, the 3rd fifo circuit 25 enters described multiplexer 29, and the output signal of described multiplexer 29 enters the 4th fifo circuit 30;
HOTLink transmit status control circuit 31 is used to control the transmit status of described HOTLink transmitter/receiver circuit 3;
Described the 4th fifo circuit 30 is connected with described HOTLink transmit status control circuit 31, and the packet that output priority is high arrives described HOTLink transmitter/receiver circuit 3;
Described RS485 accepting state control circuit 26 is connected with described second fifo circuit 22 with described first fifo circuit 21 respectively;
Described HOTLink accepting state control circuit 27 is connected with described the 3rd fifo circuit 25.
In the foregoing circuit, further, described priority decision circuit 28 is adjudicated by order priority mechanism.
In the foregoing circuit, further, as shown in Figure 3, described HOTLink transmitter/receiver circuit 3 is by a HOTLink transtation mission circuit 41, one HOTLink receiving circuits 42 and be attached thereto first transformer 43, second transformer 44 that connect respectively and form.As shown in Figure 3, HOTLink transmitter/receiver circuit 3 adopts the reception of HOTLink host-host protocol and sends data by HOTLink transtation mission circuit 41 and HOTLink receiving circuit 42 wherein, be mainly used in the packet that receives and send High Data Rate, its priority of data packets of receiving also all is higher than the priority of data packets that RS485 receiving circuit 1 receives simultaneously.
In the foregoing circuit, further, crystal oscillating circuit 4 is used for providing the groundwork clock (as Fig. 1 signal A and signal I) of this module normal operation, signal A is used for providing work clock to HOTLink reception transtation mission circuit and fpga logic circuit, and signal I is used for providing work clock to the RS485 receiving circuit.
Above-mentioned order priority mechanism is as follows: setting in this transmission circuit RS485 receiving circuit 1 usually, to receive priority of data packets be minimum two min, min+1 (min=0 of priority, 1,2, max), the benchmark priority of setting this transmission circuit is min, the limit priority of setting this transmission circuit simultaneously is max, set decision circuit and receive that priority of data packets is i, min≤i≤max wherein, the value size of max subtracts 1 for the number of underwater digital data transmission circuit in the data transmission link under water.Decision circuit sends this packet according to priority order from high to low, at first send the packet that priority is max, other two packets are in wait state, packet of every transmission, priority decision circuit 28 countings add 1, when the counting size is max-min+1, the counting zero clearing, priority decision circuit 28 restarts counting.
The high-speed underwater digital data transmission system that is used to drag the linear array sonar of the present utility model, its workflow is as follows: RS485 receiving circuit 1 adopts the RS485 agreement to receive the packet of low data rate by cable, HOTLink receives transtation mission circuit 3 and adopts the HOTLink agreements to receive the packet of High Data Rate by cable, the packet that receives and in order priority carry out transmitting by HOTLink transtation mission circuit 41.
Compared with prior art, advantage of the present utility model is:
(1) the utility model adopts based on digital logic hardware circuit, and its reliability, stability access sufficient assurance, and circuit scale is little, can realize miniaturization dragging under the restricted situation of linear array towing cable internal diameter.
(2) application of Cheng Shu digital transmission technology HOTLink agreement and RS485 agreement has further improved the reliability of module.
(3) the fpga logic circuit in this module is mainly by FIFO, string and conversion, and counter and some simple control circuits are fit to Verilog HDL language description very much, can revise design as required.
Description of drawings
Fig. 1 represents the composition diagram of underwater digital data transmission circuit of the present utility model;
Fig. 2 represents the circuit block diagram of fpga logic circuit;
Fig. 3 represents that HOTLink sends the circuit block diagram of accepting circuit;
In above-mentioned accompanying drawing, have the annexation of line segment indication circuit of arrow and the trend of data, English alphabet such as A, the B on line segment next door ... Deng conveniently being used for mark annexation and data for statement in the text.
Embodiment
Below in conjunction with the drawings and specific embodiments the utility model is described in further detail:
With reference to figure 1, RS485 receiving circuit 1 adopts the RS485 host-host protocol to receive two paths of data, is mainly used in the packet that receives low data rate.
First fifo circuit connects 21;
Second fifo circuit connects 22;
First serial-parallel conversion circuit 23 is connected with described first fifo circuit 21;
Second serial-parallel conversion circuit 24 is connected with described second fifo circuit 22; The input of described first and second serial-parallel conversion circuits is connected with described RS485 receiving circuit 1 respectively, be used to receive the two paths of data that described RS485 receiving circuit 1 receives and will change after data import described first and second fifo circuits respectively;
The 3rd fifo circuit 25 is used to receive the circuit-switched data bag that described HOTLink transmitter/receiver circuit 3 receives;
RS485 accepting state control circuit 26 is used to control the state of described RS485 receiving circuit 1;
HOTLink accepting state control circuit 27 is used to control the accepting state of described HOTLink transmitter/receiver circuit 3;
The output signal of described first fifo circuit 21, second fifo circuit 22, the 3rd fifo circuit 25 enters described multiplexer 29, and the output signal of described multiplexer 29 enters the 4th fifo circuit 30;
HOTLink transmit status control circuit 31 is used to control the transmit status of described HOTLink transmitter/receiver circuit 3;
Described the 4th fifo circuit 30 is connected with described HOTLink transmit status control circuit 31, and the packet that output priority is high arrives described HOTLink transmitter/receiver circuit 3;
Described RS485 accepting state control circuit 26 is connected with described second fifo circuit 22 with described first fifo circuit 21 respectively;
Described HOTLink accepting state control circuit 27 is connected with described the 3rd fifo circuit 25.
Fpga logic circuit 2 is controlled RS485 receiving circuit 1 and HOTLink reception transtation mission circuit 3 respectively by control signal F, G and H, receive the two paths of data that RS485 receiving circuit 1 receives by data-signal B, C, receive HOTLink by data-signal D and receive the circuit-switched data bag that transtation mission circuit 3 receives, three circuit-switched data store the data to respectively in first fifo circuit 21, second fifo circuit 22 and the 3rd fifo circuit 25, and data are cushioned.The precedence information of the packet inside that obtains receiving by RS485 accepting state control circuit 26 and HOTLink accepting state control circuit 27 respectively, RS485 accepting state control circuit 26 and HOTLink accepting state control circuit 27 are delivered to priority decision circuit 28 with these precedence informations as interruption respectively, priority decision circuit 28 is adjudicated with multiplexing by order priority mechanism, sends the high packet of priority by data-signal E then and receives transtation mission circuit 3 to HOTLink.In the present embodiment, as an example, above-mentioned order priority mechanism is as follows: setting RS485 receiving circuit in this transmission circuit 1 usually, to receive priority of data packets be minimum two 3,4 of priority, the benchmark priority of setting this transmission circuit is 3, and the limit priority of setting this transmission circuit simultaneously is 10 (choosing value 10 shows herein under water has 10 underwater digital data transmission circuits of the present utility model on the data transmission link).Priority decision circuit 28 sends this packet according to priority order from high to low, at first send priority and be 10 packet, other two packets are in wait state, packet of every transmission, counting in the priority decision circuit 28 adds 1, when the counting size is 8, the counting zero clearing, priority decision circuit 28 restarts counting.
HOTLink receives the inside of transtation mission circuit 3 and forms as shown in Figure 3, by HOTLink transtation mission circuit 41, HOTLink receiving circuit 42 and first transformer 43, second transformer 44 are formed, adopt the HOTLink host-host protocol to receive and the transmission data, be mainly used in the packet that receives and send High Data Rate, its priority of data packets of receiving also all is higher than the priority of data packets that RS485 receiving circuit 1 receives simultaneously.
With reference to Fig. 1, in order to guarantee long stability of Digital Transmission circuit and precision, crystal oscillating circuit 4 adopts on the market buys the high accuracy crystal oscillator, and this crystal oscillating circuit 4 is provided for the work clock 10.24MHz (I of clock signal shown in Fig. 1) that HOTLink receives the work clock 19.2MHz (A of clock signal shown in Fig. 1) of transtation mission circuit 3 and fpga logic circuit 2 and is used for the RS485 receiving circuit.
The workflow of this enforcement is as follows: RS485 receiving circuit 1 adopts the RS485 agreement to receive the packet of low data rate by cable, HOTLink receives transtation mission circuit 3 and adopts the HOTLink agreements to receive the packet of High Data Rate by cable, the packet that receives and in order priority carry out transmitting by HOTLink transtation mission circuit 41.
In the present embodiment, except that special indicating, conventional products and conventional annexation that all circuit all adopt market to sell.
In this enforcement, the area of side circuit plate is 105mm * 20mm, has satisfied the needs of existing towing cable internal diameter; Data transmission rate is 192M bits/s simultaneously; Adopt the pseudo noise code of m-sequence to test, the data transmission error rate is less than 1.1176 * 10
-12Simultaneously this under water data transmission circuit with compare simple and practically based on the underwater digital transmission technology of ATM, and be easy to realize miniaturization.This is the fpga logic circuit 2 employing Verilog HDL language descriptions of data transmission circuit under water, can revise design as required.
The application mode of a underwater digital data transmission circuit module has just been introduced in this enforcement here, simultaneously the utility model can realize that also a plurality of such underwater digital data transmission circuit modules unite use, thereby realizes a cover underwater digital data transmission link.The concrete connected mode of a plurality of circuit modules is as follows:
As an example, the number of setting the underwater digital data transmission circuit is 10, according to above-mentioned order priority mechanism, begins the benchmark priority of setting 10 underwater digital data transmission circuits respectively of order from small to large by " 0 ".With reference to Fig. 3, benchmark priority is connected with the reception twisted-pair feeder K of benchmark priority for the underwater digital data transmission circuit of " 8 " for the transmission twisted-pair feeder G of the underwater digital data transmission circuit of " 9 ", the rest may be inferred, last benchmark priority is connected with the reception twisted-pair feeder K of benchmark priority for the underwater digital data transmission circuit of " 0 " for the transmission twisted-pair feeder G of the underwater digital data transmission circuit of " 1 ", wherein benchmark priority is not done connection for the reception twisted-pair feeder K of the underwater digital data transmission circuit of " 9 ", benchmark priority is connected with processing terminal for the transmission twisted-pair feeder G of the underwater digital data transmission circuit of " 0 ", thereby forms a underwater digital data transmission link of being made up of 10 underwater digital data transmission circuits.
With reference to Fig. 1, RS485 receiving circuit 1 is used for the data of receiving sensor array transducer in 10 underwater digital data transmission circuits.
Unite use by a plurality of underwater digital data transmission circuits, realized the transfer of data of transducer in the sensor array is arrived the purpose of handling terminal.
In the cover underwater digital data transmission link of introducing in the above, except that special indicating, conventional products and conventional annexation that all circuit all adopt market to sell.
It should be noted last that above embodiment is only unrestricted in order to the explanation the technical solution of the utility model.Although the utility model is had been described in detail with reference to embodiment, those of ordinary skill in the art is to be understood that, the technical solution of the utility model is made amendment or is equal to replacement, the spirit and scope that do not break away from technical solutions of the utility model, it all should be encompassed in the middle of the claim scope of the present utility model.
Claims (4)
1, a kind of remote underwater high-speed data transmission circuit comprises:
Be used to receive the RS485 receiving circuit (1) of packet;
Fpga logic circuit (2) is connected with described RS485 receiving circuit (1);
HOTLink transmitter/receiver circuit (3) is connected with described fpga logic circuit (2);
Be used to provide the crystal oscillating circuit (4) of clock signal, be connected with described RS485 receiving circuit (1), described fpga logic circuit (2), described HOTLink transmitter/receiver circuit (3) respectively.
2, according to the described remote underwater high-speed data transmission circuit of claim 1, it is characterized in that described fpga logic circuit (2) comprising:
First fifo circuit (21);
Second fifo circuit (22);
First serial-parallel conversion circuit (23) is connected with described first fifo circuit (21);
Second serial-parallel conversion circuit (24) is connected with described second fifo circuit (22); The input of described first and second serial-parallel conversion circuits is connected with described RS485 receiving circuit (1) respectively, receive the two paths of data that described RS485 receiving circuit (1) receives and will change after data import described first and second fifo circuits respectively;
The 3rd fifo circuit (25) is used to receive the circuit-switched data bag that described HOTLink transmitter/receiver circuit (3) receives;
Be used to control the RS485 accepting state control circuit (26) of the state of described RS485 receiving circuit (1);
Be used to control the HOTLink accepting state control circuit (27) of the accepting state of described HOTLink transmitter/receiver circuit (3);
Priority decision circuit (28) is connected with the interrupt signal of described RS485 accepting state control circuit (26) with described HOTLink accepting state control circuit (27), and court verdict is input in the multiplexer (29);
The output signal of described first fifo circuit (21), second fifo circuit (22), the 3rd fifo circuit (25) enters described multiplexer (29), and the output signal of described multiplexer (29) enters the 4th fifo circuit (30);
Be used to control the HOTLink transmit status control circuit (31) of the transmit status of described HOTLink transmitter/receiver circuit (3);
Described the 4th fifo circuit (30) is connected with described HOTLink transmit status control circuit (31), and the packet that output priority is high arrives described HOTLink transmitter/receiver circuit (3);
Described RS485 accepting state control circuit (26) is connected with described second fifo circuit (22) with described first fifo circuit (21) respectively;
Described HOTLink accepting state control circuit (27) is connected with described the 3rd fifo circuit (25).
3, according to the described remote underwater high-speed data transmission circuit of claim 1, it is characterized in that, described HOTLink transmitter/receiver circuit (3) is by a HOTLink transtation mission circuit (41), a HOTLink receiving circuit (42) and be attached thereto first transformer (43), second transformer (44) that connect respectively and form; Wherein, HOTLink transmitter/receiver circuit (3) adopts the reception of HOTLink host-host protocol and sends data by HOTLink transtation mission circuit (41) and HOTLink receiving circuit (42) wherein, and the priority of data packets that it is received is higher than the priority of data packets that RS485 receiving circuit (1) receives.
According to each described remote underwater high-speed data transmission circuit of claim 1-3, it is characterized in that 4, being linked in sequence by a plurality of described remote underwater high-speed data transmission circuits constitutes the remote underwater high-speed data transmission link of a cover.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200520142004XU CN2907100Y (en) | 2005-11-23 | 2005-11-23 | Long-range submarine high speed data transmission circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200520142004XU CN2907100Y (en) | 2005-11-23 | 2005-11-23 | Long-range submarine high speed data transmission circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2907100Y true CN2907100Y (en) | 2007-05-30 |
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ID=38115744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU200520142004XU Expired - Fee Related CN2907100Y (en) | 2005-11-23 | 2005-11-23 | Long-range submarine high speed data transmission circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2907100Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101676969B (en) * | 2008-09-17 | 2011-12-21 | 上海市电力公司 | Horizontal guiding drill while-drilling early warning high speed data transmission system |
| CN103544828A (en) * | 2012-07-12 | 2014-01-29 | 中国船舶重工集团公司第七二六研究所 | HOTLINK (high-speed optical transceiver link)-based hybrid-type high-speed data transmission digital sonar |
-
2005
- 2005-11-23 CN CNU200520142004XU patent/CN2907100Y/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101676969B (en) * | 2008-09-17 | 2011-12-21 | 上海市电力公司 | Horizontal guiding drill while-drilling early warning high speed data transmission system |
| CN103544828A (en) * | 2012-07-12 | 2014-01-29 | 中国船舶重工集团公司第七二六研究所 | HOTLINK (high-speed optical transceiver link)-based hybrid-type high-speed data transmission digital sonar |
| CN103544828B (en) * | 2012-07-12 | 2019-03-15 | 中国船舶重工集团公司第七二六研究所 | Mixed high-speed data based on HOTLINK transmit Digital Sonar |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070530 Termination date: 20091223 |