CN2904068Y - Linear Voltage Regulator - Google Patents

Abstract

The utility model provides a linear voltage regulator, it includes: a light load transistor and a heavy load transistor coupled between an input voltage and an output voltage; an error amplifier for generating an error signal to control a gate of the light-load transistor in response to a reference voltage signal and a feedback voltage signal, the feedback voltage signal representing an output voltage; a gate control circuit coupled to a gate of the heavy-duty transistor; and a mode selection circuit coupled between the error amplifier and the gate control circuit for generating a sense current signal representative of a current flowing through the light load transistor, and allowing the error signal to control the gate of the heavy load transistor via the gate control circuit when the sense current signal is greater than a critical current signal.

Description

Linear Voltage Regulator

【Technical field】

The utility model relates to a linear voltage regulator, in particular to a linear voltage regulator capable of improving efficiency under light load mode operation.

【Background technique】

The voltage regulator is used to supply the required output current to the load at a regulated output voltage. Linear voltage regulators use a power transistor operating in the variable resistance region as a passive component. The output voltage feedback controls the variable resistance value of the power transistor, so that the input voltage (such as the battery voltage) minus the potential difference of the power transistor across the variable resistance becomes the required regulated output voltage. Under light load mode operation, the current consumed by the error amplifier remains almost constant because the required output current is reduced, so the light load mode efficiency of the prior art linear voltage regulator is relatively low. shortcoming.

FIG. 1 shows a detailed circuit diagram of a prior art linear voltage regulator 10 . As shown in the figure, the prior art linear voltage regulator 10 has a power transistor 11 connected in series between the input voltage _Vin and the output terminal A. As shown in FIG. The gate of the power transistor 11 is controlled by an error signal V _err output from an output terminal of an error amplifier 12 . The error amplifier 12 has an inverting input terminal for receiving a reference voltage signal V _ref and a non-inverting input terminal for receiving a feedback voltage signal V _fb . Therefore, the error signal V _err output from the error amplifier 12 represents the difference between the feedback voltage signal V _fb and the reference voltage signal V _ref . The reference voltage signal V _ref is determined by the reference voltage generating circuit 13 and has a predetermined voltage value. The feedback voltage signal V _fb is generated by the feedback circuit 14 connected to the output terminal A to represent the output voltage V _out . For example, the feedback circuit 14 can be implemented by a voltage dividing resistor, wherein the resistors R1 and R2 are connected in series between the output terminal A and the ground potential, so that the divided voltage provided by the coupling point of the resistors R1 and R2 [R2/(R1+ R2)]*V _out is used as the feedback voltage signal V _fb . Therefore, the linear voltage regulator 10 supplies the regulated output voltage V _out and the required output current I _out to the load 15 via the output terminal A. As shown in FIG. In order to improve the ripple of the output voltage V _out , the capacitor C can be connected between the output terminal A and the ground potential.

As the current required by the load 15 varies, the output current I _out provided by the linear voltage regulator 10 varies more or less, but the output voltage V _out is maintained at [(R1+R2)/R2]*V _ref . In order to be capable of supplying a large output current I _out , the power transistor 11 must have a sufficiently large size. However, the large size of the power transistor 11 also results in an increase in gate capacitance. In this case, in order to effectively control the gate of the power transistor 11, the error amplifier 12 must be designed to have a small output impedance, which will result in a large current consumption. Therefore, when the linear voltage regulator 10 operates in the light load mode, that is, the output current I _out is small or close to zero, the efficiency of the linear voltage regulator 10 will be deteriorated due to the large current consumption caused by the error amplifier 12 .

Therefore, it is desirable to have a linear voltage regulator that can improve efficiency in light load mode.

【Content of utility model】

In view of the aforementioned problems, an object of the present invention is to provide a linear voltage regulator that can achieve the best efficiency in light load mode.

Another object of the present invention is to provide a linear voltage regulator that can provide a large enough output current under heavy load mode.

According to the utility model, a linear voltage regulator is provided, comprising: a light load transistor having a gate coupled between an input voltage and an output voltage; an error amplifier for responding to a reference voltage signal and a feedback voltage signal to generate an error signal for controlling the gate of the light load transistor, the feedback voltage signal representing the output voltage; a heavy load transistor having a gate coupled to the input voltage and the output voltage; a gate control circuit, which is coupled to the gate of the heavy load transistor; and a mode selection circuit, which is coupled between the error amplifier and the gate control circuit, for generating a detection current signal, which represents a current flowing through the light load transistor, and when the detection current signal is greater than a critical current signal, the mode selection circuit allows the error signal to control the gate of the heavy load transistor through the gate control circuit.

According to the linear voltage regulator of the present invention, two power transistors are connected in parallel between the input voltage and the output voltage, wherein one power transistor has a larger current driving capability (that is, a larger transistor size), and the other power transistor Then it has a smaller current driving capability (that is, a smaller transistor size). In the light load mode, the linear voltage regulator according to the present invention only turns on the power transistor with small current driving capability, so that the current consumed by the error amplifier is reduced, thereby improving the efficiency.

In addition, the linear voltage regulator according to the present invention uses a current detection unit to detect the current flowing through the power transistor with smaller current driving capability. When the current detected by the current detection unit exceeds a predetermined critical current value, it means that the operation of the linear voltage regulator enters a heavy load mode. In the heavy load mode, the mode selection circuit additionally turns on the power transistor with larger current driving capability through the gate control circuit, so as to provide a large enough output current to the load.

【Description of drawings】

FIG. 1 shows a detailed circuit diagram of a prior art linear voltage regulator.

FIG. 2 shows a circuit block diagram of the linear voltage regulator according to the present invention.

FIG. 3 shows a detailed circuit diagram of the gate control circuit and the mode selection circuit according to the present invention.

Description of main component symbols:

10 State of the Art Linear Voltage Regulators

11 Heavy Duty Power Transistors

12 error amplifier

13 Reference voltage generating circuit

14 Feedback circuit

15 load

20 Linear Voltage Regulators

21 light load power transistor

22 Gate control circuit

23 mode selection circuit

24 Current detection unit

25 current comparison unit

A output terminal

C _o capacitance

I _out output current

I _gen detects current signal

I _th critical current signal

INV1, INV2 Inverter

Q1 PMOS transistor

Q2~Q5 NMOS transistors

R1, R2 resistance

SS mode selection signal

TG1, TG2 transmission gate

V _in input voltage

V _out output voltage

V _err error signal

V _fb feedback voltage signal

V _ref reference voltage signal

【Detailed ways】

The following description and accompanying drawings will make the foregoing and other objects, features and advantages of the present invention more apparent. Here, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows a circuit block diagram of the linear voltage regulator 20 according to the present invention. The circuit components shown in FIG. 2 that are similar to the circuit components shown in FIG. 1 are marked with the same reference numerals, and for the sake of simplification, their descriptions are omitted below. As shown in the figure, the linear voltage regulator 20 according to the present invention has a heavy load power transistor 11 and a light load power transistor 21 connected in parallel between the input voltage _Vin and the output terminal A. The size of the light load power transistor 21 is designed to be smaller than that of the heavy load power transistor 11 , so that the current driving capability of the light load power transistor 21 is smaller than that of the heavy load power transistor 11 . In an embodiment according to the present invention, the current driving capability of the heavy-load power transistor 11 is designed to be five times that of the light-load power transistor 21 . The gate of the light load power transistor 21 is directly connected to the output terminal of the error amplifier 12 so as to be controlled by the error signal _Verr . However, the gate of the heavy-duty power transistor 11 is indirectly connected to the output terminal of the error amplifier 12 via the gate control circuit 22, so as to be controlled by the error signal _Verr , or connected to the input voltage V _in to become non-conductive. state.

The gate control circuit 22 is controlled by the mode selection signal SS output by the mode selection circuit 23 to determine whether the gate of the heavy load power transistor 11 is connected to the output terminal of the error amplifier 12 or to the input voltage _Vin . Specifically, the mode selection circuit 23 is regarded as an external circuit of the linear voltage regulator 20, which detects the current flowing through the light-load power transistor 21 at any time and adjusts the mode selection signal SS to determine whether to activate the heavy-duty power transistor SS through the gate control circuit 22. The load power transistor 11 is effective to achieve the best efficiency in the light load mode and provide a sufficiently large output current I _out in the heavy load mode.

The mode selection circuit 23 includes a current detection unit 24 and a current comparison unit 25 . The current detection unit 24 generates a detection current signal I _sen , which is proportional to the current flowing through the light-load power transistor 21 . The current comparison unit 25 is used for comparing the detection current signal I _sen with a predetermined threshold current signal I _th . When the detection current signal I _sen is smaller than the critical current signal I _th , that is, the linear voltage regulator 20 operates in the light load mode, the mode selection signal SS enables the gate control circuit 22 to prevent the error signal V _err from being supplied to the heavy load power transistor 11 , and make the heavy load power transistor 11 non-conductive. In this case, the error amplifier 12 only needs to control the light-load power transistor 21 with a smaller size, and thus the required current consumption thereof is reduced. Since the required output current I _out is quite small in the light load mode, sufficient current driving capability can be obtained only by using the light load power transistor 21 . When the detection current signal I _sen is greater than the critical current signal I _th , that is, the linear voltage regulator 20 operates in the heavy load mode, the mode selection signal SS enables the gate control circuit 22 to allow the error signal V _err to be supplied to the heavy load power transistor 11 . As a result, the error amplifier 12 simultaneously controls the light-load power transistor 21 with a smaller size and the heavy-load power transistor 11 with a larger size, thereby effectively maintaining a sufficiently large output current I _out .

Therefore, the linear voltage regulator 20 according to the present invention effectively obtains the best efficiency in the light load mode and provides a sufficiently large output current I _out in the heavy load mode.

FIG. 3 shows a detailed circuit diagram of the gate control circuit 22 and the mode selection circuit 23 according to the present invention. The circuit components shown in FIG. 3 that are similar to the circuit components shown in FIG. 2 are marked with the same reference numerals, and for the sake of simplification, their descriptions are omitted below. As shown, the gate control circuit 22 has two transmission gates TG1 and TG2. The gate of the power transistor 11 is coupled to the input voltage V _in through the transmission gate TG1 , and is coupled to the output terminal of the error amplifier 12 through the transmission gate TG2 for receiving the error signal _Verr . The conduction of the transfer gates TG1 and TG2 is controlled by the mode selection signal SS from the mode selection circuit 23 . The mode selection signal SS has a first state (such as a low voltage level) and a second state (such as a high voltage level). When the mode selection signal SS is in the first state, the transmission gate TG1 is turned on but the transmission gate TG2 is not turned on. In this case, the gate of the heavy-duty power transistor 11 is coupled to the input voltage _Vin through the transmission gate TG1 , so the heavy-duty power transistor 11 is not turned on and the linear voltage regulator 20 operates in a light-load mode. When the mode selection signal SS is in the second state, the transmission gate TG1 is not turned on but the transmission gate TG2 is turned on. In this case, the gate of the heavy-duty power transistor 11 is controlled by the error signal _Verr through the transmission gate TG2, so the linear voltage regulator 20 operates in the heavy-duty mode. Therefore, in response to the mode selection signal SS, the gate control circuit 22 can effectively allow the input voltage V _in to control the gate of the heavy load power transistor 11 through the transmission gate TG1 or allow the error signal V _err to control the heavy load through the transmission gate TG2 The gate of the power transistor 11.

In the preferred embodiment shown in FIG. 3, the current detection unit 24 of the mode selection circuit 23 is implemented by a PMOS transistor Q1. The gate of the transistor Q1 is connected to the gate of the light load power transistor 21 , and its source is connected to the source of the light load power transistor 21 . Therefore, the drain of the transistor Q1 can supply a sense current signal I _sen , which is proportional to the current flowing through the light-load power transistor 21 .

In the preferred embodiment shown in FIG. 3 , the current comparison unit 25 is designed as a current comparator with a hysteresis effect, so as to prevent unwanted noise from occurring during the transition between the light load mode and the heavy load mode. Specifically, the current comparison unit 25 uses a current mirror formed by NMOS transistors Q2 to Q3 to compare the detected current signal I _sen with the critical current signal I _th . The gates of the transistors Q2 and Q3 are coupled to each other, and the sources thereof are both connected to the ground potential. The drain of the transistor Q2 is used to receive the detection current signal I _sen , and the drain of the transistor Q3 is used to receive the threshold current signal I _th . In the light load mode, since the detection current signal I _sen is smaller than the critical current signal I _th , the drain potential of the transistor Q3 will be pulled up close to the input voltage V _in . In this case, the mode selection signal SS output from the inverter INV2 is at a low voltage level, so that the transfer gate TG1 is turned on but the transfer gate TG2 is not turned on. As a result, the gate of the heavy-duty power transistor 11 is coupled to the input voltage _Vin through the transmission gate TG1 , so the heavy-duty power transistor 11 is not turned on. When the detection current signal I _sen is greater than the critical current signal I _th , the drain potential flowing through the transistor Q3 will be pulled down to close to the ground potential. In this case, the mode selection signal SS output from the inverter INV2 is at a high voltage level, so that the transmission gate TG1 is not turned on but the transmission gate TG2 is turned on. As a result, the gate of the heavy-duty power transistor 11 is controlled by the error signal _Verr via the transmission gate TG2, so the linear voltage regulator 20 operates in the heavy-duty mode.

In order to prevent undesired switching noise during the transition period when the detection current signal I _sen is greater than or less than the critical current signal I _th , the current comparison unit 25 is further provided with NMOS transistors Q4 and Q5 to provide a hysteresis effect for current comparison. Specifically, the gate and the drain of the transistor Q4 are respectively connected to the gate and the drain of the transistor Q3. The transistor Q5 acts as a switch and is controlled by the mode selection signal SS output from the inverter INV2. When the mode selection signal SS is at a low voltage level, the transistor Q5 is not turned on so that the transistor Q4 cannot form a current channel. In this case, the detection current signal I _sen must be smaller than the critical current signal I _th , so as to maintain the drain of the transistor Q3 at a high voltage level. Once the detection current signal I _sen increases and exceeds the threshold current signal I _th , the drain potential of the transistor Q3 drops to make the mode selection signal SS transition to a high voltage level. In this case, the transistor Q5 is turned on by the mode selection signal SS at a high voltage level, so that the transistor Q4 forms a current channel, and as a result, the drain potential of the transistor Q3 is further pulled down. If the detection current signal I _sen is reduced to be slightly smaller than the critical current signal I _th due to disturbance during this switching period, because the current channel provided by the transistor Q4 can still allow a part of the critical current signal I _th to flow, so the transistor Q4 is effectively prevented from The drain potential of Q3 is pulled high to cause a state transition of the mode selection signal SS.

Although the present invention has been described by way of illustration of preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and similar arrangements apparent to those skilled in the art. Accordingly, the scope of the claims should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.

Claims (8)

1. A linear voltage regulator comprising: an error amplifier for generating an error signal in response to a reference voltage signal and a feedback voltage signal representing the output voltage; and a heavy duty transistor having a gate coupled to an input voltage and a Between the output voltage; it is characterized by: also includes a light load transistor having a gate coupled between the input voltage and the output voltage, the gate being controlled by an error signal generated by the error amplifier; a gate control circuit coupled to the gate of the heavily loaded transistor; and A mode selection circuit, coupled between the error amplifier and the gate control circuit, is used to generate a detection current signal, which represents a current flowing through the light load transistor, and when the detection current signal is greater than a threshold current signal , the mode selection circuit allows the error signal to control the gate of the heavily loaded transistor via the gate control circuit. 2. The linear voltage regulator as claimed in claim 1, characterized in that: The current drive capability of the heavy load transistor is greater than the current drive capability of the light load transistor. 3. The linear voltage regulator as claimed in claim 1, characterized in that: The size of the heavy load transistor is larger than the size of the light load transistor. 4. The linear voltage regulator as claimed in claim 1, characterized in that: The gate control circuit includes a first transmission gate and a second transmission gate, and is controlled by the mode selection circuit, so that when the first transmission gate is turned on, the input voltage controls the first transmission gate through the first transmission gate. The gate of the heavy-duty transistor is heavily loaded, and when the second transmission gate is turned on, the error signal controls the gate of the heavy-duty transistor through the second transmission gate. 5. The linear voltage regulator as claimed in claim 4, characterized in that: The mode selection circuit consists of: a current detection unit for generating the current detection signal, and A current comparison unit, used to compare the detection current signal with the critical signal and apply a mode selection signal to the gate control circuit according to the comparison, so that when the detection current signal is smaller than the critical current signal, the mode selection signal turning on the first transmission gate. 6. The linear voltage regulator as claimed in claim 4, characterized in that: The mode selection circuit consists of: a current detection unit for generating the current detection signal, and A current comparison unit, for comparing the detection current signal with the critical signal and applying a mode selection signal to the gate control circuit according to the comparison, so that when the detection current signal is greater than the critical current signal, the mode selection signal turning on the second transmission gate. 7. The linear voltage regulator as claimed in claim 1, characterized in that: The mode selection circuit consists of: a current detection unit for generating the detection current signal, and A current comparison unit is used for comparing the detection current signal and the critical current signal. 8. The linear voltage regulator as claimed in claim 7, characterized in that: The current comparison unit is a current comparator with hysteresis effect.

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