CN2899298Y - Self-adaptive wave trap against strong narrow-band interference for frequency-extending system - Google Patents
Self-adaptive wave trap against strong narrow-band interference for frequency-extending system Download PDFInfo
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- CN2899298Y CN2899298Y CNU2005200624622U CN200520062462U CN2899298Y CN 2899298 Y CN2899298 Y CN 2899298Y CN U2005200624622 U CNU2005200624622 U CN U2005200624622U CN 200520062462 U CN200520062462 U CN 200520062462U CN 2899298 Y CN2899298 Y CN 2899298Y
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Abstract
The utility model provides a self-adaptive wave trap against strong narrow-band interference for frequency-extending system which comprises an anti-aliasing filter module, an A/D conversion module, a DDC digital down converter module, a FIFO first-in and first-out module and a DSP digital signal processor, all of which are connected with each other in sequence and respectively connected with a power module; the DDC digital down converter module, the FIFO first-in and first-out module and the DSP digital signal processor are connected with a FPGA field programmer simultaneously; the A/D conversion module, the DDC digital down converter module, the DSP digital signal processor and the FPGA field programmer are respectively connected with a crystal oscillator, and the DSP digital signal processor is connected with a storage. The utility model has the advantages of strong practicability, simple structure, strong capacity for disturbance resistance, adjustable input and output according to requirement and generalization, which can be directly connected with the available equipment.
Description
Technical field
The utility model relates to the anti-interference equipment of spread spectrum system, particularly a kind of anti-intense arrow-band interference self-adaptive trap filter of spread spectrum system.
Background technology
At spread spectrum system when running into strong narrow band interference, spread spectrum system self is helpless, and therefore the receiving terminal of wanting safeguards system still can receive the signal in the regulation effective scope under various abominable electromagnetic environments, spread spectrum system can both normally be turned round, keep stable antijamming capability.
At present, domestic research and development about the anti-interference adaptive notch technology and equipment of spread spectrum system are still immature, and great majority are to concentrate in the research of theory analysis, the breadboard that also has some to make with analog form, but actual effect is not very desirable.
The deficiency that existing spread spectrum system Adaptive Anti-jamming notch technology exists: (1) adopts the mode of adaptive algorithm, when interference signal strengthens and increases, LMS (Least Mean Square Algorithm, lms algorithm) convergence of algorithm speed is slow, and real-time is poor.(2) adopt the mode of disturbing the inhibition number, under the analog circuit mode, then trapper need be corresponding one by one with interference, needs great amount of hardware resources when disturbing more.
Summary of the invention
The purpose of this utility model is to overcome the shortcoming of above-mentioned prior art, and a kind of anti-intense arrow-band interference self-adaptive trap filter of spread spectrum system real-time, simple in structure is provided.
The purpose of this utility model realizes by following proposal: the anti-intense arrow-band interference self-adaptive trap filter of this spread spectrum system, by the anti-aliasing filter module, the A/D conversion module, DDC (Digital Down Converter) Digital Down Converter Module, FIFO (First In First Out) first-in first-out module, DSP (DigitalSignal Processor) digital signal processor interconnects composition successively, and be connected with power module respectively, described DDC Digital Down Converter Module, FIFO first-in first-out module, the DSP digital signal processor is connected with the FPGA field programmable device simultaneously, described A/D conversion module, the DDC Digital Down Converter Module, the DSP digital signal processor, FIFO first-in first-out module and FPGA field programmable device are connected with crystal oscillator respectively, and described DSP digital signal processor also is connected with memory.
Described DSP digital signal processor is a high-speed floating point DSP digital signal processor.
Described memory comprises FLASH, SBSRAM (Synchronous Burst Static RandomAccess Memory, the synchronization burst static RAM (SRAM)), SDRAM (Synchronous Dynamic randomaccess memory, synchronous dynamic ram) memory, it is used to DSP digital signal processor stored program and working procedure.
Described power module comprises that output voltage is the DC power supply of difference 5V, 3.3V, 2.5V and 1.8V.
Described FIFO first-in first-out module is used for adjusting DDC output speed and DSP input rate.
Described FPGA field programmable device is used to dispose described DDC Digital Down Converter Module, it is worked after the programming initialization, cooperate the DDC Digital Down Converter Module to export described FIFO first-in first-out module to simultaneously, and the down-conversion rate of described DDC Digital Down Converter Module also can be adjusted on demand by the FPGA field programmable device.
The anti-interference self adaptation course of work of the anti-intense arrow-band interference self-adaptive trap filter of this spread spectrum system is:
(1) receiving terminal of spread spectrum system is transformed to analog intermediate frequency (IF) signal of 70MHz with the RF radiofrequency signal, inputs to the anti-aliasing filter module;
(2) the outer unwanted signal of anti-aliasing filter module filtering band and it is inputed to the A/D conversion module;
(3) described A/D conversion module is to the analog signal sampling digitlization, and the analog if signal of 70MHz is transformed into digital medium-frequency signal, and with digital data transmission to the DDC Digital Down Converter Module;
(4) the DDC Digital Down Converter Module is finished Digital Down Convert, the digital medium-frequency signal sampling is downconverted to the zero carrier baseband signal, and conversion of signals is become I, Q double-channel signal, delivers to the DSP digital signal processor processes;
(5) after the DSP digital signal processor is handled in real time to input signal, signal is exported.
The utility model has following advantage and effect with respect to prior art:
(1) the utility model can be selected adaptive algorithm according to disturbed condition, and algorithm is insensitive to weak signal, can suppress significantly strong narrow band interference, make the spread-spectrum signal filtering interfering that is interfered, reach the reception requirement, it is slow to compare existing LMS convergence of algorithm speed, the shortcoming of real-time difference, DSP digital signal processor of the present utility model uses frequency domain adaptive or time-domain adaptive technology, can reach the real-time requirement.
(2) the utility model is in real time signal to be carried out self-adaptive processing on frequency spectrum, so when existing a plurality of interference to exist, do not need increase equipment, be subjected under the situation that the general spread spectrum system of strong jamming can't communicate, the design of application the innovation can suppress to disturb still can carry out spread spectrum, adopting the utility model, is 10～20dB to the average supression degree of depth of a plurality of strong narrow interference, disturbs position error to be not more than the FFT frequency resolution.
(3) the utility model dynamic range is big, the processing accuracy height, and the insertion loss is little.
(4) the utility model down converted frequencies, input signal bandwidth, output signal speed, output signal word length and form can be adjusted as required, and good versatility and autgmentability are arranged.
(5) in the utility model, digital medium-frequency signal receives occasion simultaneously at multichannel, spuious index and signal to noise ratio snr index are better, to ADC require moderate, the particularly introducing of DDC able to programme, replace analog filtering with digital filtering, improved the flexibility of spread spectrum system and the selectivity of filter, and solved I, Q passage matching problem preferably.
(6) the utility model can be realized directly being connected with existing spread spectrum receiving equipment, need not change existing equipment.
Description of drawings
Fig. 1 is the syndeton schematic diagram of anti-intense arrow-band interference self-adaptive trap filter in spread spectrum system of the utility model spread spectrum system.
Fig. 2 is the surface structure schematic diagram of the anti-intense arrow-band interference self-adaptive trap filter of the utility model spread spectrum system.
Fig. 3 is the internal structure schematic diagram of the anti-intense arrow-band interference self-adaptive trap filter of the utility model spread spectrum system.
Fig. 4 is the workflow diagram of the anti-intense arrow-band interference self-adaptive trap filter of the utility model spread spectrum system.
Fig. 5, the 6th, the fundamental diagram of DSP digital signal processor shown in Figure 3.
Fig. 7～13rd, the circuit theory diagrams of the anti-intense arrow-band interference self-adaptive trap filter of the utility model spread spectrum system.
Embodiment
Below in conjunction with embodiment and accompanying drawing the utility model is described in further detail, but of the present utility model
Execution mode is not limited thereto.
Embodiment
As shown in Figure 1, in spread spectrum system, signal is received by broadband signal, through multichannel coupling, radio frequency processing, and multiply each other with local oscillator, obtain the 70MHz analog if signal, enter this spread spectrum system anti-intense arrow-band interference self-adaptive trap filter again, after it carries out intermediate frequency anti-aliasing filter, A/D conversion, Digital Down Convert, digital baseband processing etc. and handles in real time input signal, output signal then.
Fig. 2 is the surface structure signal of the anti-intense arrow-band interference self-adaptive trap filter of this spread spectrum system, as shown in Figure 2, and after energized 1, if working properly, the POWER indicator light will be bright, and the utility model is provided with two direct voltages, red light 2 is 3.3V, and green light 3 is 1.8V.70MHz analog intermediate frequency signal input 4, input be the band interference signal that radiofrequency signal obtains after down-conversion, after treatment, this trapper is exported from base-band digital output 5 signal with digital baseband form.This equipment also can be connected with host computer by DSP-JTAG port 6.
As shown in Figure 3, the anti-intense arrow-band interference self-adaptive trap filter of this spread spectrum system, comprise the anti-aliasing filter module, the A/D conversion module, the DDC Digital Down Converter Module, FIFO first-in first-out module, the DSP digital signal processor interconnects composition successively, and be connected with power module respectively, the DDC Digital Down Converter Module, FIFO first-in first-out module, the DSP digital signal processor is connected with the FPGA field programmable device simultaneously, the A/D conversion module, the DDC Digital Down Converter Module, the DSP digital signal processor, the FPGA field programmable device is connected with crystal oscillator respectively, the DSP digital signal processor also is connected with memory, comprise FLASH, SBSRAM (Synchronous Burst Static Random Access Memory, the synchronization burst static RAM (SRAM)), SDRAM (Synchronous Dynamic random access memory, synchronous dynamic ram) memory.
The DSP digital signal processor is a TMS320C6701 Floating-point DSP digital signal processor.Power module comprises that output voltage is the DC power supply of difference 5V, 3.3V, 2.5V and 1.8V, satisfies the need of work of each part in the trapper.
As shown in Figure 4, the anti-intense arrow-band interference self-adaptive trap filter of this spread spectrum system carries out the anti-interference adaptive course of work and is:
(1) receiving terminal of spread spectrum system is transformed to analog intermediate frequency (IF) signal of 70MHz with the RF radiofrequency signal, inputs to the anti-aliasing filter module;
(2) the outer unwanted signal of anti-aliasing filter module filtering band and it is inputed to the A/D conversion module;
(3) described A/D conversion module is to the analog signal sampling digitlization, and the analog if signal of 70MHz is transformed into digital medium-frequency signal, and with digital data transmission to the DDC Digital Down Converter Module;
(4) the DDC Digital Down Converter Module is finished Digital Down Convert, the digital medium-frequency signal sampling is downconverted to the zero carrier baseband signal, and conversion of signals is become I, Q double-channel signal, delivers to the DSP digital signal processor processes, for it provides data source;
(5) after the DSP digital signal processor is handled in real time to input signal, signal is exported.
When the DSP digital signal processor is handled in real time to input signal, can according to circumstances adopt the different disposal scheme:
As shown in Figure 5, adopt frequency domain adaptive trapper algorithm structure.Algorithm is expressed as follows:
With N the sampled value x (n, 1) of time domain, (n N) forms a frame to x (n, 2) Λ x, does N point fast Fourier (FFT) conversion then, obtains the frequency domain components X of one group of nearly orthogonal
1(n), X
2(n), Λ, X
N(n), each component is by the control of single order sef-adapting filter independently, thereby finished Adaptive Suppression on frequency domain.To a specific power W
k, the value of n+1 frame and n frame has following relation:
Wherein
e
k(n)＝X
k(n)-W
k(n)X
k(n)＝[1-W
k(n)X
k(n) (3-36)
With the following formula substitution, then the weights iterative formula can be expressed as again:
W
k(n+1)＝W
k(n)+u[1-W
k(n)]‖X
k(n)‖
2 (3-37)
At last, to [1-W
k(n)] X
k(n) Fourier transformation (IFFT) of inverting can obtain the repressed spread-spectrum signal of narrow band interference.
As shown in Figure 6, adopt time-domain adaptive trapper algorithm structure.Algorithm is expressed as follows:
If being input as of the k moment:
X(k)＝[r(k-1)，r(k-2)，Λ，r(k-N)]
T (2-1)
Corresponding adaptive filter coefficient is:
A(k)＝[a
1(k)，a
2(k)，Λ，a
N(k)]
T (2-2)
And the matrix that k preceding p input constantly constitutes is:
X
N，p(k)＝[X(k)，X(k-1)，Λ，X(k-p+1)]
T (2-3)
And remember that respectively D (k) and E (k) are a k preceding p desired output and a preceding p vector that error constituted constantly, that is:
D(k)＝[d(k)，d(k-1)，Λ，d(n-p+1)]
T＝[r(k)，r(k-1)，Λ，r(k-p+1)]
T (2-4)
E(k)＝[e(k)，e(k-1)，Λ，e(k-p+1)]
T
＝D(k)-X
N，p(k)×A(k) (2-5)
The right value update formula of algorithm is:
A (k+1)=A (k)+μ X
T N, p(k) E (k) (2-6) brings (2-6) into (2-5) and can get:
A(k+1)＝A(k)+μX
T N，p(k)E(k)
＝[I-μX
T N，p(k)×X
N，p(k)]A(k)+μX
T N，p(k)D(k) (2-7)
Time-domain adaptive trapper algorithm adopts and improves the LMS algorithm.This algorithm is in the process of upgrading filter coefficient, the current information of system and the information before the system have not only been used, and in right value update contrary without compute matrix, therefore not only can accelerate convergence rate, and reduce amount of calculation, so its corresponding convergence rate has had very big improvement.Because this algorithm comes from the LMS algorithm, when the input signal correlation was more weak, the algorithmic statement performance was not ideal, and is consuming time more, at this time can select frequency domain adaptive trapper algorithm, goes to solve the inhibition problem of narrow band interference.
Frequency domain adaptive trapper algorithm, time-domain adaptive trapper algorithm and existing linear algorithm, nonlinear algorithm compare:
When the pseudo-code cycle is 31, and spreading gain is 15dB.AR disturbs 34dB; Single-frequency is disturbed and is respectively 100kHz, 300kHz and 400kHz, and power is 20dB; The centre frequency of BPSK type narrow band interference is 200kHz, and bandwidth is 6.4kHz, and power is 20dB.Following table is that the error rate compares:
As can be seen from the above table, the employed algorithm of the utility model is better to the inhibition effect of many interference, time-domain adaptive trapper algorithm is in the anti-interference filter better performances to signal, but when the signal input is more weak, use frequency domain adaptive trapper algorithm, can improve processing speed, satisfy real-time processing requirements.
Be the circuit theory diagrams of A/D conversion module as shown in Figure 7.A/D conversion module AD6644 is a core of finishing the A/D digital to analog conversion, and analog signal after surface wave filter, after triode amplifies, is input to T4-1 from the input of SMA_CONN interface.T4-1 is that turn ratio is 1: 4 a transformer, and in the middle of coil a centre tap is arranged.(4,5,6) end is the few end of the number of turn in this circuit, and (1,2,3) end is the many ends of the number of turn.Behind T4-1, signal has become differential signal, is input to the analog differential input of AD6644.CY2308 is a clock buffer, the clock fan-out that it produces active crystal oscillator OSC_SQDIP.Its output becomes differential signal through T4-1, is input to AD6644, as the AD conversion clock of AD6644.
Be the circuit theory diagrams of DDC Digital Down Converter Module as shown in Figure 8.The input of DDC Digital Down Converter Module AD6620 is from the output of the A/D conversion module AD6644 of Fig. 7 (ADDDATA＜13-0 〉), its clock is from the CY2308 (AD6620CLK) of Fig. 7, its configuration is finished by FPGA field programmable device XC2S30, it is output as the I/Q two paths of signals, alternately from OUT＜15-0〉output, OUT＜15-0〉be connected with two FIFO first-in first-out module SN74ALV7804, ED＜31..0 is merged in the output of FIFO first-in first-out module then 〉.The input and output process of FIFO is finished by FPGA field programmable device XC2S30 control.
Be the circuit theory diagrams of DSP digital signal processor and memory as shown in Figure 9.TMS320C6701_PART is the part of DSP digital signal processor TMS320C6701 among the figure, and HY57V281620 is SDRAM, and CY7C1329 is SBSRAM, and SST39VF400A is FLASH.
Be the circuit theory diagrams of bus driver as shown in figure 10.Buffer SN74ALB16244 is with the address wire EA＜21-2 of DSP digital signal processor TMS320C6701 among Fig. 9〉cushion amplification, FANEA＜19-2〉be the address wire that drives each memory.ED＜31-0〉be data/address bus, the data terminal of memory in the connection layout 9, and be the synthetic ED＜31-0 of output of FIFO first-in first-out module among Fig. 8.ED＜31-0〉each line becomes DSPED＜31-0 behind resistance 〉, DSPED＜31-0〉be the data terminal of DSP digital signal processor TMS320C6701.
Be the circuit theory diagrams of data output interface as shown in figure 11.Buffer SN74CB3Q3245 is connected on the MCBSP port of DSP digital signal processor TMS320C6701, the output signal of TMS320C6701 is cushioned amplification, outwards export by MCBSPOUT, MCBSPOUT promptly is the externally port of output of this spread spectrum system anti-intense arrow-band interference self-adaptive trap filter.The TMS320C6701_PART of Chu Xianing is the part of DSP digital signal processor TMS320C6701 in the drawings.
Be the circuit theory diagrams of configuration interface as shown in figure 12.FPGA_JTAG is a jtag interface, be used for FPGA field programmable device XC2S30 is programmed, and XCF01S is the configuration PROM of FPGA field programmable device XC2S30.JTAG_HEADER is another jtag interface, promptly is the DSP-JTAG port on the profile panel, and it is the JTAG mouth that connects DSP digital signal processor TMS320C6701.TMS320C6701_PART is the part of DSP digital signal processor TMS320C6701 among the figure.
Be the circuit theory diagrams of power unit as shown in figure 13.PT6933 is the power unit of devices such as DSP digital signal processor, and it provides 3.3V and 1.8V stabilized voltage power supply.LT1l8 provides the stabilized voltage power supply of 2.5V.The general supply of whole design is from POWERHEADER, and it provides 5V D.C. regulated power supply.
As mentioned above, can realize the utility model preferably.
Claims (4)
1, a kind of anti-intense arrow-band interference self-adaptive trap filter of spread spectrum system, it is characterized in that: comprise the anti-aliasing filter module, the A/D conversion module, the DDC Digital Down Converter Module, FIFO first-in first-out module, the DSP digital signal processor interconnects composition successively, and be connected with power module respectively, described DDC Digital Down Converter Module, FIFO first-in first-out module, the DSP digital signal processor is connected with the FPGA field programmable device simultaneously, described A/D conversion module, the DDC Digital Down Converter Module, the DSP digital signal processor, the FPGA field programmable device is connected with crystal oscillator respectively, and described DSP digital signal processor also is connected with memory.
2, by the anti-intense arrow-band interference self-adaptive trap filter of the described a kind of spread spectrum system of claim 1, it is characterized in that: described DSP digital signal processor is a high-speed floating point DSP digital signal processor.
3, by the anti-intense arrow-band interference self-adaptive trap filter of the described a kind of spread spectrum system of claim 1, it is characterized in that: described memory comprises FLASH, SBSRAM, SDRAM memory.
4, by the anti-intense arrow-band interference self-adaptive trap filter of the described a kind of spread spectrum system of claim 1, it is characterized in that: described power module comprises that output voltage is the DC power supply of difference 5V, 3.3V, 2.5V and 1.8V.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104394109A (en) * | 2014-07-18 | 2015-03-04 | 中国人民解放军军械工程学院 | Adaptive denoising method of non-continuous communication signal under multi-interference condition |
| CN104459725A (en) * | 2014-11-24 | 2015-03-25 | 中国电子科技集团公司第二十研究所 | Satellite signal simulation generator applied to BeiDou communication system |
-
2005
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104394109A (en) * | 2014-07-18 | 2015-03-04 | 中国人民解放军军械工程学院 | Adaptive denoising method of non-continuous communication signal under multi-interference condition |
| CN104394109B (en) * | 2014-07-18 | 2015-08-26 | 中国人民解放军军械工程学院 | A kind of discontinuous signal of communication self-adapted noise elimination method under many disturbed conditions |
| CN104459725A (en) * | 2014-11-24 | 2015-03-25 | 中国电子科技集团公司第二十研究所 | Satellite signal simulation generator applied to BeiDou communication system |
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Granted publication date: 20070509 Termination date: 20100822 |