CN2893964Y - Module with compatible interface - Google Patents

Abstract

The utility model is a template with compatible bus interface, on which connector is fixed to connect external template and used for bus structure, and templates are replaceable to each other. Connector on the template is designed for bus structure, thereby being able to be compatible with different microprocessors, microcontrollers and digital signal processors so that their cards and expansion sub-board with periphery function are compatible and replaceable to each other, which has the advantages of expansible function, economized cost, convenient upgrading, benefiting to teaching demonstration and scientific research and development.

Description

Template with compatibility interface

Technical field

The utility model relates to a kind of connector, be particularly related to a kind of template with compatibility interface, described compatibility interface can compatible various microprocessors, microcontroller and digital signal processor product, making various microprocessors, microcontroller and digital signal processor integrated circuit board and peripheral function expand daughter board can be compatible, be configured exchange flexibly, help the function expansion, save cost, make things convenient for upgrading and teaching demonstration and scientific research and development.

Background technology

In recent years, along with development of electronic technology, electronic product more and more is tending towards modularization, with versatility, applicability and the substituting needs that satisfy product.

Each template is provided with the electronic device of realizing this functions of modules, as CPU, memory etc., also be provided with the interface (connector) of these template input and output, these interfaces generally include data wire, address wire, control line, read-write, chip selection signal, memory strobe signals, interrupt signal, reset signal, various power supply and ground end points, perhaps so that provide operational environment and input, the output signal of telecommunication for the electronic device on the template.

But present standard form interface can not satisfy versatility, applicability and the substituting needs of product, so these interfaces normally design for certain device, can not be compatible.

Summary of the invention

The purpose of this utility model provides a kind of template with compatibility interface, makes between each template intercommunication to use mutually.

Above-mentioned purpose of the present utility model is achieved in that a kind of template with compatibility interface, it is characterized in that: be fixed with the connector that connects outer template on template, this connector is the bus structures connector.

Because template connector of the present utility model is designed to the bus structures connector, thereby can compatible various microprocessors, microcontroller and digital signal processor product, making various microprocessors, microcontroller and digital signal processor integrated circuit board and peripheral function expand daughter board can be compatible, is configured exchange flexibly.

In addition, the data wire pin of bus structures connector of the present utility model has 2 ⁿThe preliminary data wire pin, adapting to the processor of different abilities, n be more than or equal to or greater than 3 integer, for example, for the processor of present 8 data wires, preliminary data wire pin of the present utility model is at least 8.

Wherein, described bus structures connector has the inserting groove and the connection-peg of intercommunication, and wherein inserting groove is fixed on the template one side, and connection-peg is fixed on the another side of template.Be convenient to the template interconnection like this.

Wherein, described bus structures connector comprises: first connector of extended address, data/address bus and control bus, and second connector of expanding peripherals signal.

Wherein, described bus structures connector also comprises: expand the 3rd connector that first connector and second connector do not have the residue cpu signal of expansion.

Wherein, described control bus comprises reading writing signal line and chip selection signal line.

Wherein, the residue cpu signal comprises: the signal of communication between AD input, liquid crystal, serial ports and expansion daughter board.

Wherein, the diverse location on template is provided with first connector, second connector and the 3rd connector respectively.

Wherein, the diverse location on template is provided with first connector and second connector respectively.

Obviously, the utlity model has following technique effect:

1) because the template connector is designed to the bus structures connector, thereby can compatible various microprocessors, microcontroller and digital signal processor product, making various microprocessors, microcontroller and digital signal processor integrated circuit board and peripheral function expand daughter board can be compatible, is configured exchange flexibly; Help the function expansion, save cost, make things convenient for upgrading and teaching demonstration and scientific research and development.

2), be convenient to each template interconnection, thereby help reducing taking up room of electronic equipment because described bus structures connector has the inserting groove and the connection-peg of intercommunication.

Below in conjunction with accompanying drawing the utility model is elaborated.

Description of drawings

Fig. 1 is the stereogram of the template of first compatibility interface of the present utility model;

Fig. 2 be Fig. 1 A to plane graph;

Fig. 3 is the schematic diagram that the pin of the J1 connector of extended address of the present utility model, data/address bus and control bus concerns;

Fig. 4 is the schematic diagram that the pin of the J2 connector of expanding peripherals signal of the present utility model concerns;

Fig. 5 is the schematic diagram that the pin of the connector of expansion of the present utility model J1, the J2 cpu signal that not have expansion concerns;

Fig. 6 is the stereogram of the template of second kind of compatibility interface of the present utility model;

Fig. 7 be Fig. 6 B to plane graph;

Fig. 8 is the stereogram of the template of the third compatibility interface of the present utility model;

Fig. 9 be Fig. 8 C to plane graph.

Embodiment

Template referring to first compatibility interface of the present utility model shown in Figure 1, be provided with respectively on template 4: the connector 44 (J2 connector) of the connector 43 of extended address, data/address bus and control bus (J1 connector), expanding peripherals signal and expansion J1, J2 do not have the connector 45 (the J3 connector also can be called the connector that expansion remains cpu signal) of the cpu signal of expansion.Here the most key is that connector is the bus structures connector.The inventor recognizes, the connector of template is designed to the bus structures connector can compatible various Digital Signal Processing products, makes various digital signal panel cards and the peripheral function expansion daughter board can be compatible, is configured exchange flexibly.

Simultaneously, the utility model also is arranged to the data wire pin of bus structures connector, has 2 ⁿThe preliminary data wire pin, to adapt to the processor of different abilities, wherein n be more than or equal to or greater than 3 integer, for example, processor for present 8 data wires, preliminary data wire pin of the present utility model is at least 8, certainly can also be as required, and the preliminary data wire pin is set to 16 or 32 ...

Wherein, as can be seen from Figure 1, described bus structures connector has the inserting groove and the connection-peg of intercommunication, and wherein inserting groove is fixed on the template one side, and connection-peg is fixed on the another side of template.Be convenient to the template interconnection like this, thereby can reduce taking up room of template.

In addition, also be provided with on the template not shown with lower member:

4 of-location holes;

Signal input and output connectors such as the JTAG mouth of-DSP, the JTAG mouth of CPLD, UART mouth, spread signal interface, BNC connector are placed on the horizontal left side of plate; DSP JTAG mouth, CPLD JTAG mouth and spread signal plug-in unit are selected double looper for use, standard I DC encapsulation; The UART connector is selected the looper interface for use, standard DB9/M encapsulation.BNC connector is selected curved joint for use, the BNC encapsulation.More than all connectors part of stretching out pcb board be of a size of 7mm;

-toggle switch, the straight cutting switch of preferentially selecting for use side to dial is placed on the horizontal right side of plate, near the edge of plate;

-outlet, CAN bus interface can be placed on vertical both sides of plate, can not stretch out outside the pcb board; Outlet POW-9 encapsulation, the encapsulation of CAN bus socket screw terminal formula;

-under the situation of wiring and layout needs, the JTAG mouth of DSP, the JTAG mouth of CPLD also can be placed on the horizontal right side of plate or downside longitudinally.

Fig. 3 shows J1 connector of the present utility model, the i.e. connector of extended address, data/address bus and read-write, chip selection signal.The implication of this each pin of J1 connector that table 1 describes in detail.

Table 1

Sequence number	Code name	Implication	IO	Remarks
					1	+5V	+ 5V power supply
2	+5V	+ 5V power supply
					3	A19|XA21	Address wire	O
4	A18|XA20	Address wire	O
					5	A17|XA19	Address wire	O
6	A16|XA18	Address wire	O
					7	A15|XA17	Address wire	O
8	A14|XA16	Address wire	O
					Sequence number	Code name	Implication	IO	Remarks
9	A13|XA15	Address wire	O
					10	A12|XA14	Address wire	O
11	GND	Ground
					12	GND	Ground
13	A11|XA13	Address wire	O
					14	A10|XA12	Address wire	O
15	A09|XA11	Address wire	O
					16	A08|XA10	Address wire	O
17	A07|XA09	Address wire	O
					18	A06|XA08	Address wire	O
19	A05|XA07	Address wire	O
					20	A04|XA06	Address wire	O
21	+5V	+ 5V power supply
					22	+5V	+ 5V power supply
23	A03|XA05	Address wire	O
					24	A02|XA04	Address wire	O
25	A01|XA03	Address wire	O
					26	A00|XA02	Address wire	O
27	A21|BE3	Address wire	O
					28	A20|BE2	Address wire	O
29	NC|BE1	Address wire	O
					30	NC|BE0	Address wire	O
31	GND	Ground
					32	GND	Ground
33	D31	Data wire	IO
					34	D30	Data wire	IO
35	D29	Data wire	IO
					36	D28	Data wire	IO
37	D27	Data wire	IO
					38	D26	Data wire	IO
39	D25	Data wire	IO

Sequence number	Code name	Implication	IO	Remarks
					40	D24	Data wire	IO
41	+3.3V	+ 3.3V power supply
					42	+3.3V	+ 3.3V power supply
43	D23	Data wire	IO
					44	D22	Data wire	IO
45	D21	Data wire	IO
					46	D20	Data wire	IO
47	D19	Data wire	IO
					48	D18	Data wire	IO
49	D17	Data wire	IO
					50	D16	Data wire	IO
51	GND	Ground
					52	GND	Ground
53	D15	Data wire	IO
					54	D14	Data wire	IO
55	D13	Data wire	IO
					56	D12	Data wire	IO
57	D11	Data wire	IO
					58	D10	Data wire	IO
59	D9	Data wire	IO
					60	D8	Data wire	IO
61	GND	Ground
					62	GND	Ground
63	D7	Data wire	IO
					64	D6	Data wire	IO
65	D5	Data wire	IO
					66	D4	Data wire	IO
67	D3	Data wire	IO
					68	D2	Data wire	IO
69	D1	Data wire	IO
					70	D0	Data wire	IO
Sequence number	Code name	Implication	IO	Remarks
					71	GND	Ground
72	GND	Ground
					73	RD	Read signal	O	2X、6X、ARM：＝RD，5X：＝NOT R/W
74	WE	Write signal	O	2X、6X、ARM：＝WE，5X：＝R/W
					75	OE	Enable signal	O	6X、ARM：＝OE，2X：＝RD，5X：＝NOT R/W
76	RDY	Be ready to signal	I	The READY signal of outside input is connected to the READY pin of CPU
					77	MSTRB	Memory strobe signals	O	2X：＝STRB，5X：＝MSTRB，6X：＝NC

78	CS0	Chip selection signal 0	O	2X、5X：IO 0X000～0X1FFF 6X：CE2 0XA0000000～0XA0001FFF
					79	GND	Ground
80	GND	Ground

Illustrate:

1) address wire: 5X---A0～A19 receives 26～3 corresponding pin; A20 receives 28 pin, A21 receives 27 pin; 30 pin, 29 pin are unsettled

2X---A0～A19 receives 26～3 corresponding pin; A20 receives 28 pin, A21 receives 27 pin; 30 pin, 29 pin are unsettled

6X---A2～A21 receives 26～3 corresponding pin; BE2 receives 28 pin, BE3 receives 27 pin; BE0 connects 30 pin, BE1 connects 29 pin

ARM---CPU has connecting by the 5X processor of A0, A1 address wire, does not have the high address line that does not have by 6X processor connection processing device of A0, A1 address wire unsettled.

Expansion board---useless to 30 pin (BE0), 29 pin (BE1), 29 pin, 30 pin are unsettled

2) data wire: the high position data line that processor does not have is unsettled

3) CSO: the chip selection signal of daughter board is given in expansion, and extension CPU does not have the chip select address of use.

Arm processor---CSO is connected to the chip selection signal that CPU does not have use

4) if this CPU of signal of J1 expansion does not have this type of signal (as MSTRB), then corresponding pin is not expanded, and is unsettled, can not be other cpu signal or expansion board signal extension to this pin.

Fig. 4 shows J2 connector 44 of the present utility model, that is, and and the implication of this each pin of J2 connector that the connector of expanding peripherals signal, table 2 describe in detail.

Table 2

Sequence number	Code name	Implication	IO	Remarks
					1	+12V	+ 12V power supply
2	-12V	-12V power supply
					3	GND	Ground
4	GND	Ground
					5	+5V	+ 5V power supply
6	+5V	+ 5V power supply
					7	GND	Ground
8	GND	Ground
					9	+5V	+ 5V power supply
Sequence number	Code name	Implication	IO	Remarks
					10	+5V	+ 5V power supply

11	CPU1	CPU kind index signal	O	See explanation
					12	HOLD	The external bus inhibit signal	I
13	CPU2	CPU kind index signal	O	See explanation
					14	HOLDA	Bus keeps response signal	O
15	CPU3	CPU kind index signal	O	See explanation
					16	BUSREQ	The external bus request signal	O
17	CPU4	CPU kind index signal	O	See explanation
					18	CPU5	CPU kind index signal	O	See explanation
19	+3.3V	+ 3.3V power supply
					20	+3.3V	+ 3.3V power supply
21	CLKX0	McBSP0 carry-out bit clock	IO
					22	CLKS0	The outside input clock of McBSP0	I
23	FSX0	Clock is detectd in McBSP0 output	IO
					24	DX0	The McBSP0 dateout	O
25	GND	Ground
					26	GND	Ground
27	CLKR0	McBSP0 imports bit clock	IO
					28	NC	Empty pin
29	FSR0	Clock is detectd in the McBSP0 input	IO
					30	DR0	McBSP0 imports data	I
31	GND	Ground
					32	GND	Ground
33	CLKX1	McBSP1 carry-out bit clock	IO
					34	CLKS1	The outside input clock of McBSP1	I
35	FSX1	Clock is detectd in McBSP1 output	IO

36	DX1	The McBSP1 dateout	O
					37	GND	Ground
38	GND	Ground
					39	CLKR1	McBSP1 imports bit clock	IO
40	NC	Empty pin
					41	FSR1	Clock is detectd in the McBSP1 input	IO
42	DR1	McBSP1 imports data	I
					Sequence number	Code name	Implication	IO	Remarks
43	GND	Ground
					44	GND	Ground
45	TOUT0	Timer output 0	O
					46	TINP0	Timer input 0	I
47	NMI	Maskable does not interrupt	I
					48	INT1/EINT5	Interrupt	I	The interrupt signal of outside input is connected to the interruption of CPU: 5X-INT1; 6X:EINT5; 2X:INT2
49	XF/TOUT1	1 output of O/ timer	O	2X、5X：＝XF，6X：＝TOUT1
					50	BIO/TINP1	1 input of IN/ timer	I	2X、5X：BIO，6X：TINP1
51	GND	Ground
					52	GND	Ground
53	INT0/EINT4	Interrupt	I	The interrupt signal of outside input is connected to the interruption of CPU: 5X-INT0; 6X:EINT4; 2X:INT1
					54	IACK	The interrupt response signal	O
55	NC	Empty pin
					56	CS2	Chip selection signal 2	O	2X, 5X:IO space 0X4000～0X7FFF, 6X:CE3 0XB0000000～0XB0003FFF
57	MSC	State is finished signal	O
					58	IAQ	The address acquired signal	O
59	RESET	Reset signal	O
					60	DBINT/PD	The indication of daughter board interruption/power supply
61	GND	Ground
					62	GND	Ground
63	CNTL1	Daughter board control signal 1	O	CPU board sends to the control signal 1 of daughter board
					64	CNTL0	Daughter board control signal 0	O	CPU board sends to the control signal 0 of daughter board
65	STAT1	Daughter board status signal 1	I	The CPU board status signal 1 that daughter board sends to
					66	STAT0	Daughter board status signal 0	I	The CPU board status signal 0 that daughter board sends to
67	INT2/EINT6	Interrupt	I	The interrupt signal of outside input is connected to the interruption of CPU: 5X:INT2; 6X:EINT6; 2X:PDPINTA

68	INT3/EINT7	Interrupt	I	The interrupt signal of outside input is connected to the interruption of CPU: 5X:INT2; 6X:EINT7; 2X:PDPINTB
					Sequence number	Code name	Implication	IO	Remarks
69	CS3	Chip selection signal 3	O	2X, 5X: data space 0X8000～0XFFFF, 6X:CE3 0XB0004000～0XB000BFFF
					70	CS1	Chip selection signal 1	O	2X, 5X:IO space 0X2000～0X3FFF, 6X:CE2 0XA0002000～0XA0003FFF
71	DMAC3	The dma state signal	O
					72	DMAC2	The dma state signal	O
73	DMAC1	The dma state signal	O
					74	DMAC0	The dma state signal	O
75	DB_DET	The daughter board detection signal	I	Daughter board inputs to the signal of CPU board, and is effectively low.Whether this signal is used for detecting has daughter board to be inserted on the CPU board
					76	GND	Ground
77	GND	Ground
					78	CLKOUT	Clock	O	The clock output signal of CPU
79	GND	Ground
					80	GND	Ground

Illustrate: 1) ARM CPU has the signal of IIS bus to be connected to the following corresponding pin of J2:

The pin sequence number of J2	The signal of IIS
		35	IISLRCK
39	IISCLK
		36	IISDO
42	IISDI

2) ARM CPU has the signal of SIO bus to be connected to the following corresponding pin of J2:

The pin sequence number of J2	The signal of SIO
		21	SIOCLK
23	SIORDY
		24	SIOTXD
30	SIORXD

3) if the signal CPU board of J2 expansion is used, then can not expand; Different types of CPU board, the signal of identical function:, expand on the pin of the function that has defined as (McBSP serial ports), if this CPU does not have this type of signal (as DMA), then corresponding pin is not expanded, and is unsettled, can not be other cpu signal or expansion board signal extension to this pin.

4) 75 pin are signals that CPU board judges whether the daughter board expansion, ground connection on daughter board

5) CPU1, CPU2, CPU3, CPU4 are used to refer to CPU board kind signal, stipulate as follows:

" 1 ": representative is by moving high level on the 10K resistance

" 0 ": represent ground connection

Fig. 5 shows the utility model J3 connector, promptly expands the connector that J1, J2 do not have the cpu signal of expansion, as the communication signal between AD input, liquid crystal, serial ports etc. and expansion daughter board.The implication of this each pin of J3 connector that table 3 describes in detail.

Table 3

Sequence number	Code name	Implication	IO	Remarks
					1	+5V	+ 5V power supply
2	+5V	+ 5V power supply
					3	AIN0	Analog input 0	I
4	AIN1	Analog input 1	I
					5	AIN2	Analog input 2	I
6	AIN3	Analog input 3	I
					7	AIN4	Analog input 4	I
Sequence number	Code name	Implication	IO	Remarks
					8	AIN5	Analog input 5	I

9	AREFB	The analog input negative reference voltage	I
					10	AREFT	The analog input reference voltage	I
11	AVCOM	Analog input reference voltage common port	I
					12	TOUT2	Timer output 2	O
13	TOUT3	Timer output 3	O
					14	TOUT4	Timer output 4	O
15	ExINT4	External interrupt 4	I
					16	ExINT5	External interrupt 5	I
17	ExINT6	External interrupt 6	I
					18	ExINT7	External interrupt 7	I
19	nGCS4	The sheet choosing	O
					20	nGCS5	The sheet choosing	O
21	nGCS6	The sheet choosing	O
					22	nGCS7	The sheet choosing	O
23	nWBE0	Write byte and enable 0	O
					24	nWBE1	Write byte and enable 1	O
25	nWBE2	Write byte and enable 2	O
					26	nWBE3	Write byte and enable 3	O
27	IO0	Universal I/O port	IO
					28	IO1	Universal I/O port	IO
29	IO2	Universal I/O port	IO
					30	IO3	Universal I/O port	IO
31	IICSCL	The iic bus clock	O
					32	IICSDA	The iic bus data	IO
33	RXD1	Serial ports receives data	I
					34	TXD1	Serial ports sends data	O
35	nCTS1	Serial ports is removed received signal	O
					Sequence number	Code name	Implication	IO	Remarks
36	NRTS1	The serial ports request to send signal	O
					37	SDDAT0	SD card data 0	IO
38	SDDAT1	SD card data 1	IO
					39	SDDAT2	SD card data 2	IO
40	SDDAT3	SD card data 3	IO

41	SDCLK	SD card clock signal	O
					42	SDCMD	SD card command signal	O
43	SYS	Cpu signal	IO
					44	SYS	Cpu signal	IO
45	SYS	Cpu signal	IO
					46	CODCLK	The IIS bus clock signal	O
47	VR0	Very color LCD signal VR0	O
					48	VR1	Very color LCD signal VR1	O
49	VR2	Very color LCD signal VR2	O
					50	VR3	Very color LCD signal VR3	O
51	VR4	Very color LCD signal VR4	O
					52	VG0	Very color LCD signal VG0	O
53	VG1	Very color LCD signal VG1	O
					54	VG2	Very color LCD signal VG2	O
55	VG3	Very color LCD signal VG3	O
					56	VG4	Very color LCD signal VG4	O
					Sequence number	Code name	Implication	IO	Remarks
57	VG5	Very color LCD signal VG5	O
					58	VB0	Very color LCD signal VB0	O
59	VB1	Very color LCD signal VB1	O
					60	VB2	Very color LCD signal VB2	O
61	VB3	Very color LCD signal VB3	O

62	VB4	Very color LCD signal VB4	O
					63	XN	Touch screen signal XN	I
64	YN	Touch screen signal YN	I
					65	YP	Touch screen signal YP	I
66	XP	Touch screen signal XP	I
					67	VM	The liquid crystal voltage control signal	I
68	VFRAME	Liquid crystal hardwood clock	O
					69	VLINE	Liquid crystal line clock	O
70	VCLK	The liquid crystal bit clock	O
					71	VD0	Liquid crystal data 0	O
72	VD1	Liquid crystal data 1	O
					73	VD2	Liquid crystal data 2	O
74	VD3	Liquid crystal data 3	O
					75	VD4	Liquid crystal data 4	O
76	VD5	Liquid crystal data 5	O
					77	VD6	Liquid crystal data 6	O
78	VD7	Liquid crystal data 7	O
					79	GND	Ground
80	GND	Ground

Illustrate:

1, the spread signal of CPU identical type preferentially expands to J1, J2, and J3 expands remaining cpu signal.The spread signal of CPU:

● AD input signal: the AD unit that inputs to CPU

● interrupt: expand to remaining interrupt signal behind the J2

● timer output: expand to remaining timer output signal behind the J2

● sheet choosing: expand to remaining chip selection signal behind J1, the J2

● write byte and enable: write the byte enable signal

● the DMA:DMA control signal

● IO: universal I signal

● the IIC:IIC bus signals

● UART: serial communication signal

● LCD: liquid crystal control and data signal

● SYS: do not have the cpu signal of appointment, the cpu signal that does not have in the above definition is expanded on the SYS pin, different types of CPU defines voluntarily, but the CPU board of identical type is consistent.

2, the signal between the expansion board

Communication signal between the expansion board

USER: represent the signaling interface between the expansion board, the expansion board except CPU board can link to each other with other expansion board at " USER " pin spread signal.

● the ADn/USER:AD input signal

● the Dan/USER:DA output signal

● the IO/USER:IO signal

● USER: undefined expansion board signal, definition voluntarily

If the signal CPU board of 3 J3 expansion is used, then can not expand; Different types of CPU board, the signal of identical function:, expand on the pin of the function that has defined as (UART serial ports), if this CPU does not have this type of signal (as VLINE), then corresponding pin is not expanded, and is unsettled, can not be other cpu signal or expansion board signal extension to this pin.

Fig. 6 shows template 2 structures of second kind of compatibility interface of the present utility model, Fig. 7 be Fig. 6 B to plane graph.As shown in the figure, template 2 is provided with connector 21 and connector 22, and these two connectors are J1, J2 connector.Wherein, as can be seen from Figure 6, the bus structures connector of this template also has the inserting groove and the connection-peg of intercommunication, and wherein inserting groove is fixed on the template one side, and connection-peg is fixed on the another side of template.Be convenient to the template interconnection like this, thereby can reduce taking up room of template.

Fig. 8 shows the stereogram of the template 3 of the third compatibility interface of the present utility model, Fig. 9 be Fig. 8 C to plane graph.As shown in the figure, template 3 is provided with connector 37 and connector 36, and these two connectors are J1, J2 connector.As can be seen from Figure 8, the bus structures connector of this template also has the inserting groove and the connection-peg of intercommunication, and wherein inserting groove is fixed on the template one side, and connection-peg is fixed on the another side of template.Be convenient to the template interconnection like this, thereby can reduce taking up room of template.

Enumerate the operable two kinds of buses of the utility model (connector) below again, wherein, a kind of bus is the E-PLAY bus, and a kind of bus is the E-LAB bus.

The E-PLAY bus

1, physical characteristic: respectively arrange the double pin of a row in the both sides up and down of module, double pin is the form of pin under the last hole, makes things convenient for module to overlap up and down.The spacing of double pin is 2.54mm, and last row is 60P, and following row is 70P.The right side is 40P.(position, the attribute specification of the profile of module and planning device are seen accompanying drawing)

2, the kind of holding wire: SPI (8), IIC (2), IIS (5), UART (2), T/C (2), EXINT (5), ANOLOGIN (8), ANOLOGOUT (2), VREF (2), PWM (8), GIO (16), D (16), A (16), CS (8), WR (1), RD (1), WAIT (1), RSTOUT (1) ,/R/S/T/O/U/T (1), expansion (12), LCD (28), touch-screen (4), MCBSP (16) and part keep siding about 160 lines altogether.

Designing requirement:

1. when designing CPU board, have functions such as serial ports (or global functional serial port), USB, JTAG, CAN as CPU or wherein during a certain function, to preferentially arrange serial ports DB9 (hole in the left side of module as far as possible, intersect), interfaces such as NET, JTAG, USB and CAN (over level conversion and isolation drive) interface are arranged in the both sides of PORTA.When not having the NET functional circuit on the plate, USB interface is moved to the position of NET interface.

2.CPU to have at least on the plate simple and easy serial ports, USB (from) each one the tunnel, CPU does not have function, expand on CPU board.

3. when the design CPU board,, when universal I is enough, can simulate one group of SPI interface, one group of IIC interface and one group of simple and easy serial ports by following sequencing with universal I if CPU does not have serial ports, SPI interface or IIC interface.

4. in design during CPU board, if CPU does not have the outer extension memory bus interface, when universal I is enough preferential with universal I analog D 0-D7, A0-A3, CS0-CS3 ,/W/R ,/R/D.When if universal I is not enough, can an analog D 0-D7 (D0-D3), A0-A2, CS0-CS1 ,/W/R ,/R/D.

5. occupied holding wire is not guided PORTA, B, C again on CPU board.

6. design is during CPU board, when CPU has the TFT liquid-crystal controller, and when not having touch screen function, expand touch screen function on CPU board and links to each other with interface.

7. CPU board no matter, or interface board, the scope of all analog signals is 0--+2.5V.

8. all selector switches of using (wire jumper) are preferentially selected wire jumper for use, are the Surface Mount switch secondly.

9.CPU plate does not take spread signal line (interface EIO0-EIO9, interface board analog signal output 0--1).

10. the holding wire of not using on the interface board is unsettled, does not link to each other with power supply or ground.

11. digitally DGND links to each other with the GND of power interface by 0 Europe resistance near power interface on the CPU board with simulation ground AGND.

12. the interface of using on the plate (PORT A, B, C and JTAG) pin pad is external diameter 62mil, aperture 35mil; The pin pad of power interface is external diameter 160mil, aperture 60mil.

The E-PLAY16 bus comprises: PORT A interface, and the PORT B interface, PORT C interface, and JIAG interface and power interface define these interfaces below respectively:

The PORTA interface definition

Numbering	Definition	Remarks
				1	+ 5V	Digital power, no matter CPU board, or interface board, all digital powers are all from here or conversion thus.
2	+ 5V
		3	DGND	Digitally, on CPU board, only the resistance by 0 Europe links to each other with power supply ground near power supply.
4	DGMD
		5	D0/IO0			Bidirectional data line in the bus, link to each other with the data wire of cpu chip after will driving by 16245 on the CPU board, 16245 will and generate total address control signal by CS0---CS7 decoding by RD is controlled again.To guarantee that when the design interface plate its data wire is high-impedance state at one's leisure, otherwise must the adjunction buffer circuit.The data wire of not using can be unsettled.	Bus interface, input, output are all the 5V Transistor-Transistor Logic level, when the chip level is not inconsistent therewith, must be through level conversion.
6	D1/IO1
		7	D2/IO2
8	D3/IO3
		9	D4/IO4
10	D5/IO5
		11	D6/IO6
12	D7/IO7
		13	D8
14	D9
		15	D10
16	D11
		17	D12
18	D13
		19	D14
20	D15
		21	A0/IO8	Address wire in the bus, CPU board output, after will driving by 16244 on the CPU plate, link to each other with interface pin again, on the interface board not the time spent unsettled.
22	A1/IO9
		23	A3/IO10
24	A3/IO11
		25	A4
26	A5
		27	A6
28	A7
		29	A8
30	A9
		31	A10
32	A11
		33	A12
34	A13
		35	A14
36	A15
		37	CS0/IO12		The chip selection signal line, CPU board output, the interface board input, low level is effective, during the design CPU board, no pin is unsettled.And when the design interface plate, select 1 switch (wire jumper) to select by 8.
38	CS1/IO13
		39	CS2/IO14
40	CS3/IO15
		41	CS4
42	CS5

43	CS6
					44	CS7
45	/ W/R/IO16						CPU board output, the interface board input, write signal is effectively low
		46	/ R/D/IO17		CPU board output, the interface board input, read signal is effectively low
47	/ W/A/I/T						The CPU board input, interface board output, the request of waiting for is effectively low
		48	RSROUT		CPU board output, the interface board input, it is effectively high to reset				The 5V Transistor-Transistor Logic level
49	/ R/S/T/O/U/T			CPU board output, the interface board input, it is effectively low to reset
		50	EXINT0			The external interrupt request signal, the 5VTTL level, the CPU board input, interface board output, low level is effective, and on CPU board, the interrupt line of not using will preferentially use the interrupt line of low numbering to fill, if CPU is the 3V device, must isolate by 244/245.On interface board, all interrupt signal lines of using will select 1 switch (wire jumper) selection with 5.
51	EXINT1
		52	EXINT2
53	EXINT3
		54	EXINT4
55	T0out/C0in/CAP0			Timer output/counter input/seizure pulse input, the 5V Transistor-Transistor Logic level, when on CPU board, having only one the tunnel, the second the tunnel will fill with the first via, will use on user's plate by switch to link to each other.
		56	T1out/C1in/CAP1
57	SPI_NSS0/BFSX0						The SPI chip selection signal	Spi bus, the 5V Transistor-Transistor Logic level, cpu function pin (master), when the design CPU board, if spi bus is arranged, should preferentially use this group, unsettled when of no use.Interface board can only do from.Multiplexing MCBSP holding wire.
		58	SPI_CLK0/BCLKX0	The SPI clock
59	SPI_MISO0/BDR0				The master goes into from going out
		60	SPI_MOSI0/BDX0	The master goes out from going into

The PORTB interface definition

13	Keep	Undefined temporarily
					14	Keep
15	Keep
					16	BFSR0	The MCBSP holding wire
17	BCLKR0
		18	BFSR1
19	BCLKR1
		20	IIS_LRCK/BFSX0	IIS channel selecting clock	Multiplexing MCBSP holding wire	The IIS interface, the cpu function pin.The time spent is not unsettled.
21	IIS_SDI/BDR0						The input of IIS data
		22	IIS_SDO/BDX0	The output of IIS data
23	IIS_SCLK/BCLK XO						The IIS clock
		24	IIS_CDCLK	IIS encoding and decoding clock
25	AGIO0				A organizes GIO, the expansion IO of cpu function pin or CPU board.To preferentially use.When being taken in deficiency, CPU board to preferentially use low numbering holding wire to fill.When the design interface plate, when IO was less than 4, each IO will select 1 switch (wire jumper) to select by 4; But will be during more than 4 with 244 or 273 by bus expansion IO, in order to avoid conflict with other interface board.
		26	AGIO1
27	AGIO2
		28	AGIO3
29	AGIO4
		30	AGIO5
31	AGIO6
		32	AGIO7
33	BGIO0			B organizes GIO, the expansion IO of cpu function pin or CPU board.Will organize the corresponding signal line with A and fill when CPU board is taken in deficiency, order is organized with A.On interface board, organize with A.
		34	BGIO1
35	BGIO2
		36	BGIO6
37	BGIO4
		38	BGIO5
39	BGIO6
		40	BGIO7

Numbering	Definition	Remarks
				41	PWMA0	The PWM function output of CPU, on CPU board, the preferential holding wire of arranging low numbering, the holding wire of not using will be filled from low to high successively with existing holding wire, on interface board, each road of user side all will select 1 switch (wire jumper) to select by 4.
42	PWMA1
		43	PWMA2
44	PWMA3
		45	PWMB0	The PWM function output of CPU is on CPU board, if the holding wire deficiency will be filled with label from low to high with the A group.Design on interface board is organized with A.When the design CPU board, if the PWM of CPU divides into groups, and a certain group PWM number should be with two groups of unified this group signals of arranging of A, B during greater than 4.
46	PWMB1
		47	PWMB2
48	PWMB3
		49	EGIO0			Interface board IO is produced by the interface board expansion, can not take on the CPU board, must be unsettled.Interface board can use.
50	EGIO1
		51	EGIO2
52	EGIO3
		53	EGIO4
54	EGIO5
		55	EGIO6
56	EGIO7
		57	EGIO8
58	EGIO9
		59	AGND	Simulation ground is in order to shielding input analog signal	When PCB layout; Separate cabling is concentrated in all analog inputs, covers copper by AGND.
60	AINA0					Analog signal, on CPU, be input, will preferentially arrange the holding wire of low numbering during design, the idle signal line will be filled from low to high successively with existing holding wire.On user's plate, do when output and will select 1 switch (wire jumper) to select by 4, can directly connect when doing input.
		61	AINA1
62	AINA2
		63	AINA3
64	AINB0			Analog signal, on CPU, be input, will organize holding wire with A when idle fills in proper order, will do when output on interface board will select 1 switch (wire jumper) to select by 4, can directly connect when doing input.
		65	AINB1
66	AINB2
		67	AIN7B3
68	AGND					Simulation ground is in order to shielding input analog signal
		69	-12V	The negative supply of analog circuit.
70	-12V

The definition of PORT C interface

Numbering	Definition		Remarks
					1	VREFout	The output of CPU board reference voltage	The time spent is not unsettled.
2	VREFin	The input of CPU board reference voltage
			3	AOUT0	CPU analog signal output 0	When having only one the tunnel on CPU board, preferentially use AOUT0, AOUT1 is unsettled.
4	AOUT1	CPU analog signal output 1
			5	EAOUT0	Interface board analog signal output 0			Produce by the interface board expansion, can not take on the CPU board, must be unsettled.Interface board can use.
6	EAOUT1	Interface board analog signal output 1
			7	XPON	Touch-screen X-axis P	On CPU board, the time spent is not unsettled.Will note during use: this holding wire judges whether to need to increase associated driver circuitry directly by touch-screen output.On interface board.Can directly link to each other with touch-screen (4 line).
8	YPON	Touch-screen Y-axis P
			9	XMON	Touch-screen X-axis M
10	YMON	Touch-screen Y-axis M
			11	R00/CAP2	The liquid crystal aanalogvoltage is imported 0 liquid crystal aanalogvoltage and is imported 1 liquid crystal aanalogvoltage and import 2 liquid crystal aanalogvoltages and export 3 liquid crystal positions output common port 0			The seizure input of CPU, interface board output.
12	R01/CAP3
		13	R02/CAP4
14	R03/CAP5
		15	COM0/VM
16	COM1/VFRAME			Liquid crystal position output common port 1		The control signal of multiplexing dot matrix screen.
		17	COM2/VLINE		Liquid crystal position output common port 2
18	COM3/VCLK			Liquid crystal position output common port 3
		19	SEG0/VD0/VR0		Liquid crystal section output 0			The data signal line of multiplexing dot matrix screen.When CPU has TFT and two kinds of lcd controllers of STN, preferentially use the LCD interface of TFT type.	Carry the interface of segmentation liquid-crystal controller on the CPU, the time spent will not selected unsettled.
36	SEG17/SDCMD
		37	SEG18/SD0
38	SEG19/SD1
		39	SEG20/SD2	Liquid crystal section output 20
40	SEG21/SD3						Liquid crystal section output 21

The jtag interface definition

Numbering	The ARM definition	The DSP definition	The CYGNAL definition
				1	VCC	TMS	VCC
2	GND	nTRST	GND
				3	nTRST	TDI	GND
4	GND	GND	TCK
				5	TDI	VCC	TMS
6	GND	Empty	TDO
				7	TMS	TDO	TDI
8	GND	GND	Empty
				9	TCK	TCK	GND
10	GND	GND	Empty
				11	TDO	TCK
12	nRESET	GND
			13	VCC	EMU0
14	GND	EMU1

Annotate: the power supply of jtag interface (VCC) will be with reference to the requirement of the technical manual and the JTAG cable of cpu chip.

The power interface definition

Numbering	Definition
		1	+5V
2	GND
		3	+12V
4	-12V

The E-LAB bus

1, physical characteristic: respectively arrange the double pin of a row on the both sides up and down of module, on to arrange pin be 16P, following row's pin is 24P; The spacing of double pin is 2.54mm.

2, bus definition:

Ja Jb has comprised 16 data/address buss (D0-D15), 16 address buss (A0-A15), and 12 control buss (CS0-CS3, LCS0-LCS3, ALE, IOWR, IORD, INT), 4 kinds of power lines (VCC ,+12V ,-12V, GND).

Bidirectional data line in the bus links to each other with the data wire of cpu chip after will driving by 245 on the CPU board again, and 245 will and generate total address control signal by CS0---CS7 decoding by RD is controlled.To guarantee that when the design interface plate its data wire is high-impedance state at one's leisure, otherwise must the adjunction buffer circuit.The data wire of not using can be unsettled.

Address wire in the bus, CPU board output links to each other with interface pin after will driving by 244 on the CPU board again, on the interface board not the time spent unsettled.

The chip selection signal line, CPU board output, the interface board input, low level is effective, and during the design CPU board, no pin is unsettled.And when the design interface plate, select 1 switch (wire jumper) to select by 8; When distributing address space, the lowest address scope of each chip selection signal should be greater than 256 bytes.

The external interrupt request signal, the 5V Transistor-Transistor Logic level, the CPU board input, interface board output, low level is effective, and on CPU board, the interrupt line of not using will preferentially use the interrupt line of low numbering to fill, if CPU is the 3V device, must isolate by 244/245.

It is pointed out that above explanation is indicative rather than restrictive, its objective is that being convenient to those of ordinary skills understands the utility model.Therefore, can carry out adaptability revision to particular content according to principle of the present utility model, the definition of each pin of for example above-mentioned J1, J2, J3 connector and PORTA, B, C can change or redefine according to actual needs.

Claims (10)

1. the template with compatibility interface is fixed with the connector that is used to connect outer template on template, it is characterized in that: described connector is the bus structures connectors.

2. the template with compatibility interface according to claim 1 is characterized in that, the data wire pin of bus structures connector has the preliminary data wire pin.

3. the template with compatibility interface according to claim 2 is characterized in that, described preliminary data wire pin is 2 ⁿIndividual, wherein n be more than or equal to or greater than 3 integer.

4. the template with compatibility interface according to claim 1 is characterized in that, described bus structures connector has the inserting groove and the connection-peg of intercommunication, and wherein inserting groove is fixed on the template one side, and connection-peg is fixed on the another side of template.

5. the template with compatibility interface according to claim 1 is characterized in that, described bus structures connector comprises: first connector of extended address, data/address bus and control bus, and second connector of expanding peripherals signal.

6. the template with compatibility interface according to claim 5 is characterized in that, described bus structures connector also comprises: expand the 3rd connector that first connector and second connector do not have the residue cpu signal of expansion.

7. the template with compatibility interface according to claim 5 is characterized in that, described control bus comprises reading writing signal line and chip selection signal line.

8. the template with compatibility interface according to claim 5 is characterized in that, the residue cpu signal comprises: the signal of communication between AD input, liquid crystal, serial ports and expansion daughter board.

9. the template with compatibility interface according to claim 6 is characterized in that, the diverse location on template is provided with first connector, second connector and the 3rd connector respectively.

10. the template with compatibility interface according to claim 5 is characterized in that, the diverse location on template is provided with first connector and second connector respectively.