CN2884353Y - Tax payment acception apparatus - Google Patents

Abstract

The utility model discloses a tax controlling cashier, mainly comprises a main board with whole function of tax controlling processing and tax controlling card management, a printing board with controller and programmable character library storage, the display board with keyboard controller, display controller and display board of programmable character library storage, an IC card board, an interface board; as every module of the utility model has its own micro processor to control, which not only improve efficiency and speed but also lower the requirements on the processor performance with simple design for the circuit and cheaper IC; meanwhile, the high modularization degree lowered the development difficulty, and the card design adopted modularization largely simplify the manufacture, inspection, maintenance, fixing, to adopt the independent programmable character library storage can program individualization and satisfy the users demands.

Description

Tax-control cash register

Technical field

The utility model relates to a kind of tax-control cash register, mainly with the levying by tax of medium-sized and small enterprises, declare dutiable goods with no paper at all.

Background technology

Tax-control cash register is the important component part of national golden tax project, and country has formulated the GB18240 national standard for this reason, and various tax-control cash registers are all according to this standard design.Existing tax-control cash register has the following disadvantages: 1, the model structure complexity of transforming based on original ordinary electronic cashing machine, and the cost height can only partly satisfy the needs of GB; 2, adopt battery power supply in support, maintenance, maintenance, memory requirement height are not suitable for the application in market; 3, the character library of Cai Yonging is perfect inadequately, can not do personalized the adjustment according to user's requirement; 4, security feature is poor, and data are preserved and lacked the necessary security means, influence the realization of tax control function; 5, adopt single all tasks of microprocessor sequential processes, speed is slow, execution efficient is low.

Summary of the invention

The purpose of this utility model is to provide the tax-control cash register that a kind of cost is lower, speed is very fast, security is better, have the user individual customization capability.

The utility model tax-control cash register mainly contains mainboard, interface board, type plate, display board, IC-card plate, wherein:

Mainboard has tax control to be handled, whole abilities of tax-controlling card management, it comprises master controller U3, the asynchronous serial bus control circuit that is connected with master controller U3, tax-controlling memory, article two, IC-card read/write circuit, and extend out program circuit U19 by what parallel bus and master controller U3 articulated, clock circuit, data caching circuit, address latch circuit, master controller U3 also provides two asynchronous serial bus respectively to module communication circuit and the external communication interface circuit of interface board by the asynchronous serial bus control circuit, described two IC-card read/write circuits, article one, connect the IC-card plate by the IC-card read/write circuit and be used for read-write that subscriber card/inspection is blocked, article one, by the SAM deck on the SAM card read/write circuit connection mainboard, be used for the read-write of tax-controlling card;

Interface board comprises that module communication control circuit, external communication interface circuit reach to complete machine provides 5V and 24V power supply and 5V power down protection power supply, and described module communication control circuit provides three asynchronous serial bus to be connected respectively to the print control unit U400 of type plate, the keyboard controller U601 and the display controller U600 of display board;

Type plate comprises print control unit U400, provides one 8 bit parallel bus to connect printing character library storer U404 able to programme, driving circuit by this print control unit U400; Be connected with the external printer core by driving circuit, type plate adopts asynchronous serial bus and mainboard interaction data by the print control unit U400 control of self;

Display board comprises keyboard controller U601, display controller U600, keyboard controller U601 directly connects external keyboard, by asynchronous serial bus and mainboard interaction data, display controller U600 provides one 8 bit data bus to connect 7 sections charactron led drive circuits of character library reservoir U606 able to programme, LCD LCD, light emitting diode type respectively, be connected by the light-emitting diode display of led drive circuit with the outside, display controller U600 is by asynchronous serial bus and mainboard interaction data;

The IC-card plate comprises corresponding IC-card interface protective circuit of user/inspection card and IC-card seat, the IC-card plate directly and mainboard articulate.

The course of work:

Be divided into start, operate as normal, three parts of shutdown.

Start: after the start, 4 controllers (master controller, print control unit, keyboard controller, display controller) start, check the current state of management equipment separately respectively, master controller is responsible for checking whether tax-controlling memory, clock, tax-controlling card data be normal, and can the asynchronous serial bus control circuit operate as normal; Display controller is responsible for checking whether 7 sections charactron LED of LCD LCD, light emitting diode type are normal, shows whether character library is complete; Keyboard controller checks whether keyboard connects normally; Print control unit is responsible for checking whether printer core is working properly, and whether printing character library is complete; Master controller obtains the state of other 3 controllers (print control unit, keyboard controller, display controller) by the asynchronous serial bus control circuit, has corresponding demonstration and buzzer prompting in case self check is broken down; Master controller obtained information after self check was finished from control ephemeral data buffer EEPROM, when confirming to shut down last time whether uncompleted task was arranged, if having, continued to finish the task of last time voluntarily, entered holding state.

Operate as normal: plug-in card or button input commercial affairs or tax data, keyboard controller is responsible for resolving concrete key value, disappear to tremble and handle and the repeat key processing, after obtaining effective key assignments to the master controller submit applications, send button data to master controller, relevant displaying contents sends to display controller by master controller, display controller carries out graphics process, literal dissection process, special display process respectively according to the data of accepting, and the entire process process no longer needs the master controller intervention; Master controller cooperates tax-controlling card to begin to carry out corresponding commercial affairs after having obtained enough information and tax-control data is handled, after data processing is finished, master controller sends relevant print What to print control unit, print control unit prints graphics process, literal dissection process respectively according to the data of accepting, and can be monitored by master controller but the entire process process no longer needs master controller to intervene still; Master controller is in the processing that just can begin the next record data respectively after demonstration, print control unit send data.4 controllers are respectively taken charge of its duty in the whole process, carry out multinomial work simultaneously, and master controller only is responsible for the analysis of valid data and is handled commercial affairs and tax-control data, and other three processors are responsible for concrete interface control.

Shutdown: during powered-down, whether the master controller inspection self exist not finishing of task, if there is uncompleted task, preserve related data, stop the processing of current task, detect printer section and whether finish current print out task, if have uncompleted task, preserve related data, stop the processing of current task, all are not finished the work and all are labeled, and the start back continues to handle to wait for next time.

The utility model also has advantage alone except that having satisfied every requirement of GB to tax-control cash register: finish because whole sensitive data concentrates on the mainboard, guaranteed safety of data; Owing to adopt a plurality of processors, dissimilar tasks is separated parallel processing, this not only makes and carries out the efficient raising, speeds up, and has reduced the performance of processors requirement, and circuit design is more simple, can select more cheap IC for use; Because degree of modularity height has reduced development difficulty, each module is by the microprocessor control of oneself, and primary module need not be concerned about concrete device control; Owing to adopt modular integrated circuit board design, simplified equipment greatly and produced normally, check, safeguard, overhaul; Owing to adopted library stores device independently able to programme, can personalized programme, satisfy the needs that the user uses.

Description of drawings

Fig. 1 is the utility model general structure block diagram.

Fig. 2 is the mainboard electrical schematic diagram.

Fig. 3 is the display board electrical schematic diagram.

Fig. 4 is the type plate electrical schematic diagram.

Fig. 5 is the interface board electrical schematic diagram.

Fig. 6 is an IC-card plate electrical schematic diagram.

Fig. 7 is 7 sections charactron led board electrical schematic diagrams of light emitting diode type.

Embodiment

Fig. 1 has reflected general structure of the present utility model, and it has mainboard, interface board, type plate, display board, IC-card plate, wherein:

Mainboard has whole abilities of tax control processing, tax-controlling card management, and it comprises that master controller U3, the asynchronous serial bus control circuit that is connected with master controller U3, tax-controlling memory, two IC-card read/write circuit SAM card circuit reach by what parallel bus and master controller U3 articulated and extends out program circuit U19, (10000 years) clock circuit, data caching circuit, address latch circuit.Article two, the IC-card read/write circuit connects tax-controlling card interface and user/inspection card respectively; Address latch circuit (the least-significant byte address is provided, and sheet selects 3 bit address), and corresponding most-significant byte address is provided; The line that master controller U3 provides for tax-controlling memory is special-purpose SPI and iic bus, is respectively applied for to connect high-capacity FLASH storer AT45DB161 and tax control ephemeral data buffer memory EEPROM AT24C32.Master controller U3 also provides two asynchronous serial bus respectively to module communication circuit and the external communication interface circuit of interface board by the asynchronous serial bus control circuit;

Interface board is mainly mainboard and external interface is provided and is connected with other template; it comprises module communication control circuit, external communication interface circuit and provides 5V and 24V power supply and 5V power down protection power supply for complete machine; this power supply has adopted the vast capacity secondary capacitor to carry out energy storage cooperation boost switching chip as power supply reserve; can exempt battery (prior art is to use accumulator) like this needs the problem of periodic maintenance, charging, has improved the reliability of system.Described module communication control circuit provides three asynchronous serial bus to be connected respectively to the print control unit U400 of type plate, the keyboard controller U601 and the display controller U600 of display board.

Print control unit U400, printing character library storer U404 able to programme and corresponding driving circuit constitute the type plate with independent character processing power, be connected with printer core by driving circuit, can set printing model and the special content that needs to print by instruction, the mode that print procedure adopts the backstage to carry out, after once having transmitted print data, no longer need the main control circuit intervention.

Display controller U600, keyboard controller U601, library stores device U606 able to programme and corresponding driving circuit constitute the display board with independent displaying character processing power, be connected with the LDE display by led drive circuit, keyboard controller U601 is connected with keyboard.Can call by mode of operation, contrast adjustment, display flashing, the figure that instruction is provided with display etc., the mode that procedure for displaying adopts the backstage to carry out, once transmitted video data after, no longer need the main control circuit intervention.

The IC-card plate comprises that corresponding protection circuit protection and IC-card seat are all arranged on two IC-card interfaces.

The annexation of the structure that Fig. 1 has fully shown each template between extremely, the circuit diagram to individual template carries out auspicious stating respectively below:

Motherboard circuit is referring to Fig. 2:

Master controller U3 adopts integrated package W77E58U, and its 32 I/O mouth lines are divided into four ports of P0～P3.The P0 mouth connects data caching circuit and address latch circuit, and the P2 mouth connects the high address line that extends out program storage and metadata cache; Address latch circuit is made up of address latch chip 74HC573, metadata cache and extend out the procedure stores circuit and form by random access memory 628128 and flash chip 29C040 respectively, this partial circuit specifically be electrically connected for: the 3rd pin D0 of 74HC573 connects the 37th pin D0 of master controller U3, the 4th pin D1 of 74HC573 connects the 36th pin D1 of master controller U3, the 7th pin D2 of 74HC573 connects the 35th pin D2 of master controller U3, the 8th pin D3 of 74HC573 connects the 34th pin D3 of master controller U3, the 13rd pin D4 of 74HC573 connects the 33rd pin D4 of master controller U3, the 14th pin D5 of 74HC573 connects the 32nd pin D5 of master controller U3, the 17th pin D6 of 74HC573 connects the 31st pin D6 of master controller U3, the 18th pin D7 of 74HC573 connects the 30th pin D7 of master controller U3, and address latch chip 74HC573 is used for the least-significant byte address latch with master controller U3; The 2nd pin A0 of 74HC573 and 628128 the 10th pin A0, the 12nd pin A0 of 29C040 links to each other, the 5th pin A1 of 74HC573 and 628128 the 9th pin A1, the 11st pin A1 of 29C040 links to each other, the 6th pin A2 of 74HC573 and 628128 the 8th pin A2, the 10th pin A2 of 29C040 links to each other, the 9th pin A3 of 74HC573 and 628128 the 7th pin A3, the 9th pin A3 of 29C040 links to each other, the 12nd pin A4 of 74HC573 and 628128 the 6th pin A4, the 8th pin A4 of 29C040 links to each other, the 15th pin A5 of 74HC573 and 628128 the 5th pin A5, the 7th pin A5 of 29C040 links to each other, the 16th pin A6 of 74HC573 and 628128 the 4th pin A6, the 6th pin A6 of 29C040 links to each other, the 19th pin A7 of 74HC573 and 628128 the 3rd pin A7, the 5th pin A7 of 29C040 links to each other, this part mainly be with the least-significant byte address signal of master controller U3 output through the 74HC573 address latch give later on 628128 and 29C040 the least-significant byte address is provided.In addition, the 18th pin A8 of master controller U3 the 27th pin A8 that meets 628128 the 25th pin A8,29C040 makes the 9th bit address line; The 26th pin A9 that the 19th pin A9 of master controller U3 meets 628128 the 24th pin A9,29C040 makes the 10th bit address line; The 23rd pin A10 that the 20th pin A10 of master controller U3 meets 628128 the 21st pin A10,29C040 makes the 11st bit address line; The 25th pin A11 that the 21st pin A11 of master controller U3 meets 628128 the 23rd pin A11,29C040 makes the 12nd bit address line; The 4th pin A12 that the 22nd pin A12 of master controller U3 meets 628128 the 2nd pin A12,29C040 makes the 13rd bit address line; The 28th pin A13 that the 23rd pin A13 of master controller U3 meets 628128 the 26th pin A13,29C040 makes the 14th bit address line; The 29th pin A14 that the 24th pin A14 of master controller U3 meets 628128 the 1st pin A14,29C040 makes the 15th bit address line; Master controller U3 by address latch 74HC573 the least-significant byte address latch and jointly control and can control whole 128K storage spaces of 628128 to the control of high address and with latch chip U22:74HC377 among Fig. 2, and jointly control the 128K address space that can control 29C040 by low 15 bit address space and the U22:74HC377 of control 29C040.By the control to U22:74HC377, master controller U3 can be to the control of the 16th, the 17 bit address lines of 29C040 by data bus.

Expansion interface is made up of latch chip 74HC377 U22, U12, U13.The 3rd pin D0 of 74HC377 connects the 39th pin D0 of master controller U3, the 4th pin D1 of 74HC377 connects the 38th pin D1 of master controller U3, the 7th pin D2 of 74HC377 connects the 37th pin D2 of master controller U3, the 8th pin D3 of 74HC377 connects the 36th pin D3 of master controller U3, the 13rd pin D4 of 74HC377 connects the 35th pin D4 of master controller U3, the 14th pin D5 of 74HC377 connects the 34th pin D5 of master controller U3, the 17th pin D6 of 74HC377 connects the 33rd pin D6 of master controller U3, and the 18th pin D7 of 74HC377 connects the 32nd pin D7 of master controller U3; The 2nd pin S_VCC and the 15th pin M_VCC control IC-card power control circuit by U12:74HC377.The 6th pin S_CLK and the 9th pin M_CLK control IC-card clock control circuit by U12:74HC377.By the 5th pin S_RST of U12:74HC377 and resetting of the 16th pin M_RST control IC-card interface circuit.The 12nd pin EN485TX control serial ports by U12:74HC377 sends permission; The 5th pin S_TCP control by U22:74HC377 is to the communication of mixed-media network modules mixed-media.By the 6th pin RAM_A15 of U22:74HC377 and high two bit address of the 9th pin RAM_A16 control 628128.High two bit address of the 12nd pin P_A15 by U22:74HC377 and the 15th pin P_A16 control 29C040.The 16th pin SELECT control serial ports mode of operation by U22:74HC377; Cross the 6th pin FM control buzzer circuit of U13:74HC377.Select by the 9th pin CS45D1 of U13:74HC377 and the sheet of the 12nd pin CS45D2 control control tax-controlling memory.The selection of the 15th pin S0, the 16th pin S1 by U13:74HC377 and the 19th pin S2 control serial port circuit.

Clock circuit was made up of the clock chip DS12887A that includes battery and power management function in 10000 years, the 4th pin D0 of DS12887A connects the 39th pin D0 of master controller U3, the 5th pin D1 of DS12887A connects the 38th pin D1 of master controller U3, the 6th pin D2 of DS12887A connects the 37th pin D2 of master controller U3, the 7th pin D3 of DS12887A connects the 36th pin D3 of master controller U3, the 8th pin D4 of DS12887A connects the 35th pin D4 of master controller U3, the 9th pin D5 of DS12887A connects the 34th pin D5 of master controller U3, the 10th pin D6 of DS12887A connects the 33rd pin D6 of master controller U3, the 11st pin D7 of DS12887A connects the 32nd pin D7 of master controller U3, utilizes data bus to be provided second for master controller U3, divide, the time, day, month, the clock information in year.And carry power down protection.

Tax-controlling memory is made up of storage chip at45db161 or at45db321, by master controller U3 the 1st, 2,7 pin cooperate the 9th pin CS45D1 of U13:74HC377 and the 12nd pin CS45D2 totally 5 pins read information.The tax-controlling memory power supply is made up of power supply chip TPS76033; 6th pin S_CLK and the 9th pin M_CLK control IC-card clock control circuit of 74HC377 of IC-card read-write clock by 74HC377 can be controlled the output of Sheffer stroke gate to the control of Sheffer stroke gate u11a, u7b, and then whether control provide clock signal for IC-card read-write deck; The supplementary storage electricity is made up of storage chip AT24C32 and AT24C1024, utilizes the I2C bus to connect the 6th pin I2CSDA, the 15 pin I2CSCL of master controller U3.Communication Control electricity part is made up of triple gate chip 74HCl25:U21, U23.

Display board circuit is seen Fig. 3:

Display controller U600C adopts integrated package 78E52B, and its 32 I/O mouth lines are divided into four ports of P0～P3.The P0 mouth connects eight D and latchs chip 74HC377 and 74HC373, and the P2 mouth connects the high address line of data memory RAM 62256 and the high address line of Flash memory circuit AM27X040; Address latch circuit is made up of 74HC377, data storage circuitry is made up of random access memory 62256 and flash chip AM27X040, this partial circuit specifically be electrically connected for: the 2nd pin XSD0 of address latch chip 74HC573 connects the 39th pin XSD0 of display controller U600, the 3rd pin XSD1 of 74HC573 connects the 38th pin XSD1 of display controller U600, the 4th pin XSD2 of 74HC573 connects the 37th pin XSD2 of display controller U600, the 5th pin XSD3 of 74HC573 connects the 36th pin XSD3 of display controller U600, the 6th pin XSD4 of 74HC573 connects the 35th pin XSD4 of display controller U600, the 7th pin XSD5 of 74HC573 connects the 34th pin XSD5 of display controller U600, the 8th pin XSD6 of 74HC573 connects the 33rd pin XSD6 of display controller U600, the 9th pin XSD7 of 74HC573 connects the 32nd pin XSD7 of display controller U600, and address latch chip 74HC573 is used for the least-significant byte address latch with display controller U600; The 19th pin XSA0 of 74HC573 and 62256 the 10th pin XSA0, the 12nd pin XSA0 of AM27X040 links to each other, the 18th pin XSA1 of 74HC573 and 62256 the 9th pin XSA1, the 11st pin XSA1 of AM27X040 links to each other, the 17th pin XSA2 of 74HC573 and 62256 the 8th pin XSA2, the 10th pin XSA2 of AM27X040 links to each other, the 9th pin XSA3 of 74HC573 and 62256 the 7th pin XSA3, the 9th pin XSA3 of AM27X040 links to each other, the 15th pin XSA4 of 74HC573 and 62256 the 6th pin XSA4, the 8th pin XSA4 of AM27X040 links to each other, the 14th pin XSA5 of 74HC573 and 62256 the 5th pin XSA5, the 7th pin XSA5 of AM27X040 links to each other, the 13rd pin XSA6 of 74HC573 and 62256 the 4th pin XSA6, the 6th pin XSA6 of AM27X040 links to each other, the 19th pin XSA7 of 74HC573 and 62256 the 3rd pin XSA7, the 5th pin XSA7 of AM27X040 links to each other, this part mainly be with the least-significant byte address signal of display controller U600 output through the 74HC573 address latch give later on 62256 and AM27X040 the least-significant byte address is provided.In addition, the 21st pin XSA8 of display controller U600 the 27th pin XSA8 that meets 62256 the 25th pin XSA8, AM27X040 makes the 9th bit address line; The 26th pin XSA9 that the 22nd pin XSA9 of display controller U600 meets 62256 the 24th pin XSA9, AM27X040 makes the 10th bit address line; The 23rd pin XSA10 that the 23rd pin XSA10 of display controller U600 meets 62256 the 21st pin XSA10, AM27X040 makes the 11st bit address line; The 25th pin XSA11 that the 24th pin XSA11 of display controller U600 meets 62256 the 23rd pin XSA11, AM27X040 makes the 12nd bit address line; The 4th pin XSA12 that the 25th pin XSA12 of display controller U600 meets 62256 the 2nd pin XSA12, AM27X040 makes the 13rd bit address line; The 28th pin XSA13 that the 26th pin XSA13 of display controller U600 meets 62256 the 26th pin XSA13, AM27X040 makes the 14th bit address line; The 29th pin XSA14 that the 27th pin XSA14 of display controller U600 meets 62256 the 1st pin XSA14, AM27X040 makes the 15th bit address line; The 3rd pin XSA15 that the 28th pin XSA15 of display controller U600 meets AM27X040 makes the 16th bit address line; Display controller U600 can control whole 32K storage spaces of 62256 by the least-significant byte address latch of address latch 74HC573 and to the control of high address, and low 16 bit address space by control AM27X040 and jointly control the whole 512K address spaces that can control AM27X040 with CS40 among the figure.The input of code translator U3 meets data line XSD0～XSD7, output connects the base stage of p2～P9, and P2～P9 is 9012 driving charactron LED, in addition, data line XSD0～XSD7H receives on the liquid crystal display LCD, carries out sheet by LEDW and CE19264 and selects U3 (74HC377) and LCD (19264TRULY).P1 triode 9012 drives the backlight leds of LCD, and X9313 is digital adjustable resistance, meets V0 and the VEE of LCD, and keyboard controller U601 links to each other with keyboard, the supervisory keyboard input.

The type plate circuit is seen Fig. 4:

Print control unit U400 adopts integrated package 78E52B, and its 32 I/O mouth lines are divided into four ports of P0～P3.The P0 mouth connects eight D-latch 74HC377 and 74HC573, and the P2 mouth connects the high address line of data memory RAM 62256 and the high address line of flash memory Flash storer 29040; Address latch circuit is made up of latch 74HC573, and data storage circuitry is made up of random access memory 62256 and flash chip 29040.Specifically be electrically connected for: the 2nd pin PRD0 of 74HC573 connects the 39th pin PRD0 of print control unit U400, the 3rd pin PRD1 of 74HC573 connects the 38th pin PRD1 of print control unit U400, the 4th pin PRD2 of 74HC573 connects the 37th pin PRD2 of print control unit U400, the 5th pin PRD3 of 74HC573 connects the 36th pin PRD3 of print control unit U400, the 6th pin PRD4 of 74HC573 connects the 35th pin PRD4 of print control unit U400, the 7th pin PRD5 of 74HC573 connects the 34th pin PRD5 of print control unit U400, the 8th pin PRD6 of 74HC573 connects the 33rd pin PRD6 of print control unit U400, the 9th pin PRD7 of 74HC573 connects the 32nd pin PRD7 of print control unit U400, and address latch chip 74HC573 is used for the least-significant byte address latch with print control unit U400; The 19th pin PRA0 of 74HC573 and 62256 the 10th pin PRA0,29040 the 12nd pin PRA0 links to each other, the 18th pin PRA1 of 74HC573 and 62256 the 9th pin PRA1,29040 the 11st pin PRA1 links to each other, the 17th pin PRA2 of 74HC573 and 62256 the 8th pin PRA2,29040 the 10th pin PRA2 links to each other, the 9th pin PRA3 of 74HC573 and 62256 the 7th pin PRA3,29040 the 9th pin PRA3 links to each other, the 15th pin PRA4 of 74HC573 and 62256 the 6th pin PRA4,29040 the 8th pin PRA4 links to each other, the 14th pin PRA5 of 74HC573 and 62256 the 5th pin PRA5,29040 the 7th pin PRA5 links to each other, the 13rd pin PRA6 of 74HC573 and 62256 the 4th pin PRA6,29040 the 6th pin PRA6 links to each other, the 19th pin PRA7 of 74HC573 and 62256 the 3rd pin PRA7,29040 the 5th pin PRA7 links to each other, and this part mainly is to give 62256 and 29040 the least-significant byte address is provided later on through the 74HC573 address latch least-significant byte address signal of print control unit U400 output.In addition, the 21st pin PRA8 of print control unit U400 meets 62256 the 25th pin PRA8,29040 the 27th pin PRA8 and makes the 9th bit address line; The 22nd pin PRA9 of print control unit U400 meets 62256 the 24th pin PRA9,29040 the 26th pin PRA9 and makes the 10th bit address line; The 23rd pin PRA10 of print control unit U400 meets 62256 the 21st pin PRA10,29040 the 23rd pin PRA10 and makes the 11st bit address line; The 24th pin PRA11 of print control unit U400 meets 62256 the 23rd pin PRA11,29040 the 25th pin PRA11 and makes the 12nd bit address line; The 25th pin PRA12 of print control unit U400 meets 62256 the 2nd pin PRA12,29040 the 4th pin PRA12 and makes the 13rd bit address line; The 26th pin PRA13 of print control unit U400 meets 62256 the 26th pin PRA13,29040 the 28th pin PRA13 and makes the 14th bit address line; The 27th pin PRA14 of print control unit U400 meets 62256 the 1st pin PRA14,29040 the 29th pin PRA14 and makes the 15th bit address line; The 28th pin PRA15 of print control unit U400 meets 29040 the 3rd pin PRA15 and makes the 16th bit address line; Print control unit U400 can control whole 32K storage spaces of 62256 by the least-significant byte address latch of address latch 74HC573 and to the control of high address, and can control whole 512K address spaces of 29040 by controlling 29040 low 16 bit address space and jointly controlling with CS040.Print control unit U400 comes the expansion I/O mouth with 3 data latches 74H377, and with three or eight code translator 74HC138 they is carried out the sheet choosing.Print control unit U400 passes through 14 pin TRIG signal controlling monostable pulse producers, and finely tunes pulsewidth according to 24V; Print control unit U400 is also by UDN2916LB module controls printer driver circuit; By the action of print needle head drive circuit control syringe needle.

The interface board circuit is seen Fig. 5: its power protecting circuit is made up of speed-sensitive switch power supply chip U524, farad level capacitor C 523, C524, adopt speed-sensitive switch power supply chip MX1700 and farad level electric capacity to form back-up source, can exempt accumulator (prior art is to use accumulator) like this needs the problem of periodic maintenance, charging, has improved the reliability of system; Adopt CD4051 8 path analoging switch as the serial ports control circuit, be respectively applied for connection type plate and display board.

IC-card plate circuit is seen Fig. 6: it comprises adopts backward dioded and capacitance-resistance low-pass filter circuit to unite the IC-card interface protective circuit of formation; Comprise that also being used for guiding inserts IC-card, include hard contact, realize the IC-card seat of the physical connection of circuit and IC-card.

The led board circuit is seen Fig. 7: 87 sections charactrons that adopt light LED material to make are arranged on it, be used to show currentitem purpose dealing money and total dealing money.

Whole components and parts market that the utility model adopts is all wherein on sale:

Master controller: W77E58 TUBR051 high speed 8 bit processors that adopt 1 magnificent nation to produce, have the speed that is three times in common 8051 processors, inner integrated 32KB program storage is supported external extender storer, has two independently serial ports.Internal processes can not be derived, frequency of operation 11,000,000

Display controller, keyboard controller, print control unit: adopt the speed of common 8051 processors of W78E52B of totally 3 magnificent nations production, inner integrated 8KB program storage and WDT (house dog), frequency of operation 11,000,000.

Tax-controlling memory: adopt the DATAflash (4MB altogether) of the AT45DB161 SPI interface 2MB of 2 atmel corps, and use the EEPROM AT24C32 of the IIC interface of 4KB to protect as ephemeral data.

Character library able to programme/extender storer: the unified 29c040 512KBFLASH that adopts magnificent nation or atmel corp

Clock circuit: the DS12887A chip that has adopted DALLAS to produce, include lithium battery, crystal oscillator, power management holding circuit, can keep clock work under the outage condition 10 years.

The 5v power supply: adopt the MAX1700 speed-sensitive switch power supply chip of MAXIM company, cooperate a farad level capacitor, can guarantee that external power source stops after, motherboard circuit worked on more than 7 seconds, finished remaining operation and preserved data.

Claims (2)

1, a kind of tax-control cash register is characterized in that mainly containing mainboard, interface board, type plate, display board, IC-card plate, wherein:

Mainboard has tax control to be handled, whole abilities of tax-controlling card management, it comprises master controller U3, the asynchronous serial bus control circuit that is connected with master controller U3, tax-controlling memory, article two, IC-card read/write circuit, and extend out program circuit U19 by what parallel bus and master controller U3 articulated, clock circuit, data caching circuit, address latch circuit, master controller U3 also provides two asynchronous serial bus respectively to module communication circuit and the external communication interface circuit of interface board by the asynchronous serial bus control circuit, described two IC-card read/write circuits, article one, connect the IC-card plate by the IC-card read/write circuit and be used for read-write that subscriber card/inspection is blocked, article one, by the SAM deck on the SAM card read/write circuit connection mainboard, be used for the read-write of tax-controlling card;

Interface board comprises that module communication control circuit, external communication interface circuit reach to complete machine provides 5V and 24V power supply and 5V power down protection power supply, and described module communication control circuit provides three asynchronous serial bus to be connected respectively to the print control unit U400 of type plate, the keyboard controller U601 and the display controller U600 of display board;

Type plate comprises print control unit U400, provides one 8 bit parallel bus to connect printing character library storer U404 able to programme, driving circuit by this print control unit U400; Be connected with the external printer core by driving circuit, type plate adopts asynchronous serial bus and mainboard interaction data by the print control unit U400 control of self;

Display board comprises keyboard controller U601, display controller U600, keyboard controller U601 directly connects external keyboard, by asynchronous serial bus and mainboard interaction data, display controller U600 provides one 8 bit data bus to connect 7 sections charactron led drive circuits of character library reservoir U606 able to programme, LCD LCD, light emitting diode type respectively, be connected by the light-emitting diode display of led drive circuit with the outside, display controller U600 is by asynchronous serial bus and mainboard interaction data;

The IC-card plate comprises corresponding IC-card interface protective circuit of user/inspection card and IC-card seat, the IC-card plate directly and mainboard articulate.

2,, it is characterized in that described 5V power down protection power supply adopts speed-sensitive switch power supply chip MX1700 and farad level electric capacity (C523, C524) to form back-up source according to the described tax-control cash register of claim 1.

Images