CN2796258Y - Data bus switching card and its data processing device - Google Patents
Data bus switching card and its data processing device Download PDFInfo
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- CN2796258Y CN2796258Y CN 200520017021 CN200520017021U CN2796258Y CN 2796258 Y CN2796258 Y CN 2796258Y CN 200520017021 CN200520017021 CN 200520017021 CN 200520017021 U CN200520017021 U CN 200520017021U CN 2796258 Y CN2796258 Y CN 2796258Y
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Abstract
The utility model relates to a data bus switching card which is composed of an FPGA circuit, an FPDP circuit, an RAM circuit and an LVDS circuit. The utility model can also comprises a synchronous interface circuit and a PCI interface circuit, wherein the FPDP circuit is connected with two strips of FPDP buses, one FPDP bus is a receiving FPDP and the other FPDP bus is a transmitting FPDP. In the process of practical application, the receiving FPDP is connected with an A/D collecting module, the transmitting FPDP is connected with a D/A output module, the LVDS circuit can be connected with a data fusion module, the LVDS circuit can also be mutually connected with the other data bus switching card and the receiving FPDP and the sending FPDP of the other data bus switching card are connected with a memory array module. The utility model can realize the storage and the playback of multi-way high speed data in high speed signal digitized storage and playback equipment, namely can realize multi-way bidirection. The utility model expands the application mode of the FPDP bus.
Description
Technical field
The utility model relates to high speed signal digitlization communication technique field, relates in particular to a kind of data/address bus adapter and data processing equipment thereof.
Background technology
Modern society's forward digitlization, information-based direction high speed development in this course, often need great amount of data transmission.And in high-performance real time digital signal processing DSP and design of Data Acquisition System process, the greatest difficulty that the designer runs into is the transmission of data just.The factor that produces the data flow problem has a lot, and it is no longer feasible to handle the conventional method of these problems.
Front panel cable interface---FPDP (the Front Panel DataPort: the front panel data-interface) of a kind of industrial standard of extensive use now.By ANSI (state National Standard Association)/VITA (the international commerce and trade of VME bus association) definition, standard No. is VITA17.1.High speed data transfer between system peripheral, many CPU, the data acquisition equipment is provided.Because above-mentioned characteristic, FPDP is used as a kind of VITA standard now, actual use standard flat cable, and the transmission of 32BIT data parallel, it can provide 32 parallel front panel bus between two or more plates.It is a kind of one-way synchronization bus, and very high message transmission rate can be provided, and can be according to selected implementation with 80M byte per second or 160M byte per second transmission data.Newest F PDP-II standard reaches as high as 400MB/sec
FPDP is now adopted by many manufacturers at present, is a kind of generally acknowledged simple, quick, inexpensive method of transmitting high-speed data between system's each several part.
Traditional using method is: the FPDP bus interface of integrated output function on the high-speed a/d integrated circuit board is directly connected to the input FPDP interface of storing on the control card (or signal processing card) with cable; Be integrated with the defeated/high-speed d/a integrated circuit board of going into the FPDP interface with cable directly with store control card on output FPDP interface be connected.Because the FPDP bus itself is the one-way synchronization bus, self does not have the transmitted in both directions function.This just can't realize the multipath high-speed data in high speed signal digitlization storage and playback apparatus storage and playback also can't realize flow direction control and data fusion control that multichannel is two-way.
Summary of the invention
In view of above-mentioned existing in prior technology problem, the purpose of this utility model provides a kind of data/address bus adapter and data processing equipment thereof, can realize in high speed signal digitlization storage and playback apparatus that the storage of multipath high-speed data and playback can realize that just multichannel is two-way.Expanded the application model of FPDP bus.
The purpose of this utility model is achieved through the following technical solutions:
A kind of data/address bus adapter is made up of FPGA (Field Programmable Gate Array) gate array FPGA circuit, at least one front panel data-interface FPDP circuit, memory RAM and voltage difference divided data interface LVDS circuit; FPDP circuit, RAM all link to each other with the FPGA circuit with the LVDS circuit; Described FPDP circuit connects two FPDP buses, and one is reception FPDP, and another is for sending FPDP.
Described data/address bus adapter also comprises the fifo queue fifo circuit; Fifo circuit connects FPDP circuit and FPGA circuit.
Described FPDP circuit and/or fifo circuit are three groups.
Described data/address bus adapter also comprises synchronous interface circuit; Synchronous interface circuit links to each other with the FPGA circuit.
Described synchronous interface circuit comprises synchronous input interface circuit and synchronous output interface circuit; Described synchronous input interface circuit is by the group pulse input circuit, the direction pulse input circuit, increment signal input circuit, position quadrant input circuit, commutator pulse input circuit, gating signal input circuit and/or Transistor-Transistor Logic level circuit compose in parallel and link to each other with the FPGA circuit respectively; Described synchronous output interface circuit is by the commutator pulse output circuit, and gating signal output circuit and/or group reset signal output circuit compose in parallel and link to each other with the FPGA circuit respectively.
Described data/address bus adapter also comprises Peripheral Component Interconnect Standard PC I interface circuit; The pci interface circuit links to each other with the FPGA circuit.
A kind of data processing equipment of using above-mentioned data/address bus adapter is made up of a data bus switching card, one group of A/D acquisition module, one group D/A output module and data fusion module; The LVDS circuit connection data Fusion Module of data/address bus adapter, the reception FPDP of data/address bus adapter connects the A/D acquisition module, and the transmission FPDP of data/address bus adapter connects the D/A output module.
The another kind of data processing equipment of using above-mentioned data/address bus adapter is made up of two data bus switching cards, one group of A/D acquisition module, one group of D/A output module and storage array module; The reception FPDP of a data bus switching card connects the A/D acquisition module, and the transmission FPDP of data/address bus adapter connects the D/A output module; The reception FPDP of another data/address bus adapter is connected the storage array module with transmission FPDP; The LVDS circuit interconnection of two data bus switching cards.
Described one group of A/D acquisition module comprises three A/D acquisition modules; Described one group of D/A output module comprises three D/A output modules.
By above technical scheme data/address bus adapter described in the utility model as can be known, form by FPGA circuit, FPDP circuit, RAM and LVDS circuit; Can also comprise synchronous interface circuit and pci interface circuit, wherein said FPDP circuit connects two FPDP buses, and one is reception FPDP, and another is for sending FPDP.In actual application, receive FPDP and connect the A/D acquisition module, send FPDP and connect the D/A output module, the LVDS circuit can connect data fusion module, also can interconnect with another one data/address bus adapter, the reception FPDP of another one data/address bus adapter is connected the storage array module with transmission FPDP.The storage and the playback that can realize the multipath high-speed data in high speed signal digitlization storage and playback apparatus can realize that just multichannel is two-way.Expanded the application model of FPDP bus.
Description of drawings
Fig. 1 is a data/address bus adapter structural representation described in the utility model;
Fig. 2 is the external interface figure of data/address bus adapter described in the utility model;
Fig. 3 is the structural representation one of the data processing equipment of data/address bus adapter described in the utility model;
Fig. 4 is the structural representation two of the data processing equipment of data/address bus adapter described in the utility model;
Fig. 5 is that data/address bus adapter work hours described in the utility model are according to receiving sequential chart;
The insertion figure of external information when Fig. 6 is data/address bus adapter described in the utility model work;
Fig. 7 is that data/address bus adapter work hours described in the utility model are according to transmission timing figure.
Embodiment
Data/address bus adapter described in the utility model, its embodiment be as shown in Figure 1:
Form by FPGA (Field Programmable Gate Array) gate array FPGA circuit, front panel data-interface FPDP circuit, memory RAM, fifo queue fifo circuit, synchronous interface circuit, Peripheral Component Interconnect Standard PC I interface circuit and voltage difference divided data interface LVDS circuit; The FPDP circuit links to each other with the FPGA circuit by fifo circuit; Memory RAM, synchronous interface circuit, pci interface circuit all link to each other with the FPGA circuit with voltage difference divided data interface LVDS circuit; Described FPDP circuit connects two FPDP buses, and one is reception FPDP, and another is for sending FPDP.Above-mentioned FPDP circuit and/or fifo circuit are one or more groups, and present embodiment adopts three groups.
Above-mentioned synchronous interface circuit comprises synchronous input interface circuit and synchronous output interface circuit; Described synchronous input interface circuit comprises the group pulse input circuit, direction pulse input circuit, increment signal input circuit, position quadrant input circuit, commutator pulse input circuit, gating signal input circuit and/or Transistor-Transistor Logic level circuit; Described synchronous output interface circuit comprises the commutator pulse output circuit, gating signal output circuit and/or group reset signal output circuit.
In addition, the external interface of data/address bus adapter described in the utility model is as shown in Figure 2:
One side of data/address bus adapter is provided with 6 FPDP circuit, and fixed number is for receiving FPDP1 onboard for 6 FPDP circuit, and reception FPDP2 receives FPDP3, sends FPDP1, sends FPDP2, sends FPDP3.Reception FPDP interface is meant by the outside and send data to multifunction board that transmission FPDP interface is meant by multifunction board and transmits data to the outside.
Second limit of data/address bus adapter is provided with synchronous input interface 2, synchronous input interface 3 and synchronous output interface.Wherein input interface 2 comprises commutator pulse input circuit and strobe pulse input circuit synchronously, and input interface 3 comprises the group pulse input circuit, direction pulse input circuit, increment signal input circuit, position quadrant input circuit synchronously; Output interface comprises the commutator pulse output circuit synchronously, gating signal output circuit, group reset signal output circuit.
The 3rd limit of data/address bus adapter is provided with synchronous input interface 1 and LVDS circuit, and input interface 1 has comprised whole signals of synchronous input interface 2 and synchronous input interface 3 synchronously.
Last one side of data/address bus adapter is provided with the pci interface circuit.
The data processing equipment of the concrete application of data/address bus adapter described in the utility model, its specific embodiment 1, for the single deck tape-recorder mode of operation as shown in Figure 3:
Form by a data bus switching card, three A/D acquisition modules, three D/A output modules and data fusion module; The LVDS circuit connection data Fusion Module of data/address bus adapter, the reception FPDP of data/address bus adapter connects the A/D acquisition module, and the transmission FPDP of data/address bus adapter connects the D/A output module.
The LVDS circuit has controlled transmitted in both directions function.The data/address bus adapter will compile and merge through multipath reception FPDP from the data of multipath high-speed A/D acquisition module, and the data after the output of LVDS circuit is merged are in the data fusion module storage and uniform again.During playback signal, process is opposite.The single deck tape-recorder mode of operation mainly provides the reversible fusion of data/reallocation function, realizes the conversion between FPDP circuit and the LVDS circuit.
The data processing equipment of the concrete application of data/address bus adapter described in the utility model, its specific embodiment 2 is for two card mode of operations also can be called " back-to-back " mode of operation.Promptly two one on blocks of data bus switching cards are operated in FPDP → LVDS state, and another is operated in LVDS → FPDP state.Utilize the controlled signaling transfer point of data/address bus adapter, make the equipment room of a plurality of FPDP of comprising standard interfaces to transfer arbitrarily or to merge.
Its concrete structure is as shown in Figure 4:
Form by two data bus switching cards, three A/D acquisition modules, three D/A output modules and storage array module; The reception FPDP of a data bus switching card connects the A/D acquisition module, and the transmission FPDP of data/address bus adapter connects the D/A output module; The reception FPDP of another data/address bus adapter is connected the storage array module with transmission FPDP; The LVDS circuit interconnection of two data bus switching cards.
Shared in the system to two blocks of data bus switching cards, can be respectively data/address bus adapter A and data/address bus adapter B, be placed on respectively in ADC/DAC cabinet and admission and the playback cabinet.Two blocks of data bus switching card hardware are the same, but the function difference, the FPGA of each plate uses different control logics.Data-interface between data/address bus adapter A and A/D acquisition module or the D/A output module is unidirectional, and data are two-way between data/address bus adapter A and data/address bus adapter B, the storage array module.During system works, data are one-way flow.In the one action process, data only by the A/D acquisition module to storage array module (data recording), or only by the storage array module to D/A output module (data readback), can not have bidirectional traffic simultaneously.
Under the data recording state, the concrete course of work of its data/address bus adapter A is:
At first, the work of the control register specified data bus switching card A in the system is in admission state or playback state.During data recording, data/address bus adapter A is from 3 data that receive the reception of FPDP bus from 3 A/C acquisition modules.Data/address bus adapter A will be wherein one receive the data that receive on the FPDP bus and directly forward by the LVDS circuit, two other is received the data that receive on the FPDP bus deposit RAM earlier in, by the LVDS circuit data forwarding among the RAM is gone out again after waiting for a period of time." frame sequential " position of control register indicates 3 frames that receive after the FPDP bus data merges and puts in order, and first frame is the frame of directly transmitting.
The FPGA circuit is always transmitted immediately and is directly transmitted mouthful data of coming.When direct forwarding mouth has data to arrive,, then stop transmitting the data among the RAM, and an additional postamble is given the data of having transmitted if this moment, the LVDS circuit was transmitted data among the RAM.Begin to transmit the data of " directly transmitting mouth " simultaneously.The FPGA channel check is from directly transmitting mouthful data of coming, and just begins to transmit data after being checked through the frame head sign, stops forwarding data after being checked through the postamble sign.If stop forwarding after the data, receive data again but do not have the frame head sign, then do not transmit these data.
After the data that stop forwarding " directly transmit mouthful " (being checked through postamble), and RAM write and finished, and the FPGA circuit begins to transmit the data among the RAM immediately, and the data in RAM all forward, or are directly transmitted till mouthful data interruption.The FPGA channel check is from receiving the data that FPDP comes, only be checked through the frame head sign after, just general's data subsequently write RAM, stop to write after being checked through the postamble sign., then stop forwarding if find transmitting data among the RAM when preparing when RAM writes data, and additional postamble sign sends out, simultaneously new data is write RAM, cover original data.Finish when RAM writes, whether check the LVDS idle,, transmit the data among the RAM immediately if idle.
If certain reason causes the LVDS circuit to overflow, then lose these frame data and transmit, and empty RAM, wait for from next frame beginning transmission.
Generally speaking, 3 A/D acquisition modules are synchronously sent out data to data/address bus adapter A, and as shown in Figure 5: 3 A/D acquisition modules always almost begin to transmit data simultaneously.But 3 every frame data of A/D acquisition module are not necessarily equally long, so the moment difference of DTD.Data/address bus adapter A selects the data of one of them A/D acquisition module directly to forward, and simultaneously the data of other 2 A/D acquisition modules is carried out buffer memory (writing among the RAM).After if frame data of two A/D acquisition modules all write RAM, directly that circuit-switched data of transmitting does not also distribute, and then waits for up to the reportedly intact data of transmitting among the RAM of restarting of this way; If that circuit-switched data of directly transmitting has passed earlier, frame data of then waiting until other two-way write RAM fully and restart afterwards data among the forwarding RAM.
If 3 receive FPDP all with the speed transmission data of 200MB/s, then such arrangement can be satisfied the requirement of the 100MB/s of system data bandwidth.For example, if the data volume maximum of A/D acquisition module 1, the data that A/D acquisition module 1 can be set are directly transmitted, and the data of A/D acquisition module 2 and A/D acquisition module 3 are transmitted by RAM.Because 3 total data bandwidths of A/D acquisition module are 100MB/s, then the data bandwidth of A/D acquisition module 1 obviously can not surpass 100MB/s, if A/D acquisition module 1 is with the defeated certificate of 200MB/s transmission, then A/D acquisition module 1 takies the time of LVDS interface 50% at most, and the data bandwidth sum of A/D acquisition module 2 and A/D acquisition module 3 can not surpass 100MB/s yet, 50% the time transmission in addition of available LVDS circuit.
Have the data of 2 A/D acquisition modules need write RAM simultaneously, receive between FPDP1 and the FPDP2, the data bandwidth between FPDP1 and the RAM needs greater than 400MB/s.
RAM is divided into 2 zones, deposits the data of 2 cards respectively.
General application program should be provided with direct that mouthful that mouth is a data traffic maximum in 3 A/D acquisition modules of transmitting, and starting the RAM forwarding like this is to be right after after directly transmitting end, and the centre does not have the free time, postpones minimum.
Data/address bus adapter A can receive 1,2 or 3 data that receive the FPDP bus.Enable to receive FPDP1 respectively by the 3bit in control register " FPDP interface enable " position, receive FPDP2, receive FPDP3.If on the reception FPDP that has enabled, do not receive data, then put " the FPDP interface free of data " position of " status register ", but do not quit work.
Control logic is checked the frame number of 3 every frames of A/D acquisition module, if the frame number of 3 A/D acquisition module data that discovery is received simultaneously is inconsistent, then puts " frame synchronization step-out " flag bit of " status register ", but does not quit work.
Control logic is checked synchronous signal line (positive north, bearing increment, orientation quadrant and group pulse signal).Be checked through certain signal when effective, corresponding sign is inserted down the frame head of frame (only be presented to from direct and transmit mouthful frame that comes) down.Certain signal is meant that effectively detecting this signal is uprised by low.The sequential of inserting synchronous mark as shown in Figure 6.
Under the data recording state, the concrete course of work of its data/address bus adapter B is:
At first, work in admission state or playback state by the control register in the system " admission/playback selection " position specified data bus switching card B.During data recording, data/address bus adapter B receives data from the LVDS circuit, and the data that receive are forwarded by sending FPDP1.For sending the bigger fifo circuit of FPDP1 configuration.Overflow if send FPDP1, then abandon follow-up data, and wait is overflowed releasing, the recovery transmission.
Data/address bus adapter B can send frame data to the pci interface circuit when data are sent by transmission FPDP1.Mainframe program is provided with " reading frame number " register.If it is not 0 that control logic detects " reading frame number ", in RAM, write continuous some frame data (by " reading frame number " control).Mainframe program can read the data among the RAM.
Under the data readback state, the concrete course of work of its data/address bus adapter A is:
At first, system is in playback state by control register " admission/playback selection " position specific data bus switching card A1.Data/address bus adapter A receives data from data/address bus adapter B, delivers to corresponding transmission FPDP output after the data flow that receives is separated.
Data/address bus adapter A waits for a synchronizing signal, when synchronizing signal is effective, respectively transmits frame data to each D/A output module.After one frame data of all D/A output modules had transmitted, data/address bus adapter A waited for next synchronizing signal.If not during end of transmission, the synchronizing signal that arrives is again then ignored this synchronizing signal in data.Synchronizing signal is generated by " commutator pulse " or " gating signal " of outside input, and " synchronizing signal selection " position of control register indicates uses generate synchronizing signal for which external signal.When the external signal that detects appointment during by low uprising, the FPGA circuit is inner to generate an efficient synchronization signal.Before the transfer of data of all D/A output modules finishes, and next synchronizing signal arrives, suspend from the LVDS circuit and receive data.
Sequential such as Fig. 7 of transmission data under the data/address bus adapter A normal condition:
Data are unit with the frame, if the work of 3 D/A output modules is arranged, after then a synchronizing signal arrives, need transmission 3 frame data, and each sends on the FPDP and sends 1 frame.These 3 frame data in the data flow that the LVDS circuit is come by fixing sequence arrangement.Put in order by " frame puts in order " position regulation of control register.The frame head of each Frame contains " module No. " field, belongs to which D/A output module to distinguish these frame data." frame puts in order " position can put in order module No. and frame and connect.For example can the regulation module No. be that 1 frame is first frame in 3 frames.After once having transmitted frame data of all D/A output modules, data/address bus adapter A receives data from the LVDS circuit, searches the frame head sign.If be not checked through frame head, then the data of Jie Shouing should abandon.Data/address bus adapter A-directly receives data, till finding the frame head sign.If find the frame head sign, then check " module No. " field.If this field shows that these frame data are first frames in 3 frames, then suspend and receive data, wait for synchronizing signal, when synchronizing signal arrives, recover to receive data, and will receive data and forward from 3 transmission FPDP buses; If " module No. " field shows that this frame is not first frame in 3 frames, then continue to receive data from the LVDS circuit, search next frame head.Till first frame in finding next 3 frames.Ignore synchronizing signal during searching.If during searching, or during data are transmitting, receive a synchronizing signal, ignore this signal, and put " transfer of data step-out " position of " status register ", but do not quit work.
The data of regulation D/A output module 1 transmit by sending FPDP1, and the data of D/A output module 2 transmit by sending FPDP2, and the data of D/A output module 3 transmit by sending FPDP3.
By " data frame number " register the data that comprise what D/A output modules in the data flow are set.For example if frame number is 3, the work of 3 D/A output modules is arranged then, will send 3 frame data after the synchronizing signal, each blocks 1 frame.If frame number is 1, then have only the work of a D/A output module, only send out 1 frame data after each synchronizing signal to a D/A output module.In the course of work if some the time received unnecessary frame from the LVDS circuit, for example the frame number of She Zhiing is 2, but has received the Frame of 3 cards sometimes, then abandons unnecessary Frame, puts " the frame number mistake " of " status register "; Do not receive the frame that needs in the time of as if some, put " frame number mistake " position of " status register ", but do not quit work.
Data/address bus adapter A can innerly when needed produce a synchronizing signal.For example, when system initialization, still do not have (or not receiving) external signal, data/address bus adapter A can oneself produce a synchronizing signal, initiates a data transfer, and frame data are sent on the D/A output module in advance.Receive outer synchronous signal later on, and synchronizing signal of every reception, just transmit frame data to each D/A output module.Under this mode, the D/A output module always shifts to an earlier date a frame time and obtains data.
Replayed section can be subjected to " group pulse signal " control.Enable the group pulse controlled function by control register " group pulse enables " position.Under this mode, some frame data are formed one group.Contain in the frame head of every group first frame one " group mark ".Control logic will detect this sign.Control logic when searching for the frame that needs when next synchronizing signal arrives, be checked the group mark of frame head at every turn simultaneously.If detect group mark, when next synchronizing signal arrives, detect whether outside " group pulse signal " becomes effectively.If this signal is effective, then sequential is normal.If this invalidating signal shows that the data of playback and group pulse signal lose synchronously, control logic is sent a group reset signal by " group reseting signal line ", " group step-out " sign of " status register " is set simultaneously, and these frame data does not transmit.Control logic begins to wait for, everyly comes a synchronizing signal, checks whether " group pulse signal " becomes effectively, if effectively, and the recovery replayed section.Sequential relationship such as Fig. 8 control logic first frame frame head information that each is synchronous proposes out, writes in " user register ".This register can be read by host software.
Under the data readback state, the concrete course of work of its data/address bus adapter B is:
The definite multifunction card in " admission/playback selection " position by control register works in playback state.Data/address bus adapter B receives continuous data flow from receiving the FPDP1 interface, forwards by the LVDS circuit.Control logic is checked the LVDS circuit, if do not allow to send data, then will receive the FPDP1 interface and hang up, if allow to send data, then recovers to receive FPDP1 and receives data.
Data/address bus adapter B can be sent to one piece of data the pci interface circuit when data are transmitted by the LVDS circuit.Mainframe program is provided with " reading frame number " register.If it is not 0 that control logic detects " reading frame number ", in RAM, write continuous some frame data (by " reading frame number " control).Mainframe program can read the data among the RAM.
For ease of understanding, the register tabulation of the data/address bus adapter described in the utility model sees Table 1.
The above data/address bus adapter and data processing equipment thereof only are preferable embodiment of the utility model and representational embodiment, and the structure of described data/address bus adapter also only is representational structure simultaneously; But protection range of the present utility model is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the utility model discloses, and the variation that can expect easily or replacement all should be encompassed within the protection range of the present utility model.Therefore, protection range of the present utility model should be as the criterion with the protection range of claims.
Table 1
| Sequence number | Address offset | Title | Describe | Default value |
| 1 | 0x0 | Status register | Bit0: interrupt Bit1:FPDP interface is countless according to Bit2: frame synchronization step-out Bit3: transfer of data step-out Bit4: frame number mistake Bit5: group step-out Bit6: fail self-test | |
| 2 | 0x4 | Interruption masking | Bit0:1 enables to interrupt, and 0 shielding is interrupted | 0 |
| 3 | 0x8 | Control register | Bit0: admission/playback is selected: 1 admission, 0 playback Bit1: enable control: 1 enables, 0 forbids work Bit2: outer synchronous enabled: 1 enables, 0 forbids that Bit3:FPDP1 enables: 1 enables, 0 forbids that Bit4:FPDP2 enables: 1 enables, 0 forbids that Bit5:FPDP3 enables: 1 enables, 0 forbids Bit6-7: frame sequential, first frame: 00 FPDP1,01 FPDP2,10 FPDP3 Bit8-9: frame sequential, second frame: 00 FPDP1,01 FPDP2,10 FPDP3 Bit1o-11: frame sequential, the 3rd frame: 00 FPDP1,01 FPDP2,10 FPDP3 Bit12-13: synchronizing signal is selected: 01 commutator pulse, 10 strobe pulse Bit14: group pulse enables: 1 enables, 0 forbids Bit15: the inner synchronizing signal of sending out: write 1 signalling Bit16: self check enables: put 1 self check, 0 forbids self check | Admission: it is 1 startup integrated circuit board that 0x1939 playback: 0x1938 initializes rearmounted bit1. Can send out during playback enable behind inner (bit15=1) synchronously transmission one frame synchronously outer |
| 4 | 0x0C | The data frame number | Bit0-1:01 one frame, 10 2 frames, 11 3 frames | 0x3 |
| 5 | 0x10 | User register 1 | The group sequence number | 0x0 |
| 6 | 0x14 | User register 2 | Azimuth information | 0x0 |
| 7 | 0x18 | Read frame number | The data frame number that main frame reads, 0 expression is not read | 0x1 |
| 8 | 0x1C | Reseting register | Bit0: write 1 and reset | 0x0 |
Claims (10)
1, a kind of data/address bus adapter is characterized in that, is made up of FPGA (Field Programmable Gate Array) gate array FPGA circuit, at least one front panel data-interface FPDP circuit, memory RAM and voltage difference divided data interface LVDS circuit; FPDP circuit, RAM all link to each other with the FPGA circuit with the LVDS circuit; Described FPDP circuit connects two FPDP buses, and one is reception FPDP, and another is for sending FPDP.
2, data/address bus adapter according to claim 1 is characterized in that, also comprises the fifo queue fifo circuit; Fifo circuit connects FPDP circuit and FPGA circuit.
3, data/address bus adapter according to claim 1 and 2 is characterized in that, described FPDP circuit and/or fifo circuit are three groups.
4, data/address bus adapter according to claim 1 and 2 is characterized in that, also comprises synchronous interface circuit; Synchronous interface circuit links to each other with the FPGA circuit.
5, data/address bus adapter according to claim 4 is characterized in that, described synchronous interface circuit comprises synchronous input interface circuit and synchronous output interface circuit; Described synchronous input interface circuit is by the group pulse input circuit, the direction pulse input circuit, increment signal input circuit, position quadrant input circuit, commutator pulse input circuit, gating signal input circuit and/or Transistor-Transistor Logic level circuit compose in parallel and link to each other with the FPGA circuit respectively; Described synchronous output interface circuit is by the commutator pulse output circuit, and gating signal output circuit and/or group reset signal output circuit compose in parallel and link to each other with the FPGA circuit respectively.
6, data/address bus adapter according to claim 1 and 2 is characterized in that, also comprises Peripheral Component Interconnect Standard PC I interface circuit; The pci interface circuit links to each other with the FPGA circuit.
7, data/address bus adapter according to claim 4 is characterized in that, also comprises Peripheral Component Interconnect Standard PC I interface circuit; The pci interface circuit links to each other with the FPGA circuit.
8, a kind of data processing equipment of using above-mentioned data/address bus adapter is characterized in that, is made up of a data bus switching card, one group of A/D acquisition module, one group D/A output module and data fusion module; The LVDS circuit connection data Fusion Module of data/address bus adapter, the reception FPDP of data/address bus adapter connects the A/D acquisition module, and the transmission FPDP of data/address bus adapter connects the D/A output module.
9, a kind of data processing equipment of using above-mentioned data/address bus adapter is characterized in that, is made up of two data bus switching cards, one group of A/D acquisition module, one group of D/A output module and storage array module; The reception FPDP of a data bus switching card connects the A/D acquisition module, and the transmission FPDP of data/address bus adapter connects the D/A output module; The reception FPDP of another data/address bus adapter is connected the storage array module with transmission FPDP; The LVDS circuit interconnection of two data bus switching cards.
10, according to Claim 8 or 9 described a kind of data processing equipments of using above-mentioned data/address bus adapter, it is characterized in that described one group of A/D acquisition module comprises three A/D acquisition modules; Described one group of D/A output module comprises three D/A output modules.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200520017021 CN2796258Y (en) | 2005-04-22 | 2005-04-22 | Data bus switching card and its data processing device |
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| CN 200520017021 CN2796258Y (en) | 2005-04-22 | 2005-04-22 | Data bus switching card and its data processing device |
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| CN2796258Y true CN2796258Y (en) | 2006-07-12 |
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| CN 200520017021 Expired - Lifetime CN2796258Y (en) | 2005-04-22 | 2005-04-22 | Data bus switching card and its data processing device |
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| Country | Link |
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| CN (1) | CN2796258Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101179340B (en) * | 2007-12-12 | 2010-09-01 | 熊猫电子集团有限公司 | Method and device for low-swing difference signal bus transfer digital intermediate frequency |
| CN104810006A (en) * | 2015-04-10 | 2015-07-29 | 苏州誉双信息科技有限公司 | Adapter circuit for realizing board card compatibility |
-
2005
- 2005-04-22 CN CN 200520017021 patent/CN2796258Y/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101179340B (en) * | 2007-12-12 | 2010-09-01 | 熊猫电子集团有限公司 | Method and device for low-swing difference signal bus transfer digital intermediate frequency |
| CN104810006A (en) * | 2015-04-10 | 2015-07-29 | 苏州誉双信息科技有限公司 | Adapter circuit for realizing board card compatibility |
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