CN2779620Y - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
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- CN2779620Y CN2779620Y CN 200420084136 CN200420084136U CN2779620Y CN 2779620 Y CN2779620 Y CN 2779620Y CN 200420084136 CN200420084136 CN 200420084136 CN 200420084136 U CN200420084136 U CN 200420084136U CN 2779620 Y CN2779620 Y CN 2779620Y
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Abstract
The utility model relates to a semiconductor structure comprising a first semiconductor material layer and a second semiconductor material layer which have different stress. In the condition that the first semiconductor material layer and the second semiconductor material layer are respectively compressed and extend or extend and are compressed, the stacking collocation of the first semiconductor material layer and the second semiconductor material layer is utilized to regulate the channel stress in semiconductor elements to a strained channel.
Description
Technical field
The utility model relates to semiconductor structure, particularly strained semiconductor element.
Background technology
Semiconductor is the material of a kind of conductive capability between conductor and non-conductor, and so-called semiconductor element is exactly the electronic component that comes out with the peculiar characteristic manufacturing of semi-conducting material, because semiconductor element belongs to solid-state element (Solid State Device), its volume can narrow down to very little size.Recently, be called metal-oxide semiconductor (Metal-Oxide-Semiconductor; MOS) transistor because have advantage such as the few and suitable high integration of power consumption, has in semiconductor element widely and uses.The basic structure of MOS transistor also comprises two and is positioned at mos capacitance device both sides except possessing the capacitor that is made of metal level, oxide layer and semiconductor layer, and it is the semiconductor region opposite with silicon substrate electrically: source electrode (Source) and drain electrode (Drain).
MOS can be divided into n type metal-oxide semiconductor (NMOS) and p type metal-oxide semiconductor (PMOS), wherein NMOS transmits with electronics, PMOS transmits with the hole, because the mobility ratio hole height of electronics under electric field, so under same design, the NMOS component speeds will be faster than the speed of PMOS, and therefore in order to improve the service speed of element, early stage MOS element all is to be main the design with the nmos pass transistor.
Because constantly miniature (the Scaled Down) of semiconductor element size makes the speed of very lagre scale integrated circuit (VLSIC) promote constantly.Yet, when entering time micron from generation to generation, semiconductor element miniature owing to different physics and technical restriction become difficult.In addition, in cmos circuit,,, therefore usually the area design of PMOS is become 2～3 times of NMOS for PMOS among the CMOS and the current drives of NMOS can be mated because hole mobility (Hole Mobility) is less than the mobility of electronics.Yet the integration and the speed of the element that such design makes all are affected.Therefore, in order further to improve the speed of integrated circuit, just must propose new component structure or use new material.
Summary of the invention
In order to make high-speed inferior micrometre CMOS element, therefore, the purpose of this utility model is utilized the collocation of the semiconductor material layer of tool compression stress and stretching stress for a kind of semiconductor structure is provided, can be applicable on general base material or the insulating barrier in the silicon wafer base material, so as to adjusting channel stress.
According to above-described purpose, semiconductor structure of the present utility model can comprise: first semiconductor material layer, and be stacked on first semiconductor material layer and the second semiconductor material layers different stress of the first semiconductor material layer tool.This first semiconductor material layer and second semiconductor material layer have different lattice constants respectively, therefore can under the situation of the first semi-conducting material layer compression and the extension of second semiconductor material layer or the extension of first semiconductor material layer and the second semi-conducting material layer compression, adjust stress so as to checking and balance.Above-mentioned semiconductor can be applicable to silicon wafer base material on the base material of general naked layer or the insulating barrier.
In electronic component,, have structure applications of the present utility model now integrated circuit technique thereby promote owing to can adjust channel stress to improve carrier transport factor.
Brief Description Of Drawings
Below in conjunction with accompanying drawing embodiment of the present utility model is described in further detail.
In the accompanying drawing,
Fig. 1 is applied to the generalized section of silicon substrate on the insulating barrier for the utility model semiconductor structure;
Fig. 2 is the utility model semiconductor structure one embodiment profile;
Fig. 3 is another embodiment profile of the utility model semiconductor structure; And
Fig. 4 is the utility model semiconductor structure embodiment profile again.
Embodiment
In order to make the micrometre CMOS element high-speed time, must increase the carrier transport factor (Carrier Mobility) of passage and reduce the parasitic capacitance (Parasitic Capacitance) of source electrode and drain electrode.Carrier transport factor in the silicon materials, particularly hole mobility can be very low because of the development restriction of the strain rate (Switching Speed) of time micrometre CMOS element.In order to overcome such problem, the utility model discloses a kind of strained semiconductor structure, utilizes interacting of semi-conducting material interlayer with different stress, to carry out the stress adjustment of passage.
The utility model discloses a kind of semiconductor structure, utilizes the mutual storehouse of semi-conducting material of the semi-conducting material of tool compression stress (Compressive Stress) and stretching stress (Tensile Stress) and forms semiconductor structure.Wherein, because the semiconductor material has different stress, both lattice constants are also inequality.Therefore, under the situation that semiconductor material compression and second half conductor material are upheld, check and balance and form tension force passage (Strained-Channel), thereby can increase electronics or hole mobility.
The semi-conducting material of above-mentioned tool compression stress and the semi-conducting material of tool stretching stress all can be selected from alloy semiconductor (Alloy Semiconductor), elemental semiconductor (Element Semiconductor) or compound semiconductor (Compound Semiconductor) material.General alloy semiconductor material for example has SiGe (SiGe), carbon germanium silicon (SiGeC) or carborundum (SiC) etc.; Elemental semiconductors then has silicon and germanium or the like; Compound semiconductor then for example has semi-conducting material that GaAs (GaAs), arsenic calorize gallium (GaAlAs) or indium phosphide (InP) etc. are made of III V family or II VI compounds of group respectively etc.The above-mentioned material utilization of can arranging in pairs or groups mutually, the utility model is not limited thereto.
Semiconductor structure of the present utility model can utilize the semi-conducting material of tool compression stress or tool stretching stress to be base material earlier, again with the semiconductor material deposition of another tool counter stress thereon.Perhaps, can be on general base material or insulating barrier silicon substrate (Silicon-On-Insulator; SOI) on the structure, form semiconductor structure of the present utility model, the utility model is not limited thereto.
Fig. 1 is applied to the generalized section of silicon substrate structure on the insulating barrier for the utility model semiconductor structure.Please refer to Fig. 1, silicon substrate generally is made of silicon substrate 100 and insulating barrier 102 on the insulating barrier, and has silicon-containing film layer (not illustrating) on insulating barrier.But the utility model utilizes first semiconductor material layer 106 and is positioned at second semiconductor material layer 108 on first semiconductor material layer 106 at this, replaces general silicon-containing film layer.Wherein, first semiconductor material layer 106 has compression stress, and second semiconductor material layer 108 has stretching stress, because interacting of first semiconductor material layer 106 and second semiconductor material layer 108, thereby can adjust channel stress in first semiconductor material layer 106 and second semiconductor material layer 108.
In the utility model preferred embodiment, above-mentioned insulating barrier 102 is constituted by imbedding oxide layer, be generally the silicon dioxide material, and first semiconductor material layer 106 is made of germanium material, and 108 of second semiconductor material layers are made of silicon materials.And the preferred thickness of first semiconductor material layer 106 and second semiconductor material layer 108 is all less than 400 .It should be noted that the utility model above-mentioned material and thickness, can be according to actual product and the stress value of being adjusted changes only for giving an example, the utility model is not limited thereto.
In addition, when semiconductor structure of the present utility model only used general silicon substrate 100,106 of first semiconductor material layers were located immediately at silicon substrate 100 tops, and second semiconductor material layer 108 is positioned on first semiconductor material layer 106 again.At this moment, first semiconductor material layer can not be connected with an active area (Active Area) (illustrating), and and silicon substrate between, (Air Tunnel) insulate with aire tunnel.
No matter above-mentioned the utility model semiconductor structure, be positioned at the structure of silicon substrate on the insulating barrier or be positioned at the structure of general silicon substrate, all can carry out follow-up manufacturing and form semiconductor element.The utility model describes with several embodiment.
In the utility model one embodiment, in above-mentioned semiconductor structure, form several insulating regions 110, as shown in Figure 2.In general, these insulating regions 110 can be shallow slot isolation structure, but when these insulating regions 110 are arranged in first semiconductor material layer 106 or second semiconductor material layer 108, can select to allow it have different stress, and cause these semiconductor material layers to have more stress respectively.For example, when insulating regions 110 has stretching stress, then can cause first semiconductor material layer 106 to have more compression stress; And insulating regions 110 has compression stress, can cause second semiconductor material layer 108 to have more stretching stress.
Perhaps in another embodiment of the utility model, also in the structure of Fig. 2, form electrically the semiconductor region opposite with base material 100, source electrode 112 with drain 114, as shown in Figure 3.And same, as above-mentioned insulating regions 100,, then can cause first semiconductor material layer 106 to have more compression stress if source electrode 112 has stretching stress with drain electrode 114; If source electrode 112 has compression stress with drain electrode 114, then can cause second semiconductor material layer 108 to have more stretching stress.
And at the utility model again among the embodiment, also forming on the structure of Fig. 3 for example be sedimentary deposit 116 of cover layer (Cap Layer) or the like, and as shown in Figure 4, this sedimentary deposit 116 is covered in source electrode 112 and drains on 114, or only covers one of them.If sedimentary deposit 116 has compression stress, then can cause first semiconductor material layer 106 to have more compression stress; If sedimentary deposit 116 has stretching stress, then can cause second semiconductor material layer 106 to have more stretching stress.
Perhaps, as shown in Figure 3, more can form silicon compound (figure do not show), this silicon compound can be positioned at source electrode 112 or drain on 114.Have stretching stress and work as this silicon compound, then can cause first semiconductor material layer 106 to have more compression stress; If silicon compound has compression stress, then can cause second semiconductor material layer 106 to have more stretching stress.
It should be noted that, above-mentioned first semiconductor material layer has compression stress, and second semiconductor material layer 108 has stretching stress only for giving an example, in other embodiments, also can allow first semiconductor material layer have stretching stress, and form second semiconductor material layer thereon with compression stress.And above-mentioned semiconductor structure of the present utility model is not limited only to the mutual storehouse of single first semiconductor material layer and single second semiconductor material layer, can be according to product or arts demand and form with the mutual storehouse of greater number, and the utility model is not limited thereto.
Characteristics of the present utility model are, with material with compression stress and the mutual collocation with material of stretching stress, therefore can regulate the channel stress of the semiconductor element of manufacturing as required, thereby form strained passage.Because semiconductor structure of the present utility model can increase the mobility in electronics or hole,, all can have the existing high service speed of semiconductor element no matter therefore in NMOS or PMOS transistor.And these advantages concerning existing semiconductor technology, are a much progress in fact.
Be understandable that; for the person of ordinary skill of the art; can make other various corresponding changes and distortion according to the technical solution of the utility model and technical conceive, and all these changes and distortion all should belong to the protection range of the appended claim of the utility model.
Claims (52)
1, a kind of semiconductor structure is characterized in that, comprises at least:
At least one first semiconductor material layer; And
At least one second semiconductor material layer is positioned on this first semiconductor material layer, wherein this first semiconductor material layer and this second semiconductor material layer have stress of different nature, and this first semiconductor material layer and the mutual storehouse of this second semiconductor material layer, so as to compress respectively at this first semiconductor material layer and this second semiconductor material layer with uphold or uphold with situation about compressing under, check and balance and cause strain.
2, semiconductor structure according to claim 1, it is characterized in that, the first above-mentioned semiconductor material layer is made of alloy semiconductor, and the material of this first semiconductor material layer is selected from a group that is made up of SiGe, carbon SiGe and carborundum.
3, semiconductor structure according to claim 1, it is characterized in that, the second above-mentioned semiconductor material layer is made of alloy semiconductor, and the material of this second semiconductor material layer is selected from a group that is made up of SiGe, carbon SiGe and carborundum.
4, semiconductor structure according to claim 1 is characterized in that, the first above-mentioned semiconductor material layer is made of elemental semiconductor, and the material of this first semiconductor material layer is selected from a group that is made up of silicon and germanium.
5, semiconductor structure according to claim 1 is characterized in that, the second above-mentioned semiconductor material layer is made of elemental semiconductor, and the material of this second semiconductor material layer is selected from a group that is made up of silicon and germanium.
6, semiconductor structure according to claim 1, it is characterized in that, the first above-mentioned semiconductor material layer is made of compound semiconductor, and the material of this first semiconductor material layer is selected from a group that is made up of IIIV families such as GaAs, arsenic calorize gallium and indium phosphide and IIVI compounds of group.
7, semiconductor structure according to claim 1, it is characterized in that, the second above-mentioned semiconductor material layer is made of compound semiconductor, and the material of this second semiconductor material layer is selected from a group that is made up of IIIV families such as GaAs, arsenic calorize gallium and indium phosphide and IIVI compounds of group.
8, semiconductor structure according to claim 1 is characterized in that, also comprises several insulating regions, and this insulating regions has stretching stress, and causes this first semiconductor material layer to have more multiple pressure stress under compression.
9, semiconductor structure according to claim 8 is characterized in that, above-mentioned insulating regions has compression stress, and causes this second semiconductor material layer to have more stretching stress.
10, semiconductor structure according to claim 1, it is characterized in that, also comprise at least one source region and at least one drain region, above-mentioned source region or drain region have stretching stress, and cause this first semiconductor material layer to have more multiple pressure stress under compression.
11, semiconductor structure according to claim 10 is characterized in that, above-mentioned source region or drain region have compression stress, and causes this second semiconductor material layer to have more stretching stress.
12, semiconductor structure according to claim 10 is characterized in that, comprises that also a sedimentary deposit is positioned on this source region or this drain region, and wherein this sedimentary deposit has compression stress, and causes this first semiconductor material layer to have more multiple pressure stress under compression.
13, semiconductor structure according to claim 10 is characterized in that, comprises that also a sedimentary deposit is positioned on this source region or this drain region, and wherein this sedimentary deposit has stretching stress, and causes this second semiconductor material layer to have more stretching stress.
14, semiconductor structure according to claim 10, it is characterized in that, comprise that also a silicon compound is positioned on this source region or this drain region, wherein this silicon compound has stretching stress, and causes this first semiconductor material layer to have more multiple pressure stress under compression.
15, semiconductor structure according to claim 10, it is characterized in that, comprise that also a silicon compound is positioned on this source region or this drain region, wherein this silicon compound has compression stress, and causes this second semiconductor material layer to have more stretching stress.
16, semiconductor structure according to claim 1 is characterized in that, the thickness of above-mentioned at least one first semiconductor material layer is less than 400 .
17, semiconductor structure according to claim 1 is characterized in that, the thickness of above-mentioned at least one second semiconductor material layer is less than 400 .
18, a kind of semiconductor structure is characterized in that, comprises at least:
One base material;
One insulating barrier is positioned on this base material;
At least one first semiconductor material layer is positioned on this insulating barrier; And
At least one second semiconductor material layer is positioned on this first semiconductor material layer, wherein this first semiconductor material layer and this second semiconductor material layer have stress of different nature, and this first semiconductor material layer and the mutual storehouse of this second semiconductor material layer, so as to compress respectively at this first semiconductor material layer and this second semiconductor material layer with uphold or uphold with situation about compressing under, check and balance and cause strain.
19, semiconductor structure according to claim 18, it is characterized in that, the first above-mentioned semiconductor material layer is made of alloy semiconductor, and the material of this first semiconductor material layer is selected from a group that is made up of SiGe, carbon SiGe and carborundum.
20, semiconductor structure according to claim 18, it is characterized in that, the second above-mentioned semiconductor material layer is made of alloy semiconductor, and the material of this second semiconductor material layer is selected from a group that is made up of SiGe, carbon SiGe and carborundum.
21, semiconductor structure according to claim 18 is characterized in that, the first above-mentioned semiconductor material layer is made of elemental semiconductor, and the material of this first semiconductor material layer is selected from a group that is made up of silicon and germanium.
22, semiconductor structure according to claim 18 is characterized in that, the second above-mentioned semiconductor material layer is made of elemental semiconductor, and the material of this second semiconductor material layer is selected from a group that is made up of silicon and germanium.
23, semiconductor structure according to claim 18, it is characterized in that, the first above-mentioned semiconductor material layer is made of compound semiconductor, and the material of this first semiconductor material layer is selected from a group that is made up of IIIV families such as GaAs, arsenic calorize gallium and indium phosphide and IIVI compounds of group.
24, semiconductor structure according to claim 18, it is characterized in that, the second above-mentioned semiconductor material layer is made of compound semiconductor, and the material of this second semiconductor material layer is selected from a group that is made up of IIIV families such as GaAs, arsenic calorize gallium and indium phosphide and IIVI compounds of group.
25, semiconductor structure according to claim 18 is characterized in that, above-mentioned insulating barrier is imbedded oxide layer by one and constituted.
26, semiconductor structure according to claim 18 is characterized in that, also comprises several insulating regions, and this insulating regions has stretching stress, and causes this first semiconductor material layer to have more multiple pressure stress under compression.
27, semiconductor structure according to claim 26 is characterized in that, above-mentioned insulating regions has compression stress, and causes this second semiconductor material layer to have more stretching stress.
28, semiconductor structure according to claim 18, it is characterized in that, also comprise at least one source region and at least one drain region, above-mentioned source region or drain region have stretching stress, and cause this first semiconductor material layer to have more multiple pressure stress under compression.
29, semiconductor structure according to claim 28 is characterized in that, above-mentioned source region or drain region have compression stress, and causes this second semiconductor material layer to have more stretching stress.
30, semiconductor structure according to claim 28 is characterized in that, comprises that also a sedimentary deposit is positioned on this source region or this drain region, and wherein this sedimentary deposit has compression stress, and causes this first semiconductor material layer to have more multiple pressure stress under compression.
31, semiconductor structure according to claim 28 is characterized in that, comprises that also a sedimentary deposit is positioned on this source region or this drain region, and wherein this sedimentary deposit has stretching stress, and causes this second semiconductor material layer to have more stretching stress.
32, semiconductor structure according to claim 28, it is characterized in that, comprise that also a silicon compound is positioned on this source region or this drain region, wherein this silicon compound has stretching stress, and causes this first semiconductor material layer to have more multiple pressure stress under compression.
33, semiconductor structure according to claim 28, it is characterized in that, comprise that also a silicon compound is positioned on this source region or this drain region, wherein this silicon compound has compression stress, and causes this second semiconductor material layer to have more stretching stress.
34, semiconductor structure according to claim 18 is characterized in that, the thickness of above-mentioned at least one first semiconductor material layer is less than 400 .
35, semiconductor structure according to claim 18 is characterized in that, the thickness of above-mentioned at least one second semiconductor material layer is less than 400 .
36, a kind of semiconductor structure is characterized in that, comprises at least:
One base material;
At least one first semiconductor material layer, wherein between this first semiconductor material layer and this base material with aire tunnel as insulation; And
At least one second semiconductor material layer is positioned on this first semiconductor material layer, wherein this first semiconductor material layer and this second semiconductor material layer have stress of different nature, and this first semiconductor material layer and the mutual storehouse of this second semiconductor material layer, so as to compress respectively at this first semiconductor material layer and this second semiconductor material layer with uphold or uphold with situation about compressing under, check and balance and cause strain.
37, semiconductor structure according to claim 36, it is characterized in that, the first above-mentioned semiconductor material layer is made of alloy semiconductor, and the material of this first semiconductor material layer is selected from a group that is made up of SiGe, carbon SiGe and carborundum.
38, semiconductor structure according to claim 36, it is characterized in that, the second above-mentioned semiconductor material layer is made of alloy semiconductor, and the material of this second semiconductor material layer is selected from a group that is made up of SiGe, carbon SiGe and carborundum.
39, semiconductor structure according to claim 36 is characterized in that, the first above-mentioned semiconductor material layer is made of elemental semiconductor, and the material of this first semiconductor material layer is selected from a group that is made up of silicon and germanium.
40, semiconductor structure according to claim 36 is characterized in that, the second above-mentioned semiconductor material layer is made of elemental semiconductor, and the material of this second semiconductor material layer is selected from a group that is made up of silicon and germanium.
41, semiconductor structure according to claim 36, it is characterized in that, the first above-mentioned semiconductor material layer is made of compound semiconductor, and the material of this first semiconductor material layer is selected from a group that is made up of IIIV families such as GaAs, arsenic calorize gallium and indium phosphide and IIVI compounds of group.
42, semiconductor structure according to claim 36, it is characterized in that, the second above-mentioned semiconductor material layer is made of compound semiconductor, and the material of this second semiconductor material layer is selected from a group that is made up of IIIV families such as GaAs, arsenic calorize gallium and indium phosphide and IIVI compounds of group.
43, semiconductor structure according to claim 36 is characterized in that, also comprises several insulating regions, and this insulating regions has stretching stress, and causes this first semiconductor material layer to have more multiple pressure stress under compression.
According to the described semiconductor structure of claim 43, it is characterized in that 44, above-mentioned insulating regions has compression stress, and cause this second semiconductor material layer to have more stretching stress.
45, semiconductor structure according to claim 36, it is characterized in that, also comprise at least one source region and at least one drain region, above-mentioned source region or drain region have stretching stress, and cause this first semiconductor material layer to have more multiple pressure stress under compression.
According to the described semiconductor structure of claim 45, it is characterized in that 46, above-mentioned source region or drain region have compression stress, and cause this second semiconductor material layer to have more stretching stress.
According to the described semiconductor structure of claim 45, it is characterized in that 47, comprise that also a sedimentary deposit is positioned on this source region or this drain region, wherein this sedimentary deposit has compression stress, and causes this first semiconductor material layer to have more multiple pressure stress under compression.
According to the described semiconductor structure of claim 45, it is characterized in that 48, comprise that also a sedimentary deposit is positioned on this source region or this drain region, wherein this sedimentary deposit has stretching stress, and causes this second semiconductor material layer to have more stretching stress.
49, according to the described semiconductor structure of claim 45, it is characterized in that, comprise that also a silicon compound is positioned on this source region or this drain region, wherein this silicon compound has stretching stress, and causes this first semiconductor material layer to have more multiple pressure stress under compression.
50, according to the described semiconductor structure of claim 45, it is characterized in that, comprise that also a silicon compound is positioned on this source region or this drain region, wherein this silicon compound has compression stress, and causes this second semiconductor material layer to have more stretching stress.
51, semiconductor structure according to claim 36 is characterized in that, the thickness of above-mentioned at least one first semiconductor material layer is less than 400 .
52, semiconductor structure according to claim 36 is characterized in that, the thickness of above-mentioned at least one second semiconductor material layer is less than 400 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420084136 CN2779620Y (en) | 2004-07-22 | 2004-07-22 | Semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420084136 CN2779620Y (en) | 2004-07-22 | 2004-07-22 | Semiconductor structure |
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| CN2779620Y true CN2779620Y (en) | 2006-05-10 |
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| CN 200420084136 Expired - Lifetime CN2779620Y (en) | 2004-07-22 | 2004-07-22 | Semiconductor structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103390634A (en) * | 2012-05-09 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Sic mosfet structure and manufacturing method thereof |
| WO2015039337A1 (en) * | 2013-09-23 | 2015-03-26 | 李利锋 | Semiconductor structure |
-
2004
- 2004-07-22 CN CN 200420084136 patent/CN2779620Y/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103390634A (en) * | 2012-05-09 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Sic mosfet structure and manufacturing method thereof |
| CN103390634B (en) * | 2012-05-09 | 2015-12-02 | 中芯国际集成电路制造(上海)有限公司 | SiC MOSFET structure and manufacture method thereof |
| WO2015039337A1 (en) * | 2013-09-23 | 2015-03-26 | 李利锋 | Semiconductor structure |
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| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20140722 Granted publication date: 20060510 |