CN2768299Y - Switching type control device - Google Patents

Abstract

The utility model relates to a switching type control device which can be used for a one-time side control power supply. The utility model comprises a voltage waveform detector, a voltage feedback signal and a discharge time signal are generated through a voltage signal of a multiple sampling transformer; the voltage feedback signal is amplified by a voltage-loop error amplifier to generate a control signal; a discharge-current signal and a standby signal are correspondingly generated by an off-time modulator according to the control signal and an under-voltage signal; a pulse signal is generated by an oscillator according to the discharge-current signal, and the off time of a switching signal is determined by the pulse signal; the switching signal is generated by a pulse width modulator according to the pulse signal and the standby signal. The off time of the switching signal is controlled by the standby signal, and a minimal switching frequency can be maintained. The switching signal can be used for stabilizing and adjusting the output of the power supply.

Description

Switching control device

Technical field

The utility model relates to a kind of switching control device, is used in the control of power supply unit, particularly about the switching control device of all die change formula power supply units.

Background technology

Various power supply units have used is widely providing the stable voltage of adjusting.Based on the consideration that meets safety (safety), (off-line) power supply unit of an off-line type must provide electrical isolation (galvanic isolation) between primary side and secondary side.One optical coupler (optical-coupler) must be used for stablizing the output voltage of adjusting this off-line type power supply unit with secondary side voltage stabilizing adjuster (secondary-side regulator).In order to save number of parts and the needs of removing the secondary side anti current feed circuit, the primary side control technology is suggested in succession, and for example No. the 4th, 302,803, the U.S. Patent bulletin of announcing on November 24th, 1981.Yet above-mentioned prior art can't satisfy precise output voltage, and under the underloading condition, power loss is also quite serious.

Technology contents

Main purpose of the present utility model is under the demand that does not have optical coupler and secondary side voltage stabilizing adjuster, provides one to switch control device at side, is used for accurately controlling the output voltage of power supply unit.In addition, the utility model also proposes modulation deadline (off-time modulation), is used for reducing switching frequency, reduces the power loss of power supply unit simultaneously under the underloading condition.

The utility model discloses the power supply unit that a kind of switching control device is applied to primary side control, comprises a power switch and is used for switching a transformer, and this transformer is provided by the input voltage of this power supply unit.One switches this power switch of signal controlling, is used for stablizing the output voltage of adjusting power supply unit.One controller is connected to this transformer, during this section of deadline of this switching signal, the discharge time by repeatedly take a sample a voltage signal and this transformer, is used for producing a voltage feedback signal.First operational amplifier and first reference voltage are formed a voltage circuit error amplifier, are used for amplifying this voltage feedback signal and export a control signal.This controller is to receive this control signal and export this switching signal.This controller increases the deadline of this switching signal again according to the reduction of this control signal, wherein this switching signal keeps the switching frequency of a minimum to switch this transformer, and this voltage signal is used for taking a sample.

This controller comprises a voltage-waveform detector, is connected to this transformer, and by the auxiliary winding (auxiliary winding) of this transformer, this discharge time signal by repeatedly take a sample this voltage signal and this transformer produces this voltage feedback signal.By a voltage divider (voltage divider), this voltage-waveform detector is connected to the auxiliary winding of transformer.The discharge time of this discharge time signal indication transformer secondary side switch current.This voltage circuit error amplifier is connected to this voltage-waveform detector, is made up of first operational amplifier and first reference voltage, is used for amplifying this voltage feedback signal and produces this control signal.One deadline modulator be used for reducing power loss, be connected to this voltage circuit error amplifier, receive this control signal and and cross low voltage signal, be used for exporting a discharging current signal and a standby signal.Wherein reduce this discharging current signal and be proportional to this control signal of reduction.This is crossed low voltage signal and represents that a lower supply voltage outputs to this controller, reduces this deadline of this switching signal simultaneously.One oscillator is connected to this of modulator deadline, receive this discharging current signal, be used for exporting a pulse signal and a ramp signal, this pulse signal is used the deadline of deciding this switching signal, and the pulse duration increase of this pulse signal is proportional to this discharging current signal minimizing.

One adder is connected to a current sensing resistor, and is supplied with by this ramp signal, produces a slope signal.One pulse width modulation device is connected to this voltage circuit error amplifier, this modulator, this oscillator and this adder deadline, receive this control signal, this standby signal, this pulse signal and this slope signal and produce this switching signal, stablize the pulse duration of adjusting this switching signal by this control signal and this slope signal, therefore output voltage can accurately be adjusted.Increasing the pulse duration that is proportional to this pulse signal the deadline of this switching signal increases.For this voltage signal of repeatedly taking a sample, this standby signal is further controlled the deadline of this switching signal, and the switching frequency that is used for keeping this switching signal to have a minimum switches this transformer.According to the minimizing of load, increase the deadline of this switching signal, and reduce switching frequency.Therefore, under the underloading condition, can reduce power loss.

Below in conjunction with drawings and Examples the utility model is elaborated.

Description of drawings

Fig. 1 has the circuit block diagram of switching control device for power supply unit;

Fig. 2 is the main waveform of power supply unit and switching control device;

Fig. 3 is the control device of preferred embodiment of the present utility model;

Fig. 4 is the voltage-waveform detector of preferred embodiment of the present utility model;

Fig. 5 is the oscillator of preferred embodiment of the present utility model;

Fig. 6 is modulator deadline of preferred embodiment of the present utility model;

Fig. 7 is the circuit diagram of pulse width modulation device of the present utility model;

Fig. 8 is the circuit diagram that wakes timer up of the present utility model; And

Fig. 9 is the circuit diagram of adder of the present utility model.

Wherein, Reference numeral:

10 transformers

20 transistors

30 current sensing resistors

31 electric capacity

40 rectifiers

45 electric capacity

50 resistance

51 resistance

60 rectifiers

65 electric capacity

70 control device

71 operational amplifiers

73 comparators

75 comparators

79 NAND gate logical circuits

100 voltage-waveform detector

110 electric capacity

111 electric capacity

115 electric capacity

121 switches

122 switches

123 switches

124 switches

125 switches

130 diodes

131 diodes

135 current sources

150 operational amplifiers

151 operational amplifiers

155 comparators

156 minimum detectable signals

161 inverters

162 inverters

163 NAND gate logical circuits

164 ANDs

165 ANDs

166 ANDs

170 D flip-flops

171 D flip-flops

180 current sources

181 transistors

182 electric capacity

190 sampling pulse generators

200 oscillators

201 operational amplifiers

205 comparators

210 resistance

215 electric capacity

230 switches

231 switches

232 switches

233 switches

250 transistors

251 transistors

252 transistors

253 transistors

254 transistors

255 transistors

260 inverters

300 deadline modulator

310 operational amplifiers

311 resistance

314 transistors

315 transistors

316 transistors

321 critical currents

325 maximum discharge currents

329 minimum discharging currents

330 counters

331 comparators

332 comparators

340 buffers

350 inverters

351 NAND gate logical circuits

352 NAND gate logical circuits

356 ANDs

357 ANDs

381 resistance

382 resistance

500 pulse width modulation devices

511 NAND gate logical circuits

512 inverters

515 D flip-flops

518 inverters

519 ANDs

520 blanking circuits

521 inverters

522 inverters

523 NAND gate logical circuits

525 current sources

526 transistors

527 electric capacity

600 adders

610 operational amplifiers

611 operational amplifiers

620 transistors

621 transistors

622 transistors

650 resistance

651 resistance

Embodiment

Fig. 1 one has the power supply unit of switching control.This power supply unit comprises a transformer 10, and this transformer 10 has auxiliary winding N _A, first side winding N _PWith secondary side winding N _SThis first side winding N _PBe connected to the input voltage V of power supply unit _INFor the stable output voltage V of adjusting power supply unit _OAnd/or output current I _O, one switches control device comprises a switching signal V _PWM, being used for controlling the power switch of a transistor 20, a controller 70 is connected in a control end of this power switch, produces this switching signal V _PWM

Fig. 2 is the various signal waveforms of power supply unit shown in Figure 1.As switching signal V _PWMBe conducting (being high level in logic), so produce primary side switch current I _PPrimary side switch peak value electric current I _P1Can obtain by following formula:

${\mathrm{<figure-callout\; id="1"\; label="I\; P"\; filenames="Y20042000979000231.png"\; state="\{\{state\}\}">I</figure-callout>}}_P=\frac{V_{\mathrm{IN}}}{L_P}\&times;T_{\mathrm{ON}}---\left(1\right)$

L wherein _PFirst side winding N for transformer 10 _PInductance value; T _ONBe this switching signal V _PWMON time (on-time).

In case switching signal V _PWMFor ending (being low level in logic), this moment, the energy storage of transformer 10 will be sent to the secondary side of transformer 10, and passed through the output of diode rectifier 40 to power supply unit, so produce secondary side switch current I _SSecondary side switch peak value electric current I _S1Can be expressed as:

$I_{S1}=\frac{(V_O+V_F)}{L_S}\&times;T_{\mathrm{DS}}---\left(2\right)$

V wherein _OOutput voltage for power supply unit; V _FForward pressure drop (forward voltage drop) for diode rectifier 40; L _SSecondary side winding N for transformer 10 _SInductance value; T _DSBe the discharge time of transformer 10, also can be expressed as secondary side switch current I _SDischarge time.

Simultaneously, at the auxiliary winding N of transformer 10 _ALast generation one voltage signal V _AUX, this voltage signal V _AUXA voltage level V _AUX1Be expressed as:

$V_{\mathrm{AUX}}=\frac{T_{\mathrm{NA}}}{T_{\mathrm{NS}}}\&times;(V_O+V_F)---\left(3\right)$

T wherein _NAWith T _NSBe respectively the auxiliary winding N of this transformer 10 _AWith secondary side winding N _SUmber of turn.

As secondary side switch current I _SWhen dropping to zero, auxiliary winding N _AThe voltage signal V that is produced _AUXBegin to reduce.This also the energy storage of indication transformer 10 fully discharge in this moment.Therefore, the discharge time of equation (2) TDS can be by this switching signal V _PWMDrop edge (falling edge) to voltage signal V _AUXThe corner that begins to descend (comer) measures, as shown in Figure 2.Primary side switch current I _PPeak current I _P1With the umber of turn of transformer 10 can be with deciding secondary side switch current I _SPeak current I _S1Secondary side switch current I _SPeak current I _S1Can be expressed as:

$I_{S1}=\frac{T_{\mathrm{NP}}}{T_{\mathrm{NS}}}\&times;I_{P1}---\left(4\right)$

T wherein _NPFirst side winding N for this transformer 10 _PUmber of turn.

As shown in Figure 1, this controller 70 comprises power source supply end (supply terminal) VCC, earth terminal (ground terminal) GND, sense terminal (detection terminal) DET, output (outputterminal) OUT, sense terminals (sense terminal) CS and voltage compensation end (voltage-compensationterminal) COMV.Power source supply end VCC and earth terminal GND are used to provide the power supply of this controller 70.One resistance 50 is connected with 51 and is formed a voltage divider (voltage divider), and two resistance are connected to the auxiliary winding N of transformer 10 _AAnd between the ground connection reference level.The sense terminal DET of this controller 70 is connected to the junction of resistance 50 and resistance 51.Produce a voltage V at sense terminal DET _DETCan obtain:

$V_{\mathrm{DET}}=\frac{R_{51}}{{\mathrm{<figure-callout\; id="50"\; label="R"\; filenames="Y20042000979000221.png"\; state="\{\{state\}\}">R</figure-callout>}}_{50}+{\mathrm{<figure-callout\; id="51"\; label="R"\; filenames="Y20042000979000221.png"\; state="\{\{state\}\}">R</figure-callout>}}_{51}}\&times;V_{\mathrm{AUX}}---\left(5\right)$

R wherein ₅₀With R ₅₁Resistance value for resistance 50 and 51.

By diode rectifier 60, this voltage signal V _AUXAgain electric capacity 65 is charged, be used to provide the power source supply end VCC that power supply is given this controller 70.One current sensing resistor 30 is connected to the earth terminal reference level by the source electrode (source) of transistor 20, is used for changing primary side switch current I _PBecome a current signal V by transistor 20 _CSThe sense terminals CS of this controller 70 is connected to this current sensing resistor 30, is used for detecting this current signal V _CSThe output OUT of this controller 70 provides this switching signal V _PWM, be used for switching this transformer 10.One voltage compensation end COMV is connected to compensating network, is used for voltage circuit frequency compensation (voltage-loop frequency compensation).This compensating network can use electric capacity such as electric capacity 31 to be connected to the earth terminal reference level.

Fig. 3 is the controller 70 according to preferred embodiment of the present invention.In conjunction with Fig. 1 and Fig. 3, at sense terminal DET, this controller 70 comprises a voltage-waveform detector 100.By a voltage divider, this voltage-waveform detector 100 is connected to the auxiliary winding N of this transformer 10 _AAuxiliary winding N by this transformer 10 _A, this voltage-waveform detector 100 is by this voltage V that repeatedly takes a sample _DETTDS and export voltage feedback signal V discharge time with this transformer _FBThis voltage-waveform detector 100 this voltage feedback signal of output V _FBTo the negative terminal input of operational amplifier 71, the anode input of this operational amplifier 71 connects a reference voltage V _R1This operational amplifier 71 and this reference voltage V _R1Form the voltage circuit error amplifier, be used for amplifying voltage feedback signal V _FB, and produce a control signal V _CTROne voltage circuit error amplifier is connected to this voltage-waveform detector 100, is made up of first operational amplifier 71 and the first reference voltage VR1, is used for amplifying this voltage feedback signal V _FBWith this control signal of generation V _CTR

One deadline modulator 300 be connected to this voltage circuit error amplifier, receive this control signal V _CTRWith a mistake low voltage signal V _UVBe used for exporting a discharging current signal I _DWith a standby signal V _STBWherein reduce this discharging current signal I _DBe proportional to this control signal V _CTRReduce.This crosses low voltage signal V _UVRepresent a lower supply voltage V _CCOutput to this controller 70, and reduce this switching signal V simultaneously _PWMDeadline.One oscillator 200 is connected to this of modulator 300 deadline, receives this of modulator discharging current signal I of 300 deadline _D, be used for exporting a pulse signal PLS and a ramp signal RMP.This pulse signal PLS is used for this switching signal of initialization (initial) V _PWMWith this switching signal of decision V _PWMDeadline, and the pulse duration that increases of this pulse signal PLS and the discharging current signal of minimizing are directly proportional.

One adder 600 connects current sensing resistor 30 and this oscillator 200, receives this current signal V _CSWith this ramp signal RMP, be used for exporting a slope signal (slope signal) V _SLPThis adder 600 is by this current signal V _CSProduce this slope signal V with the addition of this ramp signal RMP _SLP, the effect of this slope signal is that voltage circuit is formed slope-compensation (slope compensation).This current sensing resistor 30 outputs one comparator 75, this comparator 75 and reference voltage V _R2Form a peak current limiter (peak-current limiter), be used for limiting primary side switch current I _PMaximum.The input of this peak current limiter is connected to the sense terminals CS of controller 70, is used for detecting this current signal V _CS, and reach periodic (cycle-by-cycle) electric current restriction.

This operational amplifier 71 has the characteristic of conduction (trans-conductance) output.The output of this operational amplifier 71 is connected to the anode input of this voltage compensation end COMV and comparator 73.The negative terminal input of comparator 73 is connected to the output of adder 600.

Be connected to comparator 73 and comparator 75 by NAND gate logical circuit 79, one pulse width modulation devices 500.This pulse width modulation device 500 also is connected to this voltage circuit error amplifier, this modulator 300, this oscillator 200 and this adder deadline, receive this control signal, this standby signal, this pulse signal and this slope signal and produce this switching signal, and control this switching signal V according to the output of this voltage circuit error amplifier and the output of this peak current limiter _PWMPulse duration.This NAND gate logical circuit 79 produces a reset signal (resetsignal) RST according to the output of comparator 73 and comparator 75, and this switching signal V is used for resetting _PWMThis switching signal V _PWMDeadline increase the pulse duration be proportional to this pulse signal and increase.For this voltage signal of repeatedly taking a sample, this standby signal is further controlled this switching signal V _PWMDeadline, be used for keeping this switching signal V _PWMSwitching frequency with a minimum switches this transformer.According to the minimizing of load, this switching signal V _PWMDeadline increase, and reduce switching frequency.Therefore, under the underloading condition, can reduce power loss.

Main purpose of the present utility model is under the demand that does not have optical coupler and secondary side voltage stabilizing adjuster, provides one to switch control device in side, is used for accurately controlling the output voltage of power supply unit.In addition, the utility model also proposes modulation deadline, is used for reducing switching frequency, reduces the power loss of power supply unit simultaneously under the underloading condition.

The composition of one voltage control loop is by this voltage signal V _AUXBe sampled to this switching signal V _PWMPulse width modulation, according to reference voltage V _R1Control voltage signal V _AUXAmplitude (magnitude).This voltage signal V _AUXVoltage level V _AUX1With output voltage V _OBe the corresponding relation of equal proportion, shown in equation (3).This voltage signal V _AUXShown in equation (5), decay to this voltage V again _DETBy this voltage V _DETRepeatedly sampling, this voltage-waveform detector 100 produces this voltage feedback signal V _FBBy the stable adjustment of voltage control loop, according to this reference voltage V _R1Numerical value control this voltage feedback signal V _FBNumerical value.This voltage circuit error amplifier and this pulse width modulation device provide loop gain for voltage control loop.Therefore, output voltage V _OCan be reduced to:

$V_O=(\frac{{\mathrm{<figure-callout\; id="50"\; label="R"\; filenames="Y20042000979000221.png"\; state="\{\{state\}\}">R</figure-callout>}}_{50}+R_{51}}{{\mathrm{<figure-callout\; id="51"\; label="R"\; filenames="Y20042000979000221.png"\; state="\{\{state\}\}">R</figure-callout>}}_{51}}\&times;\frac{T_{\mathrm{NS}}}{T_{\mathrm{NA}}}\&times;V_{R1})-V_F---\left(6\right)$

By this voltage-waveform detector 100 this voltage signal V that repeatedly takes a sample _AUXAt secondary side switch current I _SDropped to before zero this voltage signal V _AUXSampled immediately with measure.Therefore, secondary side switch current I _SChange can't influence the forward pressure drop V of diode rectifier 40 _FNumerical value.

Fig. 4 is the voltage-waveform detector 100 according to preferred embodiment of the present utility model.One sampling pulse generator (sample-pulse generator) 190 produces a sample-pulse signal, is used for reaching the repeatedly action of sampling.One critical value signal (threshold signal) 156 adds this voltage signal V _AUXProduce a level shift reflected signal (level-shifi reflected signal).First signal generator comprises D flip-flop 171, AND 165 and 166, is used for producing the first sampled signal V _SP1With the second sampled signal V _SP2The secondary signal generator comprises D flip-flop 170, NAND gate logical circuit 163, AND 164 and comparator 155, is used for producing this discharge time signal S _DS

One time delay circuit (time-delay circuit) comprises inverter 162, current source 180, transistor 181 and electric capacity 182.As this switching signal V _PWMDuring in logic low level, be used for producing one time of delay T _dThe input of inverter 161 is by this switching signal V _PWMInstitute provides.The output of this inverter 161 is connected to the input of inverter 162, also is connected to the first input end of AND 164 and the frequency input (clock-input) of D flip-flop 170 simultaneously.But the output conducting of this inverter 162 or "off" transistor 181.Electric capacity 182 is connected in the drain electrode and the source electrode of transistor 181, and the drain electrode of this transistor 181 also is the output of time delay circuit.182 chargings of 180 pairs of electric capacity of this current source.Therefore, the capacitance of the electric current of this current source 180 and electric capacity 182 determines T time of delay of this time delay circuit _dDraw (pull high) to supply voltage V on the D input of D flip-flop 170 _CCThe output of D flip-flop 170 is connected to second input of AND 164, this AND 164 output discharge time signal S _DS

As this switching signal V _PWMBe low level in logic, this discharge time signal S _DSThereby be initiate mode.The output of this NAND gate logical circuit 163 is connected in the replacement input (reset-input) of this D flip-flop 170.Two inputs of NAND gate logical circuit 163 are connected to the output of time delay circuit and the output of comparator 155 respectively.The negative terminal input of this comparator 155 is provided by the level shift reflected signal, and the anode input of comparator 155 is by voltage feedback signal V _FBInstitute provides.Therefore, at T time of delay _dAfterwards, in case the level shift reflected signal is lower than this voltage feedback signal V _FB, this discharge time signal S _DSBe dead status.In addition, as long as switching signal V _PWMFor enabling this discharge time signal S _DSIt also is dead status.

The sample-pulse signal that sampling pulse generator 190 produces puts on the frequency input, AND 165 of D flip-flop 171 and 166 the 3rd input.The D input of D flip-flop 171 and inverse output terminal link together and form except that 2 counters (divide-by-two counter).The output of D flip-flop 171 and inverse output terminal are connected to second input of AND 165 and 166.This AND 165 and 166 first input end are by discharge time signal S _DSInstitute provides.AND 165 and 166 four-input terminal are connected to the output of time delay circuit.Therefore, the output by this AND 165 and 166 produces the first sampled signal V respectively _SP1With the second sampled signal V _SP2In addition, at discharge time signal S _DSThe cycle of enabling this section during, the first sampled signal V _SP1With the second sampled signal V _SP2Alternately generate.Yet, at discharge time signal S _DST time of delay of insertion at the beginning _d, be used for forbidding producing the first sampled signal V _SP1With the second sampled signal V _SP2At T time of delay _dThis section during, the first sampled signal V _SP1With the second sampled signal V _SP2Thereby be dead status.

The first sampled signal V _SP1With the second sampled signal V _SP2Control switch 121 alternately carries out change action with switch 122, simultaneously by sense terminal DET and resistive voltage divider this voltage signal V that alternately takes a sample _AUXThe same time, this voltage signal V _AUXTo the action of charging of first electric capacity 110 and second electric capacity 111, can obtain keeping voltage (firsthold voltage) and second and keep voltage (second hold voltage) respectively across first of first electric capacity 110 and second electric capacity 111.The switch 123 and first electric capacity 110 are connected in parallel, as the usefulness of first electric capacity, 110 discharges.The switch 124 and second electric capacity 111 are connected in parallel, as the usefulness of second electric capacity, 111 discharges.One buffer amplifier (buffer amplifier) comprises operational amplifier 150 and 151, diode 130, diode 131 and current source 135, is used for producing one and keeps voltage.Operational amplifier 150 and the input of 151 anode are connected to first electric capacity 110 and second electric capacity 111 respectively.Operational amplifier 150 and the input of 151 negative terminal are connected to the output of buffer amplifier.The output that outputs to buffer amplifier that diode 130 connects by operational amplifier 150, diode 131 is connected to the output of buffer amplifier by the output of operational amplifier 151.

Therefore, keeping voltage and second high voltage of keeping voltage by first obtains this and keeps voltage.This current source 135 is used for tenth skill.One switch 125 periodically is conducting to the voltage of keeping of first output capacitance 115, is used for producing voltage feedback signal V _FBThis switch 125 carries out conducting by pulse signal PLS or ends.At T time of delay _dAfterwards, the first sampled signal V _SP1With the second sampled signal V _SP2Begin to produce first and keep voltage and second and keep voltage, so can eliminate voltage signal V _AUXSurging disturb (spike interference).As switching signal V _PWMStop using, and transistor 20 ends, this moment voltage signal V _AUXWill produce abrupt voltage wave.

As secondary side switch current I _SDrop to zero, this voltage signal V _AUXBegin to descend, the detecting by comparator 155 is used for this discharge time signal S that stops using _DSThis discharge time signal S _DSPulse duration thereby with secondary side switch current I _ST discharge time _DSConfidential relation is arranged.As this discharge time signal S _DSStop using, this will make this first sampled signal V _SP1With this second sampled signal V _SP2Stop using, and the action of repeatedly sampling stops.At this moment, keep voltage, represent a final voltage (end voltage) in the output generation of buffer amplifier.This final voltage thus with this voltage signal V _AUXConfidential relation is arranged, just at secondary side switch current I _SDropped to before zero voltage signal V _AUXJust sampled.This acquisition of keeping voltage is to get first to keep the high voltage that voltage and second is kept voltage, as this voltage signal V _AUXWhen beginning to reduce, will ignore voltage signal V _AUXSampling action.

Fig. 5 is the oscillator 200 according to preferred embodiment of the present utility model.One operational amplifier 201, a resistance 210 and a transistor 250 are formed first voltage is changeed current converter (first V-to-I converter).This first voltage changes current converter according to a reference voltage V _REFAnd generation reference current I ₂₅₀Several transistors form current mirror (current mirror) as 251,252,253,254 and 255, according to reference current I ₂₅₀Output be used for producing charging current I ₂₅₃, decide electric current I ₃₂₁, decide electric current I ₃₂₅With decide electric current I ₃₂₉The drain electrode of transistor 253 produces charging current I ₂₅₃One first switch 230 is connected between the drain electrode and oscillating capacitance 215 of transistor 253.First end points of second switch 231 is connected to oscillating capacitance 215, and second end points of second switch 231 is by this discharging current signal I _DDrive.This ramp signal RMP is by being obtained across oscillating capacitance 215 two ends.The anode input of first comparator 205 is connected to oscillating capacitance 215, the first comparators 205 output pulse signal PLS, and this pulse signal PLS determines switching frequency.First end points of the 3rd switch 232 is by high critical value voltage (high threshold voltage) V _HSupply with, first end points of the 4th switch 233 is by low critical value voltage (low threshold voltage) V _LSupply with.Second end points of second end points of the 3rd switch 232 and the 4th switch 233 is connected in the negative terminal input of first comparator 205.The input of inverter 260 is connected to the output of first comparator 205, is used for producing rp pulse signal/PLS.Pulse signal PLS is used for conducting or by second switch 231 and the 4th switch 233.Rp pulse signal/PLS controls the conducting of first switch 230 and the 3rd switch 232 or ends.

Fig. 6 is the modulator 300 deadline of preferred embodiment of the present utility model.This, modulator 300 was connected to oscillator 200 deadline, was used for connecting a minimum discharging current I ₃₂₉, a maximum discharge current I ₃₂₅With a critical value electric current I ₃₂₁One operational amplifier 310, a transistor 314 and a resistance 311 form second voltage is changeed current converter.This second voltage changes current converter according to control signal V _CTRProduce a Control current I ₃₁₄This Control current I ₃₁₄Be connected to this minimum discharging current I ₃₂₉, this maximum discharge current I ₃₂₅With this critical value electric current I ₃₂₁, its objective is to be used for producing discharging current signal I _DThis Control current I ₃₁₄Delete the critical value electric current I by the current mirror of forming by transistor 315 and 316 ₃₂₁, and produce discharging current signal I _DAs control signal V _CTRReduce this discharging current signal I _DReduce.As discharging current signal I _DDuring reduction, this will make cycle and the switching signal V of pulse signal PLS _PWMDeadline increase.Yet, this minimum discharging current I ₃₂₉Decision discharging current signal I _DMinimum value.This maximum discharge current I ₃₂₅Nip discharging current signal I _DMaximum.The voltage V of this control signal _CTRBe proportional to loading condition.Therefore, when load reduces, this discharging current signal I _DAlso decrease.And this discharging current signal I _DMinimum value and maximum by nip at fixing level.

In case this control signal V _CTRBe lower than the first critical value voltage V _TH1, comparator 331 produces first by inverter 350 and enables signal.In case this control signal V _CTRBe higher than the first critical value voltage V _TH1, comparator 331 produces first disables by NAND gate logical circuit 351.In case the decay supply power voltage of this controller (attenuated supply voltage) is lower than the second critical value voltage V _TH2, comparator 332 produced low voltage signal V by NAND gate logical circuit 352 _UVThis decay supply power voltage is by supply power voltage V _CCVia the voltage of resistance 381 with resistance 382 decay back gained.One delay counter (delaycounter) 330 has T time of delay _D1In case first to enable signal be initiate mode for this, and than T time of delay _D1Also long, this delay counter produces standby and enables signal (standby-enable signal).Buffer 340, an AND 356 and 357 are formed a standby signal generator (standby-signalgenerator).This AND 356 is connected to delay counter 330, enables signal according to standby and enables standby signal V _STBThis standby signal V _STBBy AND 357, be dead status with crossing low voltage signal according to first disables.

Fig. 7 is the circuit diagram of pulse width modulation device 500 of the present utility model.Pulse width modulation device 500 comprises that a NAND gate logical circuit 511, a D flip-flop 515, an AND 519, inverter 512, inverter 518 and inverter 551 formed one switches signal generator, a blanking circuit (blanking circuit) 520 and wakes timer (wake-up timer) 550 up.Move supply voltage V in the switching signal generator on the D input of this D flip-flop 515 to _CCThis pulse signal PLS drives the input of inverter 512.The output of inverter 512 is connected to the frequency input of this D flip-flop 515, is used for enabling this switching signal V _PWMThe output of this D flip-flop 515 is connected to the first input end of AND 519, and second input of this AND 519 is connected to the output of inverter 512.AND 519 this switching signal of output V _PWMBe used for switching power supply.PLS enables when this pulse signal, this switching signal V _PWMPromptly stop using.Therefore, the pulse duration of this pulse signal PLS can be controlled this switching signal V _PWMDeadline.

The replacement input (reset-input) of this D flip-flop 515 is connected to the output of NAND gate logical circuit 511.The first input end of NAND gate logical circuit 511 is provided by reset signal (reset signal) RST, is used for periodically this switching signal V that stops using _PWMSecond input of NAND gate logical circuit 511 is connected to the output of blanking circuit 520, in case this switching signal V _PWMEnable, promptly can guarantee this switching signal V _PWMThe ON time (minimum on-time) of a minimum.The 3rd input of NAND gate logical circuit 511 is connected to the output that wakes timer 550 up by inverter 551, is used for guaranteeing switching signal V _PWMMinimum switching frequency.This switching signal V _PWMMinimum ON time will guarantee this discharge time of T _DSMinimum value, this will guarantee a suitable repeatedly sampling action, this voltage signal V is used for taking a sample in voltage-waveform detector 100 _AUXThis discharge time T _DSWith switching signal V _PWMON time T _ONClose association is arranged.With reference to equation (1), (2), (4) and (7), this discharge time T _DSCan be expressed as equation (8):

$L_S={\left(\frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}\right)}^2\&times;L_P---\left(7\right)$

$T_{\mathrm{DS}}=\left(\frac{V_{\mathrm{IN}}}{V_O+V_F}\right)\&times;\frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}\&times;T_{\mathrm{ON}}---\left(8\right)$

This switching signal generator produces this switching signal V according to this pulse signal PLS _PWM, this switching signal V wherein _PWMBe initialised according to the drop edge of this pulse signal PLS, and according to the initiate mode of this pulse signal PLS this switching signal V that stops using _PWMSo that to be provided this deadline; This switching signal generator is connected to voltage circuit error amplifier utmost point adder 600 again to obtain control signal V _CTRWith this slope signal V _SLP, be used for controlling this switching signal V _PWMPulse duration.

The input of this blanking circuit 520 is by switching signal V _PWMInstitute provides.As this switching signal V _PWMEnable, this blanking circuit 520 will produce a blanking signal (blanking signal) V _BLKForbid the replacement action of this D flip-flop 515.This blanking circuit 520 comprises a NAND gate logical circuit 523, a current source 525, an electric capacity 527, a transistor 526, inverter 521 and 522.This switching signal V _PWMPut on the input of inverter 521 and the first input end of NAND gate logical circuit 523.527 chargings of 525 pairs of electric capacity of this current source.This electric capacity 527 is connected in the drain electrode and the source electrode of this transistor 526.The output conducting of inverter 521 or by this transistor 526.The input of inverter 522 is connected to the drain electrode of this transistor 526.The output of inverter 522 is connected to second input of NAND gate logical circuit 523, the output output blanking signal V of this NAND gate logical circuit 523 _BLKThe capacitance of the electric current of this current source 525 and this electric capacity 527 determines this blanking signal V _BLKPulse duration.The input of inverter 518 is connected to the output of NAND gate logical circuit 523.The output of inverter 518 produces a clear signal (clearsignal) CLR, is used for conducting or switch shown in the 4th figure 123 and switch 124.

Switching signal V _PWMMinimum switching frequency guarantee the change action of transformer 10, this voltage signal V is used for repeatedly taking a sample _AUXThis wakes timer 550 up and is connected to modulator 300 deadline, according to standby signal V _STBProduce a wake-up signal (wake-up signal), and enable this switching signal V _PWMIf this voltage-waveform detector 100 is because output voltage V _OOvervoltage takes place and be sampled to a very high voltage, perhaps can produce a permanent reset signal RST, this will cause permanent this switching signal V of stopping using _PWMEven so, this wakes timer 550 up and will enable this switching signal V _PWMThis timer that wakes timer 550 up is counted by pulse signal PLS.This replacement input that wakes timer 550 up is by this blanking signal V _BLKSupply with.

Therefore, in case produce this switching signal V _PWM, this wakes timer 550 up and will reset with this wake-up signal.This pattern input (mode-input) that wakes timer 550 up is connected to this standby signal V _STBAs this standby signal V _STBStop using, this wakes timer 550 up will produce wake-up signal, be used for each cycle of pulse signal PLS.In case this standby signal V _STBEnable, this wakes timer 550 up will produce wake-up signal after the specific period of pulse signal PLS, so can guarantee switching signal V _PWMMinimum switching frequency.Fig. 8 is according to the circuit diagram that wakes timer 550 up of the present utility model.

Fig. 9 is the circuit diagram according to adder 600 of the present utility model.One operational amplifier 610, transistor 620, transistor 621, transistor 622 and a resistance 650 are formed tertiary voltage is changeed current converter (thirdV-to-I converter), is used for producing an electric current I according to ramp signal RMP ₆₂₂The anode input of one operational amplifier 611 is by current signal V _CSInstitute provides.The negative terminal input of this operational amplifier 611 connects with the output of this operational amplifier 611, is used for setting up this operational amplifier 611 as same buffer (buffer).The drain electrode of transistor 622 is connected to the output of this operational amplifier 611 by resistance 651.Drain electrode at transistor 622 produces this slope signal V _SLPThis slope signal V _SLPThereby with ramp signal RMP and current signal V _CSConfidential relation is arranged.

Main purpose of the present utility model is under the demand that does not have optical coupler and secondary side voltage stabilizing adjuster, provides one to switch control device in side, is used for accurately controlling the output voltage of power supply unit.In addition, the utility model also proposes modulation deadline, is used for reducing switching frequency, reduces the power loss of power supply unit simultaneously under the underloading condition.

Certainly; the utility model also can have other various embodiments; under the situation that does not deviate from the utility model spirit and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the utility model, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the utility model.

Claims (8)

1, a kind of switching control device is connected in the primary side of a transformer, and control is switched this transformer and exported a direct current electric power, it is characterized in that, includes:

One power switch, output are connected in the primary side of this transformer, and this power switch also couples an input voltage; And

One controller is connected in a control end of this power switch, and has between the off period and the switching signal of the minimum switching frequency of maintenance between this off period in to this control end output one;

This controller between this off period in, import in the auxiliary winding of this transformer repeatedly a voltage signal and a discharge time of sampling and produce a control signal, also input can reduce this control signal to increase the mistake low voltage signal of this deadline.

2, switching control device according to claim 1 is characterized in that, described controller comprises:

One voltage-waveform detector is connected with this transformer, imports in the auxiliary winding of this transformer repeatedly this discharge time of this voltage signal of sampling and this transformer and produces a voltage feedback signal;

One voltage circuit error amplifier is connected with this voltage-waveform detector, is made up of first operational amplifier and first reference voltage, and this voltage circuit error amplifier amplifies this voltage feedback signal and produces this control signal;

One deadline modulator, be connected with this voltage circuit error amplifier, receive this control signal and and cross low voltage signal, export a discharging current signal and a standby signal that a signal reduces the reduction that is proportional to this control signal;

One oscillator, with this deadline modulator be connected, receive this discharging current signal, this deadline and increase pulse duration of output one decision is proportional to the pulse signal and a ramp signal of the minimizing of this discharging current signal;

One adder is connected with a current sensing resistor, and is supplied with by this ramp signal, produces a slope signal; And

One pulse width modulation device, with this voltage circuit error amplifier, this deadline modulator, this oscillator be connected with this adder, receive this control signal, this standby signal, this pulse signal and this slope signal and produce this switching signal, stablize the pulse duration of adjusting this switching signal by this control signal and this slope signal; Be directly proportional with the pulse duration of this pulse signal the deadline of this switching signal.

3, switching control device according to claim 2 is characterized in that, this voltage-waveform detector comprises:

One sampling pulse generator produces a sample-pulse signal;

One critical value signal produces a level shift signal with this voltage signal;

One first electric capacity and one second electric capacity;

One first signal generator, produce and control one first sampled signal and one second sampled signal that two switches carry out change action respectively, this first signal generator this voltage signal of alternately taking a sample, and on this first electric capacity and this second electric capacity, alternately keeping one first and keeping voltage and one second and keep voltage;

One secondary signal generator is exported a discharge time signal, is inserted in the beginning of this discharge time signal in addition a time of delay, and this first sampled signal and this second sampled signal are dead status in during this cycle time of delay; And

One produces a buffer amplifier of keeping signal, obtains this and first keeps voltage and this second and keep the voltage union and go out to keep voltage; And

One first output capacitance, taking a sample, this is kept signal and produces this voltage feedback signal.

4, switching control device according to claim 2, it is characterized in that, the input of this voltage-waveform detector is this voltage signal of sampling repeatedly, is created in the secondary side switch current and drops to sampled and a final voltage that measures before zero, and produce this voltage feedback signal.

5, switching control device according to claim 2 is characterized in that, this, modulator comprised deadline:

An one minimum discharging current and a maximum discharge current;

One critical value electric current;

One voltage changes current converter, produces a Control current according to this control signal, and this Control current is connected to this minimum discharging current, this maximum discharge current and this critical value electric current, produces this discharging current signal; This Control current is deleted this critical value electric current, produces this discharging current signal, and this minimum discharging current determines the minimum value of this discharging current signal, the maximum of this this discharging current signal of maximum discharge current clamp;

One first critical value voltage, this control signal are lower than this first critical value voltage and then produce one first and enable signal, and this control signal is higher than this first critical value voltage and then produces one first disables;

One second critical value voltage, the decay supply power voltage of this controller are lower than this second critical value voltage and then produce this and cross low voltage signal;

One delay counter has the count delay time, and this count delay time is shorter than this and first enables signal and then export a standby and enable signal; And

One standby signal generator is connected to this delay counter, enables signal according to this standby and enables this standby signal.

6, switching control device according to claim 2 is characterized in that, this oscillator comprises:

One first voltage changes current converter, produces a charging current and reference current according to a reference voltage;

One oscillating capacitance;

One first switch, first end points of this first switch is supplied with by this charging current, and second end points of this first switch is connected to this oscillating capacitance;

One second switch, first end points of this second switch is connected to this oscillating capacitance, and second end points of this second switch is driven by this discharging current signal;

One first comparator, the non-inverting input of this first comparator is connected to this oscillating capacitance, produces this pulse signal;

One the 3rd switch, first end points of the 3rd switch is supplied with by a high critical value voltage, and second end points of the 3rd switch is connected to the inverting input of this first comparator;

One the 4th switch, first end points of the 4th switch is supplied with by a low critical value voltage, and second end points of the 4th switch is connected to the inverting input of this first comparator; And

One inverter, an input of this inverter is connected to the output of this first comparator, produces a rp pulse signal;

This pulse signal conducting or by this second switch and the 4th switch, this rp pulse signal conduction or end this first switch and the 3rd switch.

7, switching control device according to claim 1 is characterized in that, this switching signal has the ON time of a minimum of the minimum value that is used for guaranteeing this discharge time.

8, switching control device according to claim 2 is characterized in that, this pulse width modulation device comprises:

One switches signal generator, is connected to this oscillator, produces this switching signal according to this pulse signal; This switching signal is initialised according to the drop edge of this pulse signal, and stops using this switching signal so that to be provided this deadline according to the initiate mode of this pulse signal; This switching signal generator is also connected to this control signal and this slope signal of the pulse duration that is used for controlling this switching signal;

One blanking circuit according to the conducting state of this switching signal, is enabled the minimum ON time of this switching signal; And

One wakes timer up, is connected to this of modulator deadline, enables this switching signal according to this standby signal; This wakes the dead status of timer according to this standby signal up, will enable this switching cycle for each cycle of this pulse signal; This wakes timer up and enable this switching cycle after this standby signal is enabled back and the specific period at this pulse signal.

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