CN2750573Y - Fast double-error-correction Reed-Solomon code decoder - Google Patents

Abstract

The utility model discloses a fast double-error-correction Reed-Solomon code decoder, which is composed of a syndrome calculating circuit, an error number judgment circuit, an error position calculating circuit and an error amplitude calculating circuit which are connected in sequence. The decoder works on a finite field GF (2< 8 >), does not use a Chien search method and a lookup table method, adopts a fast decoding algorithm to directly calculate the position of the error according to result of a syndrome, has the advantages of simple decoding structure, low complexity of hard wares, simple control signals, high decoding speed, no influence caused by code length, etc., and is suitable for utility systems such as portable FLASH storage systems. The utility model systems require products with low power consumption, fast information gorge and disgorge and high data reliability.

Description

Fast double-error-correction Reed-solomon code decoder

Technical field

The utility model relates to a kind of a kind of chip apparatus that carries out error correction in technical fields such as digital communication, storage, network data transmission.

Background technology

In digital communication department was unified data-storage system, error control coding (Error ControlCoding) technology was used widely as data integrity protection's important means.Digital audio-video laser disc (DVD), digital broadcasting (DVB), big capacity storage systems such as (Mass-Storage) adopt Read-Solomon (Reed-Solomon is called for short RS) sign indicating number to improve the reliability and the integrality of data as error control coding more.

Some consumer application systems (as adopting the Mass-Storage system of FLASH memory) are based on the performance of product and the consideration of cost, usually with the RS sign indicating number of double-error-correction as error control coding, guarantee the reliability and the fail safe of data.They wish that the decoding circuit computational speed of RS sign indicating number is fast, and hardware realizes that cost is little.

At present, the decoding circuit for the RS sign indicating number of double-error-correction adopts two kinds of methods usually: first kind is the particular location of determining mistake with Berlekamp-Massey algorithm (perhaps Euclidian algorithm) and Chien searching algorithm.This method versatility is good, but the algorithm complexity, and hardware is realized the cost height.The Chien search method need spend the operation time that is proportional to code length, and decoding speed is slow.Second method is look-up table (look-up-table), and it is that in advance good result is left in the read-only memory (ROM), determines that wrong position is than very fast.But when code length was longer, the capacity of ROM was bigger, the hardware implementation cost height.

The decode procedure of common RS sign indicating number comprises four steps:

1. the calculating of syndrome (Syndrome);

2. utilize syndrome mistake in computation addressing multinomial (error-locator polynomial);

3. according to the wrong addressing polynomial computation position (error locations) that makes mistake;

4. calculate wrong amplitude (error magnatitude) by errors present.

Finding the solution of step 2 adopted Berlekamp-Messay algorithm or Euclidian algorithm usually.The hardware complexity number relevant with code length and error correction of realizing Berlekamp-Messay algorithm or Euclidian algorithm circuit is irrelevant.The common employing Chien searching algorithm of finding the solution of the 3rd step errors present realizes that the iterations of algorithm is proportional to code length.These decoding algorithms all fail to make full use of the less characteristics of error correction number, and the hardware costs of realization is big, and arithmetic speed is slow.

Step 2 and definite errors present of 3 can realize that also it is to utilize the look-up table of depositing errors present in advance in ROM with lookup table technology.Can draw the position of making a mistake quickly like this, but when code length is longer, need jumbo ROM, hardware costs is big.

Summary of the invention

At the shortcoming of present correction two bit-errors RS code decoders, the utility model proposes a kind of finite field gf (2 that is operated in ⁸) on, need not the Chien search method, also without the fast double-error-correction RS code decoder of directly finding the solution of look-up table ROM, it is fast that it has decoding speed, the characteristics that hardware costs is little.

A kind of fast double-error-correction Reed-solomon code decoder, decoder is made up of syndrome counting circuit (I), error number decision circuitry (II), errors present counting circuit (III) and wrong amplitude calculating circuit (IV), and for being linked in sequence; Wherein the Reed-solomon sign indicating number be RS (N, N-4), code length N is an arbitrary integer in 5～255; The input data enter syndrome counting circuit (I), after calculate syndrome S ₀, S ₁, S ₂And S ₃Judge the number that makes a mistake by error number decision circuitry (II); Calculate errors present respectively by errors present counting circuit (III) again; By wrong amplitude calculating circuit (IV), calculate errors present according to the number that makes a mistake after, calculate wrong amplitude again.

The utility model utilizes the characteristics of RS sign indicating number double-error-correction, a kind of combination directly can calculate the fast decoding algorithm of errors present from the syndrome result combination of circuits has been proposed, it is simple to have decoding architecture, advantages such as hardware complexity is low, control signal is simple, decoding speed is subjected to that code length influences soon and not, be very suitable for requiring in product is low in energy consumption, information throughput is fast and data reliability the is high application system, in portable FLASH storage system product.

Description of drawings

Fig. 1 is a finite field gf (2 ⁸) quadratic equation z ²The solving circuit block diagram of+z+K=0 root;

Fig. 2 is a finite field gf (2 ⁸) quadratic equation z ²A kind of implementation of the root solving circuit of+z+K=0;

Fig. 3 is quick Reed-Solomon decoder circuit block diagram.

Fig. 4 is that FLASH memory 528 byte datas are divided figure.

Fig. 5 is RS (176, a 172) decoder block diagram.

Embodiment

Be located at finite field gf (2 ⁸) general type that can correct the RS sign indicating number of two mistakes is:

RS(N，N-4)

Wherein N (4＜N≤255=is a code length; N-4 is an information word length; Code distance d=5.

If r (x), c (x) and e (x) represent receiverd polynomial, code word (code word) multinomial and wrong multinomial respectively.So, satisfy between them:

r(x)＝c(x)+e(x) (1)

The definition syndrome is S _i(i=0,1,2,3), the position of supposing two mistakes is i ₁And i ₂, the amplitude of mistake is Y ₁And Y ₂So:

$S_j=X_1{X}_1^j+Y_2{X}_2^j---\left(2\right)$

In the formula,

${\mathrm{<figure-callout\; id="1"\; label="X"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">X</figure-callout>}}_1={\mathrm{\&alpha;}}^{{\mathrm{<figure-callout\; id="1"\; label="i"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">i</figure-callout>}}_1},$ $X_2={\mathrm{\&alpha;}}^{i_2},$ Definition addressing multinomial σ (x) is:

σ(x)＝(x-X ₁)(x-X ₂)＝x ²+σ ₁x+σ ₀ (3)

Wherein, σ ₁=X ₁+ X ₂, σ ₀=X ₁X ₂(4)

So, S ₂=S ₁σ ₁+ S ₀σ ₀(5)

S ₃＝S ₂σ ₁+S ₁σ ₀ (6)

Can draw: ${\mathrm{\&sigma;}}_0=(S_2^2+S_1{S}_3)/({\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">S</figure-callout>}}_1^2+S_0{S}_2)---\left(7\right)$

${\mathrm{\&sigma;}}_1=(S_1{S}_2+S_0{S}_3)/({\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">S</figure-callout>}}_1^2+S_0{S}_2)---\left(8\right)$

Can get by formula (2) and (4) so:

Y ₂＝(S ₀X ₁+S ₁)/σ ₁ (9)

Y ₁＝S ₀+Y ₂ (10)

The method for solving of the detection of RS sign indicating number error number, errors present and wrong amplitude is as follows:

1. if do not have wrong the generation, so

S ₀＝S ₁＝S ₂＝S ₃＝0 (11)

2., suppose that wrong position and amplitude are i if single error takes place ₁And Y ₁, it is as follows to calculate A, B and C:

$A=S_0{\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">S</figure-callout>}}_1+{\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">S</figure-callout>}}_1^2,B=S_1{S}_2+S_0{S}_3,C=S_1{S}_3+S_2^2---\left(12\right)$

So:

${\mathrm{<figure-callout\; id="0"\; label="S"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">S</figure-callout>}}_0={\mathrm{<figure-callout\; id="1"\; label="Y"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">Y</figure-callout>}}_1\&NotEqual;0,{\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">S</figure-callout>}}_1=X_1{\mathrm{<figure-callout\; id="1"\; label="Y"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">Y</figure-callout>}}_1\&NotEqual;0,S_2=X_1^2{\mathrm{<figure-callout\; id="1"\; label="Y"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">Y</figure-callout>}}_1\&NotEqual;0,S_3=X_1^3{\mathrm{<figure-callout\; id="1"\; label="Y"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">Y</figure-callout>}}_1\&NotEqual;0---\left(13\right)$

A＝0，B＝0，C＝0

So, can obtain wrong position and amplitude is:

X ₁＝S ₁/S ₀，Y ₁＝S ₀ (14)

3. if two wrong generations, the position of supposing two mistakes is i ₁And i ₂, the amplitude of mistake is Y ₁And Y ₂So:

S ₀＝X ₁+X ₂≠0

S ₁＝X ₁Y ₁+X ₂Y ₂≠0

$S_2=X_1^2{\mathrm{<figure-callout\; id="1"\; label="Y"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">Y</figure-callout>}}_1+X_2^2{Y}_2\&NotEqual;0---\left(15\right)$

$S_3=X_1^3{\mathrm{<figure-callout\; id="1"\; label="Y"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">Y</figure-callout>}}_1+X_2^3{Y}_2\&NotEqual;0$

$A=S_0{S}_2+{\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">S</figure-callout>}}_1^2=(X_1^2+X_2^2)Y_1{Y}_2\&NotEqual;0$

$B=S_1{S}_2+S_0{S}_3=({\mathrm{<figure-callout\; id="1"\; label="X"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">X</figure-callout>}}_1+X_2)({\mathrm{<figure-callout\; id="1"\; label="X"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">X</figure-callout>}}_1^2+X_2^2)Y_1{Y}_2\&NotEqual;0---\left(16\right)$

$C=S_1{S}_3+S_2^2=X_1{X}_2({\mathrm{<figure-callout\; id="1"\; label="X"\; filenames="Y200420004200.600121.png"\; state="\{\{state\}\}">X</figure-callout>}}_1^2+X_2^2)Y_1{Y}_2\&NotEqual;0$

With x=σ ₁Among the z substitution addressing multinomial σ (x), can get:

z ²+z+K＝0 (17)

In the formula, $K={\mathrm{\&sigma;}}_0/{\mathrm{\&sigma;}}_1^2.$ Two root Z of formula (17) ₁, Z ₂And the relational expression between the K is:

Z ₁[7]＝z ₂[7]＝K[4]K[2]K[1]K[0]；

Z ₁[6]＝Z ₂[6]＝K[7]K[4]K[2]K[1]K[0]；

Z ₁[5]＝Z ₂[5]＝K[6]K[4]K[3]K[2]K[1]；

z ₁[4]＝Z ₂[4]＝K[7]K[0]； (18)

Z ₁[3]＝Z ₂[3]＝K[4]K[3]K[2]K[1]；

Z ₁[2]＝Z ₂[2]＝K[6]K[4]K[3]K[0]；

Z ₁[1]＝Z ₂[1]＝K[4]K[2]K[0]；

Z ₁[0]＝0，Z ₂[0]＝1；

Fig. 1 is for finding the solution quadratic equation z ²The circuit block diagram of+z+K=0 root, wherein K[7:0] be the constant of equation, Z ₁[7:0] and Z ₂[7:0] two roots for obtaining.

Fig. 2 is a finite field gf (2 ⁸) quadratic equation z ²A kind of circuit in the solving circuit form of two roots of+z+K=0.

Obtain Z ₁And Z ₂After, can obtain errors present X ₁And X ₂Value:

X ₁＝σ ₁Z ₁，X ₂＝σ ₁Z ₂ (19)

Then can calculate wrong amplitude Y according to formula (9) and (10) ₁And Y ₂, finished the decode procedure of correcting two wrong RS sign indicating numbers.

Fig. 3 is quick Reed-Solomon decoder circuit block diagram.I is the syndrome counting circuit among the figure, and it calculates S from the decoding data of input ₀, S ₁, S ₂, S ₃II is the error number decision circuitry, and it judges the wrong number Error_Number that takes place according to the relation between the value of syndrome; III is the errors present counting circuit, and it is according to the number that makes a mistake, and calculates wrong position X respectively ₁And X ₂IV is wrong amplitude calculating circuit, and it is according to number, the position of making a mistake, and calculates wrong amplitude Y ₁And Y ₂

Be example 512 byte datas of the Mass-Storage of FLASH memory are carried out the protection of RS (176,172) code data, the utility model specific implementation method is described.

Usually the FLASH memory is that unit wipes (erase), reads (read) and writes (write) operation with page or leaf (page).Every page amount of physical memory is the 512+16=528 byte, and wherein 512 is real data, and 16 bytes can be used as the ECC protection.

The utility model adopts following method that 512 byte datas are protected:

Data are divided into three sections, and the length of first section, second section and the 3rd segment data is respectively 172 bytes, 172 bytes and 168 bytes, as shown in Figure 4.

With RS (176,172) sign indicating number every segment data is carried out the ECC protection.The block diagram of concrete RS (176,172) decoder as shown in Figure 5.

The left side is an input signal among Fig. 5, DataIn[7:0] be the decoding data of input, CLK is a work clock.The right is decoding output result, E_Count[1:0] for deciphering output, ErrAdr1[7:0] be first wrong address, ErrVal1[7:0] be first wrong amplitude, ErrAdr2[7:0] be the address of second mistake, ErrVal2[7:0] be the amplitude of second mistake.

Respectively for following three kinds of situations explanation, the decode results of RS code decoder.

Decoding when one, not having mistake

Faultless 176 byte datas (hexadecimal representation) are shown in table 1:

05	50	51	52	53	54	55	56	57	58	59	5A	5B	5C	5D	5E	5F
																	06	60	61	62	63	64	65	66	67	68	69	6A	6B	6C	6D	6E	6F
07	70	71	72	73	74	75	76	77	78	79	7A	7B	7C	7D	7E	7F
																	08	80	81	82	83	84	85	86	87	88	89	8A	8B	8C	8D	8E	8F
09	90	91	92	93	94	95	96	97	98	99	9A	9B	9C	9D	9E	9F
																	0A	A0	A1	A2	A3	A4	A5	A6	A7	A8	A9	AA	AB	88	76	76	88

The faultless 176 byte decoding data tables of table 1

In the table, front 172 bytes are information word, and last four bytes 88,76,76 and 88 are verification units.

RS (176,172) decoder working result is:

1. the result is exported in decoding

Err_Count＝0，

Err_Adr1＝0，

Err_Val1＝0，

Err_Adr2＝0，

Err_Val2＝0。

2. interpretation of result

Decode results shows that inerrancy takes place.

Two, the decoding during single error

176 byte datas (hexadecimal representation) of single error are shown in table 2:

176 byte decoding data tables of table 2 single error

In the table, the information data value 80 of address 20 is made mistakes and is 20.

Front 172 bytes are information word, and last four bytes 88,76,76 and 88 are verification units.

The decoder working result is:

1. decode results:

Err_Count＝1，

Err_Adr1＝20，

Err_Val1＝A0，

Err_Adr2＝0，

Err_Val2＝0。

2. interpretation of result

A wrong generation is arranged this moment.The data that find first wrong address Err_Adr1=20 to be stored are 80, carry out xor operation with 80 with first wrong amplitude A0, and the result is 20.

Three, two decodings when wrong

176 byte datas (hexadecimal representation) of two mistakes are shown in table 3:

176 byte decoding data tables of two mistakes of table 3

In the table, the information data value 80 of address 20 is made mistakes and be should be 20, and the information data value 90 of address 30 is made mistakes, and should be 30.

Front 172 bytes are information word, and last four bytes 88,76,76 and 88 are verification units.The decoder working result is:

1. decode results:

Err_Count＝2，

Err_Adr1＝20，

Err_Val1＝A0，

Err_Adr2＝30，

Err_Val2＝A0。

2. interpretation of result

The checking of decoding data, data 80 and first wrong amplitude A0 that first wrong address Err_Adr1=20 is stored carry out xor operation, and the result is 20; Data 90 and first wrong amplitude A0 that the address Err_Adr2=30 of second mistake is stored carry out xor operation, and the result is 30.

Claims (1)

1. fast double-error-correction Reed-solomon code decoder, it is characterized in that: decoder is made up of syndrome counting circuit (I), error number decision circuitry (II), errors present counting circuit (III) and wrong amplitude calculating circuit (IV), and for being linked in sequence; Wherein the Reed-solomon sign indicating number be RS (N, N-4), code length N is an arbitrary integer in 5～255; The input data enter syndrome counting circuit (I), after calculate syndrome S ₀, S ₁, S ₂And S ₃Judge the number that makes a mistake by error number decision circuitry (II); Calculate errors present respectively by errors present counting circuit (III) again; By wrong amplitude calculating circuit (IV), calculate errors present according to the number that makes a mistake after, calculate wrong amplitude again.

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