CN2739703Y

CN2739703Y - Data distributing card

Info

Publication number: CN2739703Y
Application number: CN 200420049991
Authority: CN
Inventors: 张光磊
Original assignee: Beijing Guangweitong Sci & Tech Development Co Ltd
Current assignee: Beijing Guangweitong Sci & Tech Development Co Ltd
Priority date: 2004-05-20
Filing date: 2004-05-20
Publication date: 2005-11-09
Anticipated expiration: 2014-05-20

Abstract

The utility model provides a data distributing card, comprising a PCI interface unit composed of a PCI interface and a PCI controller; a data caching unit composed of a plurality of FIFO chips, and a control logic unit composed of two removable and written logical chips. Each input data channel or output data channel uses one FIFO chip; one removable and written logical chip is used for controlling and reading the status of each FIFO chip, and the other removable and written logical chip is used for controlling the addressing of each FIFOchip and the reading/ writing of the data; in the process of the program transmission, the PCI controller and the control logic unit can intercommunicate; the input data from the PCI interface can be controlled to write in the FIFO chip of the input data channel or the output data channel; in the process of the program logging, the PCI controller and the control logic unit can intercommunicate, and the data which is written in each FIFO chip is controlled to be output from the PCI interface. The utility model has the advantages of high dependability, good extensibility, strong environmental adaptation, etc.

Description

The data allocations card

Technical field

The utility model relates to a kind of data allocations card, particularly relates to the special-purpose PCI plug-in card of finishing data cache and distribution function in video server system.

Background technology

Current era, development in science and technology is maked rapid progress, and cable television system is extensively popularized throughout the country, and is changed to digital form by analog form.In the digital video frequency server system, the data allocations card that needs the high-capacity and high-speed degree is responsible for the data that buffer memory will send and the data of reception, with corresponding digital video broadcasting-wired system (Digital Video Broadcasting for Cable systems, DVB-C) cooperating is to improve message transmission rate.Existing data allocations card generally adopts IPC (industrial computer) framework, though firmer, durable than common PC, when certain piece plug-in card breaks down when need changing, need shutdown and open cabinet again row change, and System Expansion is poor.

Summary of the invention

The purpose of this utility model provides a kind of data allocations card that can overcome the prior art defective, to be implemented in digital video engine (Digital Video Engine, DVE) between internal memory and the DVB-C interfacing equipment at a high speed, high capacity ground transmission digital video data, finish the conversion of message transmission rate and physical interface between the ASI interface of pci interface and DVB-C simultaneously.

Concrete technical scheme of the present utility model is as described below:

A kind of data allocations card, comprise pci interface unit, data buffer storage unit and steering logic unit, the pci interface unit comprises pci interface and pci controller, data buffer storage unit comprises a plurality of fifo chips, every road inputs or outputs data channel and uses a slice fifo chip, the steering logic unit comprises can deleting for two can write logic chip, a slice can be deleted and can be write the state that logic chip is used for controlling and reading each fifo chip, and another sheet can be deleted and can write addressing and the data read/write that logic chip is used for controlling each fifo chip; In the program broadcast process, pci controller intercoms mutually with deleting programmable logic chip, and control will write the fifo chip that respectively inputs or outputs data channel from the data of pci interface input by direct memory access mode; In the program typing process, pci controller intercoms mutually with deleting programmable logic chip, and the data that control will write in each fifo chip are exported from pci interface by direct memory access mode.

The PCI-9656 controller that pci controller is produced for PLX company.

High capacity, high speed FIFO chip id T72V36110 that fifo chip is produced for IDT company.

The deleting of state that is used for controlling and read each fifo chip can be write the EPLD chip ispMACH4256 that logic chip is produced for Lattice company.

The addressing and the deleting of data read/write that are used for controlling each fifo chip can be write the EPLD chip ispMACH4128 that logic chip is produced for Lattice company.

The multichannel data output channel is by time division way shared data output interface.

The data input channel exclusively enjoys Data Input Interface.

The physical arrangement of data allocations card of the present utility model meets in the Compact PCI standard definition to the PMC module.Compact PCI framework; have advantages such as reliability height, extensibility is good, environmental suitability is strong; compare with the IPC framework; when certain piece plug-in card breaks down the needs replacing; because Compact PCI framework is supported hot plug; can under non-stop-machine situation, change plug-in card at any time, need not shutdown row replacing again.

Though the unit cost of sharing when the power system capacity that adopts Compact PCI framework is less is higher, because System Expansion is good, so the unit cost that power system capacity is shared when big descends on the contrary.

Description of drawings

The digital video services system schematic that Fig. 1 relates to for the utility model.

Fig. 2 is a structural representation of the present utility model.

Embodiment

As shown in Figure 1, when system works, digital video engine main frame (Digital Video EngineHost, DVEH) control figure video engine (DVE) is finished download, broadcast and the typing task of program; DVE by small computer system interface (Small Computer Systems Interface, SCSI) (Redundant Array of Independent Disks RAID), finishes the read/write of program data to adapter visit disk array; When program was downloaded, program data was transferred to DVEH by LAN (Local Area Network) from nearline storage equipment, give DVE by the pci bus of DVEH inside again, and DVE writes disk array by the scsi interface adapter again; When program broadcasts, program data is by direct memory access (DMA) (DirectMemory Access, DMA) mode is read in the internal memory of DVE, after the multiple connection computing, write in the fifo chip that respectively inputs or outputs data channel by the pci controller on the high-speed high capacity data allocations card by direct memory access mode again, read by the control of the programmable logic chip in the DVB-C card extender, send through ASI and send into network after chip is handled; Section directory is fashionable, program data is handled through the ASI receiving chip, by writing among the input channel FIFO of high-speed high capacity data allocations card after the detection of the programmable logic chip in the DVB-C card extender, send into the internal memory of DVE by pci controller by dma mode again, DVE handles the back accordingly and writes the RAID disk array by the scsi interface adapter.

Of the present utility modelly to the effect that make pci controller and peripheral circuit co-ordination, design the control that corresponding logical circuit is shared with the read-write control of finishing the metadata cache chip and output data timesharing.As shown in Figure 2, data allocations card of the present utility model mainly is made up of pci interface unit, data buffer storage unit and steering logic unit.

The pci interface unit comprises the PCI-9656 controller that uses PLX company to produce, can compatible 33/66MHz bus frequency and 32/64-bit highway width, be configured to the card pattern.The local bus of PCI-9656 is 33/66MHz, 32-bit, has 2 dma controllers.The pci interface clock is provided by base plate, offers each several part respectively and use behind clock buffering CY7B9910, to guarantee the control of driving force and time delay.By using independently pci controller, can maximally utilise dma mode and carry out data transmission, saved the processing resource of DVE, make it can finish the high-speed data Processing tasks smoothly.When carrying out DMA, can reach the message transmission rate of the highest 528MB/s.

High capacity, high speed FIFO chip id T72V36110 that data buffer storage unit uses IDT company to produce are operated in 36-bit to write/state that 9-bit reads.Every road I/O data are used a slice FIFO, and its capacity is 131072 * 36-bit.Because pci interface is burst by the visit of data at a high speed, and the DVB-C adapter that links to each other with the data allocations card is continuously and at a slow speed to the visit of data, and the rate-matched between them all relies on metadata cache to realize.

The EPLD chip that the steering logic unit uses Lattice company to produce realizes, the operation of being finished each fifo status control and being read by 1 ispMACH4256 is finished control to each FIFO addressing and data read/write by 1 ispMACH4128.Output channel 0～4, input channel and control/status register are addressed to 00000000H～000C0000H respectively, and step-length is 00020000H.Five output channels are by time division way shared data output interface, and the clock frequency of this data output channel is 27MHz, and data width is 8-bits, so the maximum output speed of each output channel is 43.2Mbps.Data Input Interface then exclusively enjoys for input channel, clock frequency and the data width same with output interface, so the maximum input rate of input channel support is 216Mbps.Pci interface of the present utility model can be realized the DMA transfer rate of 528MB/s.

Claims

1, a kind of data allocations card, it is characterized in that: comprise pci interface unit, data buffer storage unit and steering logic unit, the pci interface unit comprises pci interface and pci controller, data buffer storage unit comprises a plurality of fifo chips, every road inputs or outputs data channel and uses a slice fifo chip, the steering logic unit comprises can deleting for two can write logic chip, a slice can be deleted and can be write the state that logic chip is used for controlling and reading each fifo chip, and another sheet can be deleted and can write addressing and the data read/write that logic chip is used for controlling each fifo chip; In the program broadcast process, pci controller intercoms mutually with deleting programmable logic chip, and control will write the fifo chip that respectively inputs or outputs data channel from the data of pci interface input by direct memory access mode; In the program typing process, pci controller intercoms mutually with deleting programmable logic chip, and the data that control will write in each fifo chip are exported from pci interface by direct memory access mode.

2, a kind of data allocations card according to claim 1 is characterized in that: the PCI-9656 controller that described pci controller is produced for PLX company.

3, a kind of data allocations card according to claim 1 is characterized in that: high capacity, high speed FIFO chip id T72V36110 that described fifo chip is produced for IDT company.

4, a kind of data allocations card according to claim 1 is characterized in that: the EPLD chip that the steering logic unit produces for Lattice company.

5, a kind of data allocations card according to claim 1 is characterized in that: the deleting of state that is used for controlling and read each fifo chip can be write the EPLD chip ispMACH4256 that logic chip is produced for Lattice company.

6, a kind of data allocations card according to claim 1 is characterized in that: the addressing and the deleting of data read/write that are used for controlling each fifo chip can be write the EPLD chip ispMACH4128 that logic chip is produced for Lattice company.

7, a kind of data allocations card according to claim 1 is characterized in that: the multichannel data output channel is by time division way shared data output interface.

8, a kind of data allocations card according to claim 1, it is characterized in that: the data input channel exclusively enjoys Data Input Interface.