CN2738474Y - Isolated circuit on IIC bus - Google Patents
Isolated circuit on IIC bus Download PDFInfo
- Publication number
- CN2738474Y CN2738474Y CN 200420097525 CN200420097525U CN2738474Y CN 2738474 Y CN2738474 Y CN 2738474Y CN 200420097525 CN200420097525 CN 200420097525 CN 200420097525 U CN200420097525 U CN 200420097525U CN 2738474 Y CN2738474 Y CN 2738474Y
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- CN
- China
- Prior art keywords
- bus
- iic bus
- buffer circuit
- circuit
- iic
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
The utility model discloses an isolated circuit on IIC bus which comprises CPU. The CPU is connected with integrated-circuit chips through the IIC bus. In stand-by states, the bus ports of the integrated-circuit chips are in low-resistance states. The IIC bus is connectedly provided with an isolated circuit in stand-by states which excludes the integrated-circuit chips whose bus ports are in the low-resistance states from the IIC bus, which avoids abnormality of machines caused by lowly drawn electric potential of the bus. The isolated circuit has simple structure. Compared with some other circuits or special-purpose integrated chips and in times of reducing the cost of production, the isolated circuit eliminates completely abnormal problems that were constantly encountered in stand-by states and effectively assures normal work of complete machine and increases system reliability.
Description
Technical field
The utility model relates to a kind of buffer circuit, specifically, relates to a kind of buffer circuit that is used on the household electrical appliance iic bus.
Background technology
At present, in household electrical appliance such as existing television set, general CPU controls each other functional integrated circuit chip co-ordinations by iic bus.If machine is in holding state, iic bus should be in the wait state of high level, at this moment, if a certain peripheral integrated circuit (IC) chip is arranged when holding state, its bus connection port is not to be in high-impedance state, but a little resistance is arranged over the ground, at this moment, will drag down the current potential of iic bus, can't realize that under holding state controlling main power source by CPU powers on, cause the machine can't operate as normal.
Summary of the invention
Be low resistance state in order to overcome in the prior art some integrated circuit (IC) chip its bus connection port when the holding state, thereby the iic bus current potential is dragged down, cause the deficiency that machine can't operate as normal, the utility model provides a kind of buffer circuit, this buffer circuit is connected on the iic bus, when holding state, realize effective isolation of iic bus and low resistance state integrated circuit (IC) chip, thereby guaranteed the operate as normal of complete machine.
For solving the problems of the technologies described above, the utility model is achieved by the following technical programs:
A kind of buffer circuit that is used on the iic bus, comprise CPU, described CPU links to each other with integrated circuit (IC) chip by iic bus, described integrated circuit (IC) chip its bus port when holding state is low resistive state, be connected with a buffer circuit on described iic bus, described buffer circuit is iic bus and bus port the integrated circuit (IC) chip of low resistance state and cuts off when the machine standby.
As a preferred embodiment of the present utility model, described buffer circuit includes two N-channel MOS pipes, the grid of described metal-oxide-semiconductor all links to each other with main power source, drain electrode connects the control end and the data terminal of iic bus respectively, and source electrode connects the bus control end and the bus data end of described integrated circuit (IC) chip respectively.
The drain electrode of described metal-oxide-semiconductor links to each other with standby power through pull-up resistor, and source electrode links to each other with main power source through other pull-up resistor; In addition, the source electrode of metal-oxide-semiconductor and drain electrode are respectively through capacity earth.
Compared with prior art, advantage of the present utility model and good effect are: the utility model is by setting up buffer circuit on iic bus, use two N-channel MOS pipes to connect the bus port of iic bus and integrated circuit (IC) chip respectively, realized iic bus when standby and bus end be effective isolation of the integrated circuit (IC) chip of low resistance state, the machine of having avoided bus potential to be caused by dragging down is unusual, thereby effectively guaranteed the operate as normal of complete machine, improved the reliability of system.
Description of drawings
Fig. 1 is the concrete circuit connection diagram of buffer circuit in the utility model.
Embodiment
Below in conjunction with the drawings and specific embodiments the utility model is described in further detail.
On the iic bus that buffer circuit of the present utility model is connected with CPU links to each other, mainly N-channel MOS pipe Q100, the Q101 that is 2N7000 by two models forms, and its concrete annexation is referring to shown in Figure 1.Wherein, the grid of described metal-oxide-semiconductor Q100, Q101 links to each other with main power source+3.3V_SW, drain electrode connects the control end MSTR_SCL and the data terminal MSTR_SDA of iic bus respectively, source electrode connects the bus control end 23MSTR_SCL0 and the bus data end 23MSTR_SDA0 of integrated circuit (IC) chip respectively, and the bus port 23MSTR_SCL0 of described integrated circuit (IC) chip and 23MSTR_SDA0 are low resistive state when standby.In addition, the drain electrode of metal-oxide-semiconductor Q100, Q101 links to each other with standby power STD+3.3V through pull-up resistor R116, R117, and through capacitor C 142, C143 ground connection; Source electrode links to each other with main power source+3.3V SW through pull-up resistor R114, R115, and through capacitor C 140, C141 ground connection.
Its operation principle is: with metal-oxide-semiconductor Q100 is example, when main power source+3.3V_SW powers on, when machine is in normal operating conditions, is low level 0 if MSTR_SCL holds, and the 23MSTR_SCL0 end is clamped to 0.7V, at this moment, and V
GSGreater than threshold voltage, metal-oxide-semiconductor Q100 conducting, and then make the 23MSTR_SCL0 terminal voltage equal the MSTR_SCL terminal voltage, be low level 0.If the MSTR_SCL end is high level 1, the 23MSTR_SCL0 end is low level 0, then metal-oxide-semiconductor Q100 conducting, make the 23MSTR_SCL0 end become high level 1, at this moment, metal-oxide-semiconductor Q100 ends, because the 23MSTR_SCL0 end has pull-up resistor R114, R115, so the 23MSTR_SCL0 end is kept high level state.
When holding state, main power source disappears, and+3.3V_SW becomes 0V, at this moment, metal-oxide-semiconductor Q100 ends, and the high-low level state of source bus line port 23MSTR_SCL0 can't influence the state of the bus MSTR_SCL end of drain electrode CPU one side, thereby has realized the isolation features of expection.
The utility model by adopt above-mentioned simple circuit configuration realized iic bus when the standby and bus end be effective isolation of the integrated circuit (IC) chip of low resistance state, circuit structure is simple, dependable performance.Certainly; above-mentioned explanation is not to be to restriction of the present utility model; the utility model also is not limited in above-mentioned giving an example, and variation, remodeling, interpolation or replacement that those skilled in the art are made in essential scope of the present utility model also should belong to protection range of the present utility model.
Claims (4)
1. buffer circuit that is used on the iic bus, comprise CPU, described CPU links to each other with integrated circuit (IC) chip by iic bus, described integrated circuit (IC) chip its bus port when holding state is low resistive state, it is characterized in that: be connected with a buffer circuit on described iic bus, described buffer circuit is iic bus and bus port the integrated circuit (IC) chip of low resistance state and cuts off when the machine standby.
2. the buffer circuit that is used on the iic bus according to claim 1, it is characterized in that: described buffer circuit includes two N-channel MOS pipes, the grid of described metal-oxide-semiconductor all links to each other with main power source, drain electrode connects the control end and the data terminal of iic bus respectively, and source electrode connects the bus control end and the bus data end of described integrated circuit (IC) chip respectively.
3. the buffer circuit that is used on the iic bus according to claim 2 is characterized in that: the drain electrode of described metal-oxide-semiconductor links to each other with standby power through pull-up resistor, and source electrode links to each other with main power source through other pull-up resistor.
4. the buffer circuit that is used on the iic bus according to claim 3 is characterized in that: the source electrode of described metal-oxide-semiconductor and drain electrode are respectively through capacity earth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420097525 CN2738474Y (en) | 2004-11-05 | 2004-11-05 | Isolated circuit on IIC bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420097525 CN2738474Y (en) | 2004-11-05 | 2004-11-05 | Isolated circuit on IIC bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2738474Y true CN2738474Y (en) | 2005-11-02 |
Family
ID=35348376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200420097525 Expired - Fee Related CN2738474Y (en) | 2004-11-05 | 2004-11-05 | Isolated circuit on IIC bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2738474Y (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103792401A (en) * | 2012-10-30 | 2014-05-14 | 苏州工业园区新宏博通讯科技有限公司 | DC electricity meter board card module |
| CN108828315A (en) * | 2018-06-26 | 2018-11-16 | 努比亚技术有限公司 | Mobile terminal loudspeaker impedance measuring circuit, speaker circuit and mobile terminal |
| WO2020077857A1 (en) * | 2018-10-15 | 2020-04-23 | 深圳市华星光电技术有限公司 | Liquid crystal display circuit and display |
| CN112504460A (en) * | 2020-07-30 | 2021-03-16 | 河南科技大学 | Electronic temperature measuring box integrating harmful gas detection function |
-
2004
- 2004-11-05 CN CN 200420097525 patent/CN2738474Y/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103792401A (en) * | 2012-10-30 | 2014-05-14 | 苏州工业园区新宏博通讯科技有限公司 | DC electricity meter board card module |
| CN108828315A (en) * | 2018-06-26 | 2018-11-16 | 努比亚技术有限公司 | Mobile terminal loudspeaker impedance measuring circuit, speaker circuit and mobile terminal |
| CN108828315B (en) * | 2018-06-26 | 2020-12-08 | 浙江豪声电子科技股份有限公司 | Mobile terminal loudspeaker impedance measuring circuit, loudspeaker circuit and mobile terminal |
| WO2020077857A1 (en) * | 2018-10-15 | 2020-04-23 | 深圳市华星光电技术有限公司 | Liquid crystal display circuit and display |
| CN112504460A (en) * | 2020-07-30 | 2021-03-16 | 河南科技大学 | Electronic temperature measuring box integrating harmful gas detection function |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |